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1551 | art_zh | 1 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
2 | ;; ;; |
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3 | ;; Copyright (C) 2010 KolibriOS team. All rights reserved. ;; |
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4 | ;; Distributed under terms of the GNU General Public License ;; |
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5 | ;; ;; |
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1683 | art_zh | 6 | ;; HT.inc ;; ;; |
1551 | art_zh | 7 | ;; ;; |
8 | ;; AMD HyperTransport bus control ;; |
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9 | ;; ;; |
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1599 | art_zh | 10 | ;; art_zh |
1551 | art_zh | 11 | ;; ;; |
12 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
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13 | |||
1560 | art_zh | 14 | $Revision: 1554 $ |
1551 | art_zh | 15 | |
1599 | art_zh | 16 | NB_MISC_INDEX equ 0xF0000060 ; NB Misc indirect access |
17 | NB_MISC_DATA equ 0xF0000064 |
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18 | PCIEIND_INDEX equ 0xF00000E0 ; PCIe Core indirect config space access |
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19 | HTIU_NB_INDEX equ 0xF0000094 ; HyperTransport indirect config space access |
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1551 | art_zh | 20 | |
21 | ;============================================================================= |
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22 | ; |
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23 | ; This code is a part of Kolibri-A and will only work with AMD RS760+ chipsets |
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24 | ; |
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25 | ;============================================================================= |
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1683 | art_zh | 26 | |
27 | org $-OS_BASE ; physical addresses needed at initial stage |
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28 | |||
1560 | art_zh | 29 | align 4 |
1551 | art_zh | 30 | |
31 | ;------------------------------------------ |
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32 | ; params: al = nbconfig register# |
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33 | ; returns: eax = register content |
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34 | ; |
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35 | rs7xx_nbconfig_read_pci: |
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36 | and eax, 0x0FC ; leave register# only |
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37 | or eax, 0x80000000 ; bdf = 0:0.0 |
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38 | mov dx, 0x0CF8 ; write to index reg |
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39 | out dx, eax |
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40 | add dl, 4 |
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41 | in eax, dx |
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42 | ret |
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1560 | art_zh | 43 | align 4 |
1551 | art_zh | 44 | |
45 | rs7xx_nbconfig_flush_pci: |
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46 | mov eax, 0x0B0 ; a scratch reg |
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47 | mov dx, 0xCF8 |
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48 | out dx, eax |
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49 | ret |
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50 | |||
1560 | art_zh | 51 | align 4 |
1551 | art_zh | 52 | |
1599 | art_zh | 53 | ;------------------------------------------ |
54 | ; params: al = nbconfig register# |
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55 | ; ebx = register content |
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56 | ; |
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1551 | art_zh | 57 | rs7xx_nbconfig_write_pci: |
58 | and eax, 0x0FC ; leave register# only |
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59 | or eax, 0x80000000 ; bdf = 0:0.0 |
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60 | mov dx, 0x0CF8 ; write to index reg |
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61 | out dx, eax |
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62 | add dl, 4 |
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63 | mov eax, ebx |
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64 | out dx, eax |
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65 | ret |
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66 | |||
67 | ;*************************************************************************** |
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68 | ; Function |
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1599 | art_zh | 69 | ; rs7xx_unlock_bar3: unlocks the BAR3 register of nbconfig that |
70 | ; makes pcie config address space visible |
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71 | ; ----------------------- |
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72 | ; in: nothing out: nothing destroys: eax ebx edx |
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73 | ; |
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74 | ;*************************************************************************** |
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75 | align 4 |
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76 | rs7xx_unlock_bar3: |
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77 | mov eax, NB_MISC_INDEX |
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1683 | art_zh | 78 | mov ebx, 0x080 ; NBMISCIND:0x0; write-enable |
1599 | art_zh | 79 | call rs7xx_nbconfig_write_pci ; set index |
80 | mov eax, NB_MISC_DATA |
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81 | call rs7xx_nbconfig_read_pci ; read data |
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82 | mov ebx, eax |
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83 | and ebx, 0xFFFFFFF7 ; clear bit3 |
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84 | mov eax, NB_MISC_DATA |
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85 | call rs7xx_nbconfig_write_pci ; write it back |
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86 | mov eax, NB_MISC_INDEX |
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87 | xor ebx, ebx ; reg#0; write-locked |
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88 | call rs7xx_nbconfig_write_pci ; set index |
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89 | ret |
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90 | |||
1683 | art_zh | 91 | |
92 | |||
93 | ;*************************************************************************** |
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94 | ; Function |
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95 | ; rs7xx_pcie_init: |
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96 | ; |
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97 | ; Description |
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98 | ; PCIe extended (memory-mapped) config space detection |
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99 | ; |
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100 | ;*************************************************************************** |
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101 | |||
102 | align 4 |
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103 | |||
104 | rs7xx_pcie_init: |
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105 | call rs7xx_unlock_bar3 |
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106 | mov al, 0x7C ; NB_IOC_CFG_CNTL |
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107 | call rs7xx_nbconfig_read_pci |
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108 | mov ebx, eax |
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109 | ; call rs7xx_nbconfig_flush_pci |
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110 | test ebx, 0x20000000 ; BAR3 locked? |
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111 | jz $ |
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112 | mov al, 0x84 ; NB_PCI_ARB |
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113 | call rs7xx_nbconfig_read_pci |
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114 | shr eax,16 |
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115 | and ax, 7 ; the Bus range lays here: |
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116 | jnz @f |
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117 | mov ax, 8 ; 1=2Mb, 2=4MB, 3=8MB, 4=16MB |
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118 | @@: |
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119 | mov word[PCIe_bus_range-OS_BASE], ax ; 5=32Mb, 6=64MB, 7=128Mb, 8=256Mb |
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120 | mov cl, al |
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121 | call rs7xx_nbconfig_flush_pci |
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122 | dec cl ; <4M ? |
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123 | jz @f |
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124 | dec cl ; one PDE needed anyway |
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125 | @@: |
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126 | mov ebx, 1 |
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127 | shl ebx, cl |
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128 | mov word[mmio_pcie_cfg_pdes-OS_BASE], bx ; 1..64 PDE(s) needed, |
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129 | shl ebx, 22 |
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130 | mov dword[mmio_pcie_cfg_lim-OS_BASE], ebx ; or 4..256Mb space to map |
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131 | dec dword[mmio_pcie_cfg_lim-OS_BASE] |
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132 | |||
133 | mov al, 0x1C ; NB_BAR3_PCIEXP_MMCFG |
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134 | call rs7xx_nbconfig_read_pci |
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135 | mov ebx, eax |
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136 | call rs7xx_nbconfig_flush_pci |
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137 | mov eax, ebx |
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138 | and eax, 0xFFE00000 ; valid bits [31..21] |
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1928 | art_zh | 139 | jz $ ; invalid map! |
1683 | art_zh | 140 | .addr_found: |
141 | mov dword[mmio_pcie_cfg_addr-OS_BASE], eax ; physical address (lower 32 bits) |
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142 | add dword[mmio_pcie_cfg_lim-OS_BASE], eax |
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143 | |||
1928 | art_zh | 144 | ; ---- common mapping procedure ---- |
145 | ; (eax = phys. address of PCIe conf.space) |
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146 | ; |
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147 | map_pcie_pages: |
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3519 | art_zh | 148 | or eax, (PG_NOCACHE + PG_SHARED + PG_LARGE + PG_UW) ; UW is unsafe! |
1683 | art_zh | 149 | mov ecx, PCIe_CONFIG_SPACE ; linear address |
150 | mov ebx, ecx |
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151 | shr ebx, 20 |
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152 | add ebx, (sys_pgdir - OS_BASE) ; PgDir entry @ |
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153 | mov dl, byte[mmio_pcie_cfg_pdes-OS_BASE] ; 1 page = 4M in address space |
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154 | cmp dl, 0x34 ; =(USER_DMA_BUFFER - PCIe_CONFIG_SPACE) / 4M |
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155 | jb @f |
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156 | mov dl, 0x33 |
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157 | mov byte[mmio_pcie_cfg_pdes-OS_BASE], dl |
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158 | @@: |
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159 | xor dx, dx ; PDEs counter |
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160 | .write_pde: |
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161 | mov dword[ebx], eax ; map 4 buses |
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162 | add bx, 4 ; new PDE |
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163 | add eax, 0x400000 ; +4M phys. |
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164 | add ecx, 0x400000 ; +4M lin. |
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165 | cmp dl, byte[mmio_pcie_cfg_pdes-OS_BASE] |
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3519 | art_zh | 166 | jae pcie_cfg_mapped |
1683 | art_zh | 167 | inc dl |
168 | jmp .write_pde |
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169 | |||
1928 | art_zh | 170 | ; ---- stepping 10h CPUs and Fusion APUs: the configspace is stored in MSR_C001_0058 ---- |
171 | align 4 |
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172 | fusion_pcie_init: |
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2014 | art_zh | 173 | mov ecx, 0xC0010058 |
174 | rdmsr |
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175 | or edx, edx |
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176 | jnz $ ; PCIe is in the upper memory. Stop. |
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177 | xchg dl, al |
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1928 | art_zh | 178 | mov dword[mmio_pcie_cfg_addr-OS_BASE], eax ; store the physical address |
2014 | art_zh | 179 | mov ecx, edx |
180 | and dl, 1 |
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181 | jz $ ; bit[0] = 1 means no PCIe mapping allowed. Stop. |
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182 | shr cl, 2 ; ecx = log2(number of buses) |
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183 | mov word[PCIe_bus_range-OS_BASE], cx |
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184 | sub cl, 2 |
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185 | jae @f |
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186 | xor cl, cl |
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1928 | art_zh | 187 | @@: |
2014 | art_zh | 188 | shl edx, cl ; edx = number of 4M pages to map |
189 | mov word[mmio_pcie_cfg_pdes-OS_BASE], dx |
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190 | shl edx, 22 |
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191 | dec edx |
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192 | add edx, eax ; the upper configspace limit |
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1928 | art_zh | 193 | mov dword[mmio_pcie_cfg_lim-OS_BASE], edx |
1683 | art_zh | 194 | |
3519 | art_zh | 195 | pcie_cfg_mapped: |
1928 | art_zh | 196 | |
3519 | art_zh | 197 | create_mmio_pte: |
198 | |||
199 | mov ecx, mmio_pte ; physical address |
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200 | or ecx, (PG_NOCACHE + PG_SHARED) |
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201 | mov ebx, FUSION_MMIO ; linear address |
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202 | shr ebx, 20 |
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203 | add ebx, (sys_pgdir - OS_BASE) ; PgDir entry @ |
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204 | mov dword[ebx], ecx ; Fusion MMIO tables |
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205 | |||
206 | map_apic_mmio: |
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207 | mov ecx, 0x01B ; APIC BAR |
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208 | rdmsr |
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209 | and eax, 0xFFFFF000 ; physical address |
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210 | or eax, (PG_NOCACHE + PG_SHARED + PG_UW) ; UW is unsafe! |
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211 | mov dword[mmio_pte + 0], eax |
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212 | |||
213 | ret ; <<< OK >>> |
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214 | |||
1683 | art_zh | 215 | ; ================================================================================ |
216 | |||
217 | org OS_BASE+$ ; back to the linear address space |
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218 | |||
1599 | art_zh | 219 | ;-------------------------------------------------------------- |
220 | align 4 |
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221 | rs780_read_misc: |
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222 | ; in: eax(al) - reg# out: eax = NBMISCIND data |
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223 | push edx |
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224 | mov edx, NB_MISC_INDEX |
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225 | and eax, 0x07F |
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226 | mov [edx], eax |
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227 | add dl, 4 |
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228 | mov eax, [edx] |
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229 | pop edx |
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230 | ret |
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231 | |||
232 | ;------------------------------------------- |
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233 | align 4 |
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234 | rs780_write_misc: |
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235 | ; in: eax(al) - reg# ebx = NBMISCIND data |
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236 | push edx |
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237 | mov edx, NB_MISC_INDEX |
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238 | and eax, 0x07F |
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239 | or eax, 0x080 ; set WE |
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240 | mov [edx], eax |
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241 | add dl, 4 |
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242 | mov [edx], ebx |
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243 | sub dl, 4 |
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244 | xor eax, eax |
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245 | mov [edx], eax ; safety last |
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246 | pop edx |
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247 | ret |
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248 | |||
249 | ;------------------------------------------------------------- |
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250 | align 4 |
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251 | rs780_read_pcieind: |
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252 | ; in: ah = bridge#, al = reg# out: eax = PCIEIND data |
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253 | push edx |
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254 | xor edx, edx |
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255 | mov ah, dl ; bridge# : 0 = Core+GFX; 0x10 = Core+SB |
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256 | and dl, 15 ; 0x20 = Core+GPP; 2..12 = a PortBridge |
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257 | shl edx, 15 ; device# |
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258 | add edx, PCIEIND_INDEX ; full bdf-address |
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259 | and eax, 0x30FF |
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260 | or al, al |
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261 | jnz @f |
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262 | shl eax, 4 ; set bits 17..16 for a Core bridge |
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263 | @@: |
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264 | mov [edx], eax |
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265 | add dl, 4 |
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266 | mov eax, [edx] |
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267 | pop edx |
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268 | ret |
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269 | |||
270 | ;------------------------------------------- |
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271 | align 4 |
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272 | rs780_write_pcieind: |
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273 | ; in: ah = bridge#, al = reg#, ebx = PCIEIND data |
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274 | push edx |
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275 | xor edx, edx |
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276 | mov ah, dl ; bridge# : 0 = Core+GFX; 0x10 = Core+SB |
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277 | and dl, 15 ; 0x20 = Core+GPP; 2..12 = a PortBridge |
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278 | shl edx, 15 ; device# |
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279 | add edx, PCIEIND_INDEX ; full bdf-address |
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280 | and eax, 0x30FF |
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281 | or al, al |
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282 | jnz @f |
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283 | shl eax, 4 ; set bits 17..16 for a Core bridge |
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284 | @@: |
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285 | mov [edx], eax |
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286 | add dl, 4 |
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287 | mov [edx], ebx |
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288 | sub dl, 4 |
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289 | xor eax, eax |
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290 | mov [edx], eax ; safety last |
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291 | pop edx |
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292 | ret |
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293 | |||
294 | ;------------------------------------------------ |
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295 | align 4 |
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296 | rs780_read_htiu: |
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297 | ; in: al = reg# | out: eax = HTIU data |
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298 | ;------------------------------------------------ |
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299 | push edx |
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300 | mov edx, HTIU_NB_INDEX |
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301 | and eax, 0x07F |
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302 | mov [edx], eax |
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303 | add dl, 4 |
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304 | mov eax, [edx] |
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305 | pop edx |
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306 | ret |
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307 | ;------------------------------------------------ |
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308 | align 4 |
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309 | rs780_write_htiu: |
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310 | ; in: al = reg#; ebx = data |
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311 | ;------------------------------------------------ |
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312 | push edx |
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313 | mov edx, HTIU_NB_INDEX |
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314 | and eax, 0x07F |
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315 | or eax, 0x100 |
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316 | mov [edx], eax |
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317 | add dl, 4 |
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318 | mov [edx], ebx |
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319 | sub dl, 4 |
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320 | xor eax, eax |
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321 | mov [edx], eax |
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322 | pop edx |
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323 | ret |
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324 | |||
1928 | art_zh | 325 | ;------------------------------------------------ |
326 | align 4 |
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327 | sys_rdmsr: |
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328 | ; in: [esp+8] = MSR# |
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329 | ; out: [esp+8] = MSR[63:32] |
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330 | ; [eax] = MSR[31: 0] |
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331 | ;------------------------------------------------ |
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2014 | art_zh | 332 | push ecx edx |
333 | mov ecx, [esp+16] |
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334 | rdmsr |
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335 | mov [esp+16], edx |
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336 | pop edx ecx |
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337 | ret><><<>4M> |
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1599 | art_zh | 338 |