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1551 | art_zh | 1 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
2 | ;; ;; |
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3 | ;; Copyright (C) 2010 KolibriOS team. All rights reserved. ;; |
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4 | ;; Distributed under terms of the GNU General Public License ;; |
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5 | ;; ;; |
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6 | ;; ;; |
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7 | ;; AMD HyperTransport bus control ;; |
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8 | ;; ;; |
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1599 | art_zh | 9 | ;; art_zh |
1551 | art_zh | 10 | ;; ;; |
11 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
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12 | |||
1560 | art_zh | 13 | $Revision: 1554 $ |
1551 | art_zh | 14 | |
1599 | art_zh | 15 | NB_MISC_INDEX equ 0xF0000060 ; NB Misc indirect access |
16 | NB_MISC_DATA equ 0xF0000064 |
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17 | PCIEIND_INDEX equ 0xF00000E0 ; PCIe Core indirect config space access |
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18 | HTIU_NB_INDEX equ 0xF0000094 ; HyperTransport indirect config space access |
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1551 | art_zh | 19 | |
20 | ;============================================================================= |
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21 | ; |
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22 | ; This code is a part of Kolibri-A and will only work with AMD RS760+ chipsets |
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23 | ; |
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24 | ;============================================================================= |
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1560 | art_zh | 25 | align 4 |
1551 | art_zh | 26 | |
27 | ;------------------------------------------ |
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28 | ; params: al = nbconfig register# |
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29 | ; returns: eax = register content |
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30 | ; |
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31 | rs7xx_nbconfig_read_pci: |
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32 | and eax, 0x0FC ; leave register# only |
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33 | or eax, 0x80000000 ; bdf = 0:0.0 |
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34 | mov dx, 0x0CF8 ; write to index reg |
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35 | out dx, eax |
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36 | add dl, 4 |
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37 | in eax, dx |
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38 | ret |
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1560 | art_zh | 39 | align 4 |
1551 | art_zh | 40 | |
41 | rs7xx_nbconfig_flush_pci: |
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42 | mov eax, 0x0B0 ; a scratch reg |
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43 | mov dx, 0xCF8 |
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44 | out dx, eax |
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45 | ret |
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46 | |||
1560 | art_zh | 47 | align 4 |
1551 | art_zh | 48 | |
1599 | art_zh | 49 | ;------------------------------------------ |
50 | ; params: al = nbconfig register# |
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51 | ; ebx = register content |
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52 | ; |
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1551 | art_zh | 53 | rs7xx_nbconfig_write_pci: |
54 | and eax, 0x0FC ; leave register# only |
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55 | or eax, 0x80000000 ; bdf = 0:0.0 |
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56 | mov dx, 0x0CF8 ; write to index reg |
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57 | out dx, eax |
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58 | add dl, 4 |
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59 | mov eax, ebx |
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60 | out dx, eax |
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61 | ret |
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62 | |||
63 | ;*************************************************************************** |
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64 | ; Function |
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1599 | art_zh | 65 | ; rs7xx_unlock_bar3: unlocks the BAR3 register of nbconfig that |
66 | ; makes pcie config address space visible |
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67 | ; ----------------------- |
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68 | ; in: nothing out: nothing destroys: eax ebx edx |
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69 | ; |
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70 | ;*************************************************************************** |
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71 | align 4 |
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72 | rs7xx_unlock_bar3: |
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73 | mov eax, NB_MISC_INDEX |
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74 | mov ebx, 0x080 ; reg#0; write-enable |
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75 | call rs7xx_nbconfig_write_pci ; set index |
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76 | mov eax, NB_MISC_DATA |
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77 | call rs7xx_nbconfig_read_pci ; read data |
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78 | mov ebx, eax |
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79 | and ebx, 0xFFFFFFF7 ; clear bit3 |
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80 | mov eax, NB_MISC_DATA |
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81 | call rs7xx_nbconfig_write_pci ; write it back |
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82 | mov eax, NB_MISC_INDEX |
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83 | xor ebx, ebx ; reg#0; write-locked |
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84 | call rs7xx_nbconfig_write_pci ; set index |
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85 | ret |
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86 | |||
87 | ;-------------------------------------------------------------- |
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88 | align 4 |
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89 | rs780_read_misc: |
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90 | ; in: eax(al) - reg# out: eax = NBMISCIND data |
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91 | push edx |
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92 | mov edx, NB_MISC_INDEX |
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93 | and eax, 0x07F |
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94 | mov [edx], eax |
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95 | add dl, 4 |
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96 | mov eax, [edx] |
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97 | pop edx |
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98 | ret |
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99 | |||
100 | ;------------------------------------------- |
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101 | align 4 |
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102 | rs780_write_misc: |
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103 | ; in: eax(al) - reg# ebx = NBMISCIND data |
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104 | push edx |
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105 | mov edx, NB_MISC_INDEX |
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106 | and eax, 0x07F |
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107 | or eax, 0x080 ; set WE |
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108 | mov [edx], eax |
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109 | add dl, 4 |
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110 | mov [edx], ebx |
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111 | sub dl, 4 |
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112 | xor eax, eax |
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113 | mov [edx], eax ; safety last |
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114 | pop edx |
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115 | ret |
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116 | |||
117 | ;------------------------------------------------------------- |
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118 | align 4 |
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119 | rs780_read_pcieind: |
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120 | ; in: ah = bridge#, al = reg# out: eax = PCIEIND data |
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121 | push edx |
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122 | xor edx, edx |
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123 | mov ah, dl ; bridge# : 0 = Core+GFX; 0x10 = Core+SB |
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124 | and dl, 15 ; 0x20 = Core+GPP; 2..12 = a PortBridge |
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125 | shl edx, 15 ; device# |
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126 | add edx, PCIEIND_INDEX ; full bdf-address |
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127 | and eax, 0x30FF |
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128 | or al, al |
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129 | jnz @f |
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130 | shl eax, 4 ; set bits 17..16 for a Core bridge |
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131 | @@: |
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132 | mov [edx], eax |
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133 | add dl, 4 |
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134 | mov eax, [edx] |
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135 | pop edx |
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136 | ret |
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137 | |||
138 | ;------------------------------------------- |
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139 | align 4 |
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140 | rs780_write_pcieind: |
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141 | ; in: ah = bridge#, al = reg#, ebx = PCIEIND data |
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142 | push edx |
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143 | xor edx, edx |
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144 | mov ah, dl ; bridge# : 0 = Core+GFX; 0x10 = Core+SB |
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145 | and dl, 15 ; 0x20 = Core+GPP; 2..12 = a PortBridge |
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146 | shl edx, 15 ; device# |
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147 | add edx, PCIEIND_INDEX ; full bdf-address |
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148 | and eax, 0x30FF |
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149 | or al, al |
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150 | jnz @f |
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151 | shl eax, 4 ; set bits 17..16 for a Core bridge |
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152 | @@: |
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153 | mov [edx], eax |
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154 | add dl, 4 |
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155 | mov [edx], ebx |
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156 | sub dl, 4 |
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157 | xor eax, eax |
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158 | mov [edx], eax ; safety last |
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159 | pop edx |
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160 | ret |
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161 | |||
162 | ;------------------------------------------------ |
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163 | align 4 |
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164 | rs780_read_htiu: |
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165 | ; in: al = reg# | out: eax = HTIU data |
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166 | ;------------------------------------------------ |
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167 | push edx |
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168 | mov edx, HTIU_NB_INDEX |
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169 | and eax, 0x07F |
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170 | mov [edx], eax |
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171 | add dl, 4 |
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172 | mov eax, [edx] |
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173 | pop edx |
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174 | ret |
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175 | ;------------------------------------------------ |
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176 | align 4 |
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177 | rs780_write_htiu: |
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178 | ; in: al = reg#; ebx = data |
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179 | ;------------------------------------------------ |
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180 | push edx |
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181 | mov edx, HTIU_NB_INDEX |
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182 | and eax, 0x07F |
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183 | or eax, 0x100 |
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184 | mov [edx], eax |
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185 | add dl, 4 |
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186 | mov [edx], ebx |
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187 | sub dl, 4 |
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188 | xor eax, eax |
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189 | mov [edx], eax |
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190 | pop edx |
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191 | ret |
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192 | |||
193 | |||
194 | |||
195 | ;*************************************************************************** |
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196 | ; Function |
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1551 | art_zh | 197 | ; rs7xx_pcie_init: |
198 | ; |
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199 | ; Description |
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200 | ; PCIe extended (memory-mapped) config space detection |
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201 | ; |
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202 | ;*************************************************************************** |
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203 | |||
1560 | art_zh | 204 | align 4 |
205 | |||
1551 | art_zh | 206 | rs7xx_pcie_init: |
1599 | art_zh | 207 | call rs7xx_unlock_bar3 |
1551 | art_zh | 208 | mov al, 0x7C ; NB_IOC_CFG_CNTL |
209 | call rs7xx_nbconfig_read_pci |
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210 | mov ebx, eax |
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211 | call rs7xx_nbconfig_flush_pci |
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212 | test ebx, 0x20000000 ; BAR3 locked? |
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213 | jz .rs7xx_pcie_blocked |
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214 | mov al, 0x84 ; NB_PCI_ARB |
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215 | call rs7xx_nbconfig_read_pci |
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216 | shr eax,16 |
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217 | and ax, 7 ; the Bus range lays here: |
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218 | jnz @f |
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219 | mov ax, 8 ; 1=2Mb, 2=4MB, 3=8MB, 4=16MB |
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220 | @@: |
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221 | mov [PCIe_bus_range], ax ; 5=32Mb, 6=64MB, 7=128Mb, 8=256Mb |
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222 | mov cl, al |
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223 | call rs7xx_nbconfig_flush_pci |
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224 | dec cl ; <4M ? |
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225 | jnz @f |
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226 | inc cl ; one PDE needed anyway |
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227 | @@: |
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228 | dec cl |
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229 | mov ebx, 1 |
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230 | shl ebx, cl |
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231 | mov [mmio_pcie_cfg_pdes], bx ; 1..64 PDE(s) needed, |
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232 | shl ebx, 22 |
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233 | mov [mmio_pcie_cfg_lim], ebx ; or 4..256Mb space to map |
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234 | dec [mmio_pcie_cfg_lim] |
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235 | |||
236 | mov al, 0x1C ; NB_BAR3_PCIEXP_MMCFG |
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237 | call rs7xx_nbconfig_read_pci |
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238 | mov ebx, eax |
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239 | call rs7xx_nbconfig_flush_pci |
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240 | mov eax, ebx |
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241 | and eax, 0xFFE00000 ; valid bits [31..21] |
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1560 | art_zh | 242 | jz .rs7xx_pcie_blocked ; NB BAR3 may be invisible! |
243 | ; try to get pcie ecfg address indirectly |
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244 | .addr_found: |
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1551 | art_zh | 245 | mov [mmio_pcie_cfg_addr], eax ; physical address (lower 32 bits) |
246 | add [mmio_pcie_cfg_lim], eax |
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247 | |||
248 | or eax, (PG_SHARED + PG_LARGE + PG_UW) ; by the way, UW is unsafe! |
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249 | mov ecx, PCIe_CONFIG_SPACE ; linear address |
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250 | mov ebx, ecx |
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251 | shr ebx, 20 |
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252 | add ebx, sys_pgdir ; PgDir entry @ |
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1560 | art_zh | 253 | mov dl, byte[mmio_pcie_cfg_pdes] ; 1 page = 4M in address space |
254 | cmp dl, (USER_DMA_BUFFER - PCIe_CONFIG_SPACE) / 4194304 |
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255 | jb @f |
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256 | mov dl, ((USER_DMA_BUFFER - PCIe_CONFIG_SPACE) / 4194304) - 1 |
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257 | mov byte[mmio_pcie_cfg_pdes], dl |
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1551 | art_zh | 258 | @@: |
1560 | art_zh | 259 | xor dx, dx ; PDEs counter |
260 | @@: |
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261 | mov dword[ebx], eax ; map 4 buses |
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1551 | art_zh | 262 | add bx, 4 ; new PDE |
263 | add eax, 0x400000 ; +4M phys. |
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264 | add ecx, 0x400000 ; +4M lin. |
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1560 | art_zh | 265 | cmp dl, byte[mmio_pcie_cfg_pdes] |
266 | jnc .pcie_cfg_mapped |
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267 | inc dl |
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268 | jmp @b |
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1599 | art_zh | 269 | mov eax, cr3 |
270 | mov cr3, eax ; flush TLB |
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1551 | art_zh | 271 | .pcie_cfg_mapped: |
272 | mov esi, boot_pcie_ok |
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273 | call boot_log |
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1560 | art_zh | 274 | ret ; <<< OK >>> |
1551 | art_zh | 275 | .rs7xx_pcie_fail: |
276 | mov esi, boot_rs7xx_fail |
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277 | call boot_log |
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1599 | art_zh | 278 | jmp $ |
1551 | art_zh | 279 | .rs7xx_pcie_blocked: |
280 | mov esi, boot_rs7xx_blkd |
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281 | call boot_log |
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1599 | art_zh | 282 | jmp $><><<>4M> |
1551 | art_zh | 283 |