WebSVN – Kolibri OS – Blame – /drivers/video/radeonhd/rhd

Rev	Author	Line No.	Line
1029	serge	1	/*
		2	* Copyright 2007, 2008 Luc Verhaegen
		3	* Copyright 2007, 2008 Matthias Hopf
		4	* Copyright 2007, 2008 Egbert Eich
		5	* Copyright 2007, 2008 Advanced Micro Devices, Inc.
		6	*
		7	* Permission is hereby granted, free of charge, to any person obtaining a
		8	* copy of this software and associated documentation files (the "Software"),
		9	* to deal in the Software without restriction, including without limitation
		10	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		11	* and/or sell copies of the Software, and to permit persons to whom the
		12	* Software is furnished to do so, subject to the following conditions:
		13	*
		14	* The above copyright notice and this permission notice shall be included in
		15	* all copies or substantial portions of the Software.
		16	*
		17	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		18	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		19	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		20	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
		21	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
		22	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
		23	* OTHER DEALINGS IN THE SOFTWARE.
		24	*/
		25	#ifndef _RHD_REGS_H
		26	# define _RHD_REGS_H
		27
		28	enum {
		29	CLOCK_CNTL_INDEX = 0x8, /* (RW) */
		30	CLOCK_CNTL_DATA = 0xC, /* (RW) */
		31	BUS_CNTL = 0x4C, /* (RW) */
		32	MC_IND_INDEX = 0x70, /* (RW) */
		33	MC_IND_DATA = 0x74, /* (RW) */
		34	CONFIG_CNTL = 0xE0,
		35	/* RS690 ?? */
		36	RS60_MC_NB_MC_INDEX = 0x78,
		37	RS60_MC_NB_MC_DATA = 0x7C,
		38	RS69_MC_INDEX = 0xE8,
		39	RS69_MC_DATA = 0xEC,
		40	R5XX_CONFIG_MEMSIZE = 0x00F8,
		41
		42	HDP_FB_LOCATION = 0x0134,
		43
		44	SEPROM_CNTL1 = 0x1C0, /* (RW) */
		45
		46	AGP_BASE = 0x0170,
		47
		48	GPIOPAD_MASK = 0x198, /* (RW) */
		49	GPIOPAD_A = 0x19C, /* (RW) */
		50	GPIOPAD_EN = 0x1A0, /* (RW) */
		51	VIPH_CONTROL = 0xC40, /* (RW) */
		52
		53	ROM_CNTL = 0x1600,
		54	GENERAL_PWRMGT = 0x0618,
		55	LOW_VID_LOWER_GPIO_CNTL = 0x0724,
		56	MEDIUM_VID_LOWER_GPIO_CNTL = 0x0720,
		57	HIGH_VID_LOWER_GPIO_CNTL = 0x071C,
		58	CTXSW_VID_LOWER_GPIO_CNTL = 0x0718,
		59	LOWER_GPIO_ENABLE = 0x0710,
		60
		61	/* VGA registers */
		62	VGA_RENDER_CONTROL = 0x0300,
		63	VGA_MODE_CONTROL = 0x0308,
		64	VGA_MEMORY_BASE_ADDRESS = 0x0310,
		65	VGA_HDP_CONTROL = 0x0328,
		66	D1VGA_CONTROL = 0x0330,
		67	D2VGA_CONTROL = 0x0338,
		68
		69	EXT1_PPLL_REF_DIV_SRC = 0x0400,
		70	EXT1_PPLL_REF_DIV = 0x0404,
		71	EXT1_PPLL_UPDATE_LOCK = 0x0408,
		72	EXT1_PPLL_UPDATE_CNTL = 0x040C,
		73	EXT2_PPLL_REF_DIV_SRC = 0x0410,
		74	EXT2_PPLL_REF_DIV = 0x0414,
		75	EXT2_PPLL_UPDATE_LOCK = 0x0418,
		76	EXT2_PPLL_UPDATE_CNTL = 0x041C,
		77
		78	EXT1_PPLL_FB_DIV = 0x0430,
		79	EXT2_PPLL_FB_DIV = 0x0434,
		80	EXT1_PPLL_POST_DIV_SRC = 0x0438,
		81	EXT1_PPLL_POST_DIV = 0x043C,
		82	EXT2_PPLL_POST_DIV_SRC = 0x0440,
		83	EXT2_PPLL_POST_DIV = 0x0444,
		84	EXT1_PPLL_CNTL = 0x0448,
		85	EXT2_PPLL_CNTL = 0x044C,
		86	P1PLL_CNTL = 0x0450,
		87	P2PLL_CNTL = 0x0454,
		88	P1PLL_INT_SS_CNTL = 0x0458,
		89	P2PLL_INT_SS_CNTL = 0x045C,
		90
		91	P1PLL_DISP_CLK_CNTL = 0x0468, /* rv620+ */
		92	P2PLL_DISP_CLK_CNTL = 0x046C, /* rv620+ */
		93	EXT1_SYM_PPLL_POST_DIV = 0x0470, /* rv620+ */
		94	EXT2_SYM_PPLL_POST_DIV = 0x0474, /* rv620+ */
		95
		96	PCLK_CRTC1_CNTL = 0x0480,
		97	PCLK_CRTC2_CNTL = 0x0484,
		98
		99	/* these regs were reverse enginered,
		100	* so the chance is high that the naming is wrong
		101	* R6xx+ ??? */
		102	AUDIO_PLL1_MUL = 0x0514,
		103	AUDIO_PLL1_DIV = 0x0518,
		104	AUDIO_PLL2_MUL = 0x0524,
		105	AUDIO_PLL2_DIV = 0x0528,
		106	AUDIO_CLK_SRCSEL = 0x0534,
		107
		108	DCCG_DISP_CLK_SRCSEL = 0x0538, /* rv620+ */
		109
		110	SRBM_STATUS = 0x0E50,
		111
		112	AGP_STATUS = 0x0F5C,
		113
		114	R7XX_MC_VM_FB_LOCATION = 0x2024,
		115
		116	R6XX_MC_VM_FB_LOCATION = 0x2180,
		117	R6XX_HDP_NONSURFACE_BASE = 0x2C04,
		118	R6XX_CONFIG_MEMSIZE = 0x5428,
		119	R6XX_CONFIG_FB_BASE = 0x542C, /* AKA CONFIG_F0_BASE */
		120	/* PCI config space */
		121	PCI_CONFIG_SPACE_BASE = 0x5000,
		122	PCI_CAPABILITIES_PTR = 0x5034,
		123
		124	/* CRTC1 registers */
		125	D1CRTC_H_TOTAL = 0x6000,
		126	D1CRTC_H_BLANK_START_END = 0x6004,
		127	D1CRTC_H_SYNC_A = 0x6008,
		128	D1CRTC_H_SYNC_A_CNTL = 0x600C,
		129	D1CRTC_H_SYNC_B = 0x6010,
		130	D1CRTC_H_SYNC_B_CNTL = 0x6014,
		131
		132	D1CRTC_V_TOTAL = 0x6020,
		133	D1CRTC_V_BLANK_START_END = 0x6024,
		134	D1CRTC_V_SYNC_A = 0x6028,
		135	D1CRTC_V_SYNC_A_CNTL = 0x602C,
		136	D1CRTC_V_SYNC_B = 0x6030,
		137	D1CRTC_V_SYNC_B_CNTL = 0x6034,
		138
		139	D1CRTC_CONTROL = 0x6080,
		140	D1CRTC_BLANK_CONTROL = 0x6084,
		141	D1CRTC_INTERLACE_CONTROL = 0x6088,
		142	D1CRTC_BLACK_COLOR = 0x6098,
		143	D1CRTC_STATUS = 0x609C,
		144	D1CRTC_COUNT_CONTROL = 0x60B4,
		145
		146	/* D1GRPH registers */
		147	D1GRPH_ENABLE = 0x6100,
		148	D1GRPH_CONTROL = 0x6104,
		149	D1GRPH_LUT_SEL = 0x6108,
		150	D1GRPH_SWAP_CNTL = 0x610C,
		151	D1GRPH_PRIMARY_SURFACE_ADDRESS = 0x6110,
		152	D1GRPH_SECONDARY_SURFACE_ADDRESS = 0x6118,
		153	D1GRPH_PITCH = 0x6120,
		154	D1GRPH_SURFACE_OFFSET_X = 0x6124,
		155	D1GRPH_SURFACE_OFFSET_Y = 0x6128,
		156	D1GRPH_X_START = 0x612C,
		157	D1GRPH_Y_START = 0x6130,
		158	D1GRPH_X_END = 0x6134,
		159	D1GRPH_Y_END = 0x6138,
		160	D1GRPH_UPDATE = 0x6144,
		161
		162	/* LUT */
		163	DC_LUT_RW_SELECT = 0x6480,
		164	DC_LUT_RW_MODE = 0x6484,
		165	DC_LUT_RW_INDEX = 0x6488,
		166	DC_LUT_SEQ_COLOR = 0x648C,
		167	DC_LUT_PWL_DATA = 0x6490,
		168	DC_LUT_30_COLOR = 0x6494,
		169	DC_LUT_READ_PIPE_SELECT = 0x6498,
		170	DC_LUT_WRITE_EN_MASK = 0x649C,
		171	DC_LUT_AUTOFILL = 0x64A0,
		172
		173	/* LUTA */
		174	DC_LUTA_CONTROL = 0x64C0,
		175	DC_LUTA_BLACK_OFFSET_BLUE = 0x64C4,
		176	DC_LUTA_BLACK_OFFSET_GREEN = 0x64C8,
		177	DC_LUTA_BLACK_OFFSET_RED = 0x64CC,
		178	DC_LUTA_WHITE_OFFSET_BLUE = 0x64D0,
		179	DC_LUTA_WHITE_OFFSET_GREEN = 0x64D4,
		180	DC_LUTA_WHITE_OFFSET_RED = 0x64D8,
		181
		182	/* D1CUR */
		183	D1CUR_CONTROL = 0x6400,
		184	D1CUR_SURFACE_ADDRESS = 0x6408,
		185	D1CUR_SIZE = 0x6410,
		186	D1CUR_POSITION = 0x6414,
		187	D1CUR_HOT_SPOT = 0x6418,
		188	D1CUR_UPDATE = 0x6424,
		189
		190	/* D1MODE */
		191	D1MODE_DESKTOP_HEIGHT = 0x652C,
		192	D1MODE_VIEWPORT_START = 0x6580,
		193	D1MODE_VIEWPORT_SIZE = 0x6584,
		194	D1MODE_EXT_OVERSCAN_LEFT_RIGHT = 0x6588,
		195	D1MODE_EXT_OVERSCAN_TOP_BOTTOM = 0x658C,
		196	D1MODE_DATA_FORMAT = 0x6528,
		197
		198	/* D1SCL */
		199	D1SCL_ENABLE = 0x6590,
		200	D1SCL_TAP_CONTROL = 0x6594,
		201	D1MODE_CENTER = 0x659C, /* guess */
		202	D1SCL_HVSCALE = 0x65A4, /* guess */
		203	D1SCL_HFILTER = 0x65B0, /* guess */
		204	D1SCL_VFILTER = 0x65C0, /* guess */
		205	D1SCL_UPDATE = 0x65CC,
		206	D1SCL_DITHER = 0x65D4, /* guess */
		207	D1SCL_FLIP_CONTROL = 0x65D8, /* guess */
		208
		209	/* CRTC2 registers */
		210	D2CRTC_H_TOTAL = 0x6800,
		211	D2CRTC_H_BLANK_START_END = 0x6804,
		212	D2CRTC_H_SYNC_A = 0x6808,
		213	D2CRTC_H_SYNC_A_CNTL = 0x680C,
		214	D2CRTC_H_SYNC_B = 0x6810,
		215	D2CRTC_H_SYNC_B_CNTL = 0x6814,
		216
		217	D2CRTC_V_TOTAL = 0x6820,
		218	D2CRTC_V_BLANK_START_END = 0x6824,
		219	D2CRTC_V_SYNC_A = 0x6828,
		220	D2CRTC_V_SYNC_A_CNTL = 0x682C,
		221	D2CRTC_V_SYNC_B = 0x6830,
		222	D2CRTC_V_SYNC_B_CNTL = 0x6834,
		223
		224	D2CRTC_CONTROL = 0x6880,
		225	D2CRTC_BLANK_CONTROL = 0x6884,
		226	D2CRTC_BLACK_COLOR = 0x6898,
		227	D2CRTC_INTERLACE_CONTROL = 0x6888,
		228	D2CRTC_STATUS = 0x689C,
		229	D2CRTC_COUNT_CONTROL = 0x68B4,
		230
		231	/* D2GRPH registers */
		232	D2GRPH_ENABLE = 0x6900,
		233	D2GRPH_CONTROL = 0x6904,
		234	D2GRPH_LUT_SEL = 0x6908,
		235	D2GRPH_SWAP_CNTL = 0x690C,
		236	D2GRPH_PRIMARY_SURFACE_ADDRESS = 0x6910,
		237	D2GRPH_PITCH = 0x6920,
		238	D2GRPH_SURFACE_OFFSET_X = 0x6924,
		239	D2GRPH_SURFACE_OFFSET_Y = 0x6928,
		240	D2GRPH_X_START = 0x692C,
		241	D2GRPH_Y_START = 0x6930,
		242	D2GRPH_X_END = 0x6934,
		243	D2GRPH_Y_END = 0x6938,
		244
		245	/* LUTB */
		246	DC_LUTB_CONTROL = 0x6CC0,
		247	DC_LUTB_BLACK_OFFSET_BLUE = 0x6CC4,
		248	DC_LUTB_BLACK_OFFSET_GREEN = 0x6CC8,
		249	DC_LUTB_BLACK_OFFSET_RED = 0x6CCC,
		250	DC_LUTB_WHITE_OFFSET_BLUE = 0x6CD0,
		251	DC_LUTB_WHITE_OFFSET_GREEN = 0x6CD4,
		252	DC_LUTB_WHITE_OFFSET_RED = 0x6CD8,
		253
		254	/* D2MODE */
		255	D2MODE_DESKTOP_HEIGHT = 0x6D2C,
		256	D2MODE_VIEWPORT_START = 0x6D80,
		257	D2MODE_VIEWPORT_SIZE = 0x6D84,
		258	D2MODE_EXT_OVERSCAN_LEFT_RIGHT = 0x6D88,
		259	D2MODE_EXT_OVERSCAN_TOP_BOTTOM = 0x6D8C,
		260	D2MODE_DATA_FORMAT = 0x6D28,
		261
		262	/* D2SCL */
		263	D2SCL_ENABLE = 0x6D90,
		264	D2SCL_TAP_CONTROL = 0x6D94,
		265	D2MODE_CENTER = 0x6D9C, /* guess */
		266	D2SCL_HVSCALE = 0x6DA4, /* guess */
		267	D2SCL_HFILTER = 0x6DB0, /* guess */
		268	D2SCL_VFILTER = 0x6DC0, /* guess */
		269	D2SCL_UPDATE = 0x6DCC,
		270	D2SCL_DITHER = 0x6DD4, /* guess */
		271	D2SCL_FLIP_CONTROL = 0x6DD8, /* guess */
		272
		273	/* Audio, reverse enginered */
		274	AUDIO_ENABLE = 0x7300, /* RW */
		275	AUDIO_TIMING = 0x7344, /* RW */
		276	/* Audio params */
		277	AUDIO_VENDOR_ID = 0x7380, /* RW */
		278	AUDIO_REVISION_ID = 0x7384, /* RW */
		279	AUDIO_ROOT_NODE_COUNT = 0x7388, /* RW */
		280	AUDIO_NID1_NODE_COUNT = 0x738c, /* RW */
		281	AUDIO_NID1_TYPE = 0x7390, /* RW */
		282	AUDIO_SUPPORTED_SIZE_RATE = 0x7394, /* RW */
		283	AUDIO_SUPPORTED_CODEC = 0x7398, /* RW */
		284	AUDIO_SUPPORTED_POWER_STATES = 0x739c, /* RW */
		285	AUDIO_NID2_CAPS = 0x73a0, /* RW */
		286	AUDIO_NID3_CAPS = 0x73a4, /* RW */
		287	AUDIO_NID3_PIN_CAPS = 0x73a8, /* RW */
		288	/* Audio conn list */
		289	AUDIO_CONN_LIST_LEN = 0x73ac, /* RW */
		290	AUDIO_CONN_LIST = 0x73b0, /* RW */
		291	/* Audio verbs */
		292	AUDIO_RATE_BPS_CHANNEL = 0x73c0, /* RO */
		293	AUDIO_PLAYING = 0x73c4, /* RO */
		294	AUDIO_IMPLEMENTATION_ID = 0x73c8, /* RW */
		295	AUDIO_CONFIG_DEFAULT = 0x73cc, /* RW */
		296	AUDIO_PIN_SENSE = 0x73d0, /* RW */
		297	AUDIO_PIN_WIDGET_CNTL = 0x73d4, /* RO */
		298	AUDIO_STATUS_BITS = 0x73d8, /* RO */
		299
		300	/* HDMI */
		301	HDMI_TMDS = 0x7400,
		302	HDMI_LVTMA = 0x7700,
		303	HDMI_DIG = 0x7800,
		304
		305	/* R500 DAC A */
		306	DACA_ENABLE = 0x7800,
		307	DACA_SOURCE_SELECT = 0x7804,
		308	DACA_SYNC_TRISTATE_CONTROL = 0x7820,
		309	DACA_SYNC_SELECT = 0x7824,
		310	DACA_AUTODETECT_CONTROL = 0x7828,
		311	DACA_AUTODETECT_INT_CONTROL = 0x7838,
		312	DACA_FORCE_OUTPUT_CNTL = 0x783C,
		313	DACA_FORCE_DATA = 0x7840,
		314	DACA_POWERDOWN = 0x7850,
		315	DACA_CONTROL1 = 0x7854,
		316	DACA_CONTROL2 = 0x7858,
		317	DACA_COMPARATOR_ENABLE = 0x785C,
		318	DACA_COMPARATOR_OUTPUT = 0x7860,
		319
		320	/* TMDSA */
		321	TMDSA_CNTL = 0x7880,
		322	TMDSA_SOURCE_SELECT = 0x7884,
		323	TMDSA_COLOR_FORMAT = 0x7888,
		324	TMDSA_FORCE_OUTPUT_CNTL = 0x788C,
		325	TMDSA_BIT_DEPTH_CONTROL = 0x7894,
		326	TMDSA_DCBALANCER_CONTROL = 0x78D0,
		327	TMDSA_DATA_SYNCHRONIZATION_R500 = 0x78D8,
		328	TMDSA_DATA_SYNCHRONIZATION_R600 = 0x78DC,
		329	TMDSA_TRANSMITTER_ENABLE = 0x7904,
		330	TMDSA_LOAD_DETECT = 0x7908,
		331	TMDSA_MACRO_CONTROL = 0x790C, /* r5x0 and r600: 3 for pll and 1 for TX */
		332	TMDSA_PLL_ADJUST = 0x790C, /* rv6x0: pll only */
		333	TMDSA_TRANSMITTER_CONTROL = 0x7910,
		334	TMDSA_TRANSMITTER_ADJUST = 0x7920, /* rv6x0: TX part of macro control */
		335
		336	/* DAC B */
		337	DACB_ENABLE = 0x7A00,
		338	DACB_SOURCE_SELECT = 0x7A04,
		339	DACB_SYNC_TRISTATE_CONTROL = 0x7A20,
		340	DACB_SYNC_SELECT = 0x7A24,
		341	DACB_AUTODETECT_CONTROL = 0x7A28,
		342	DACB_AUTODETECT_INT_CONTROL = 0x7A38,
		343	DACB_FORCE_OUTPUT_CNTL = 0x7A3C,
		344	DACB_FORCE_DATA = 0x7A40,
		345	DACB_POWERDOWN = 0x7A50,
		346	DACB_CONTROL1 = 0x7A54,
		347	DACB_CONTROL2 = 0x7A58,
		348	DACB_COMPARATOR_ENABLE = 0x7A5C,
		349	DACB_COMPARATOR_OUTPUT = 0x7A60,
		350
		351	/* LVTMA */
		352	LVTMA_CNTL = 0x7A80,
		353	LVTMA_SOURCE_SELECT = 0x7A84,
		354	LVTMA_COLOR_FORMAT = 0x7A88,
		355	LVTMA_FORCE_OUTPUT_CNTL = 0x7A8C,
		356	LVTMA_BIT_DEPTH_CONTROL = 0x7A94,
		357	LVTMA_DCBALANCER_CONTROL = 0x7AD0,
		358
		359	/* no longer shared between both r5xx and r6xx */
		360	LVTMA_R500_DATA_SYNCHRONIZATION = 0x7AD8,
		361	LVTMA_R500_PWRSEQ_REF_DIV = 0x7AE4,
		362	LVTMA_R500_PWRSEQ_DELAY1 = 0x7AE8,
		363	LVTMA_R500_PWRSEQ_DELAY2 = 0x7AEC,
		364	LVTMA_R500_PWRSEQ_CNTL = 0x7AF0,
		365	LVTMA_R500_PWRSEQ_STATE = 0x7AF4,
		366	LVTMA_R500_BL_MOD_CNTL = 0x7AF8,
		367	LVTMA_R500_LVDS_DATA_CNTL = 0x7AFC,
		368	LVTMA_R500_MODE = 0x7B00,
		369	LVTMA_R500_TRANSMITTER_ENABLE = 0x7B04,
		370	LVTMA_R500_MACRO_CONTROL = 0x7B0C,
		371	LVTMA_R500_TRANSMITTER_CONTROL = 0x7B10,
		372	LVTMA_R500_REG_TEST_OUTPUT = 0x7B14,
		373
		374	/* R600 adds an undocumented register at 0x7AD8,
		375	* shifting all subsequent registers by exactly one. */
		376	LVTMA_R600_DATA_SYNCHRONIZATION = 0x7ADC,
		377	LVTMA_R600_PWRSEQ_REF_DIV = 0x7AE8,
		378	LVTMA_R600_PWRSEQ_DELAY1 = 0x7AEC,
		379	LVTMA_R600_PWRSEQ_DELAY2 = 0x7AF0,
		380	LVTMA_R600_PWRSEQ_CNTL = 0x7AF4,
		381	LVTMA_R600_PWRSEQ_STATE = 0x7AF8,
		382	LVTMA_R600_BL_MOD_CNTL = 0x7AFC,
		383	LVTMA_R600_LVDS_DATA_CNTL = 0x7B00,
		384	LVTMA_R600_MODE = 0x7B04,
		385	LVTMA_R600_TRANSMITTER_ENABLE = 0x7B08,
		386	LVTMA_R600_MACRO_CONTROL = 0x7B10,
		387	LVTMA_R600_TRANSMITTER_CONTROL = 0x7B14,
		388	LVTMA_R600_REG_TEST_OUTPUT = 0x7B18,
		389
		390	LVTMA_TRANSMITTER_ADJUST = 0x7B24, /* RV630 */
		391	LVTMA_PREEMPHASIS_CONTROL = 0x7B28, /* RV630 */
		392
		393	/* I2C in separate enum */
		394
		395	/* HPD */
		396	DC_GPIO_HPD_MASK = 0x7E90,
		397	DC_GPIO_HPD_A = 0x7E94,
		398	DC_GPIO_HPD_EN = 0x7E98,
		399	DC_GPIO_HPD_Y = 0x7E9C
		400	};
		401
		402	enum CONFIG_CNTL_BITS {
		403	RS69_CFG_ATI_REV_ID_SHIFT = 8,
		404	RS69_CFG_ATI_REV_ID_MASK = 0xF << RS69_CFG_ATI_REV_ID_SHIFT
		405	};
		406
		407	enum rv620Regs {
		408	/* DAC common */
		409	RV620_DAC_COMPARATOR_MISC = 0x7da4,
		410	RV620_DAC_COMPARATOR_OUTPUT = 0x7da8,
		411
		412	/* RV620 DAC A */
		413	RV620_DACA_ENABLE = 0x7000,
		414	RV620_DACA_SOURCE_SELECT = 0x7004,
		415	RV620_DACA_SYNC_TRISTATE_CONTROL = 0x7020,
		416	/* RV620_DACA_SYNC_SELECT = 0x7024, ?? */
		417	RV620_DACA_AUTODETECT_CONTROL = 0x7028,
		418	RV620_DACA_AUTODETECT_STATUS = 0x7034,
		419	RV620_DACA_AUTODETECT_INT_CONTROL = 0x7038,
		420	RV620_DACA_FORCE_OUTPUT_CNTL = 0x703C,
		421	RV620_DACA_FORCE_DATA = 0x7040,
		422	RV620_DACA_POWERDOWN = 0x7050,
		423	/* RV620_DACA_CONTROL1 moved */
		424	RV620_DACA_CONTROL2 = 0x7058,
		425	RV620_DACA_COMPARATOR_ENABLE = 0x705C,
		426	/* RV620_DACA_COMPARATOR_OUTPUT changed */
		427	RV620_DACA_BGADJ_SRC = 0x7ef0,
		428	RV620_DACA_MACRO_CNTL = 0x7ef4,
		429	RV620_DACA_AUTO_CALIB_CONTROL = 0x7ef8,
		430
		431	/* DAC B */
		432	RV620_DACB_ENABLE = 0x7100,
		433	RV620_DACB_SOURCE_SELECT = 0x7104,
		434	RV620_DACB_SYNC_TRISTATE_CONTROL = 0x7120,
		435	/* RV620_DACB_SYNC_SELECT = 0x7124, ?? */
		436	RV620_DACB_AUTODETECT_CONTROL = 0x7128,
		437	RV620_DACB_AUTODETECT_STATUS = 0x7134,
		438	RV620_DACB_AUTODETECT_INT_CONTROL = 0x7138,
		439	RV620_DACB_FORCE_OUTPUT_CNTL = 0x713C,
		440	RV620_DACB_FORCE_DATA = 0x7140,
		441	RV620_DACB_POWERDOWN = 0x7150,
		442	/* RV620_DACB_CONTROL1 moved */
		443	RV620_DACB_CONTROL2 = 0x7158,
		444	RV620_DACB_COMPARATOR_ENABLE = 0x715C,
		445	RV620_DACB_BGADJ_SRC = 0x7ef0,
		446	RV620_DACB_MACRO_CNTL = 0x7ff4,
		447	RV620_DACB_AUTO_CALIB_CONTROL = 0x7ef8,
		448	/* DIG1 */
		449	RV620_DIG1_CNTL = 0x75A0,
		450	RV620_DIG1_CLOCK_PATTERN = 0x75AC,
		451	RV620_LVDS1_DATA_CNTL = 0x75BC,
		452	RV620_TMDS1_CNTL = 0x75C0,
		453	/* DIG2 */
		454	RV620_DIG2_CNTL = 0x79A0,
		455	RV620_DIG2_CLOCK_PATTERN = 0x79AC,
		456	RV620_LVDS2_DATA_CNTL = 0x79BC,
		457	RV620_TMDS2_CNTL = 0x79C0,
		458
		459	/* RV62x I2C */
		460	RV62_GENERIC_I2C_CONTROL = 0x7d80, /* (RW) */
		461	RV62_GENERIC_I2C_INTERRUPT_CONTROL = 0x7d84, /* (RW) */
		462	RV62_GENERIC_I2C_STATUS = 0x7d88, /* (RW) */
		463	RV62_GENERIC_I2C_SPEED = 0x7d8c, /* (RW) */
		464	RV62_GENERIC_I2C_SETUP = 0x7d90, /* (RW) */
		465	RV62_GENERIC_I2C_TRANSACTION = 0x7d94, /* (RW) */
		466	RV62_GENERIC_I2C_DATA = 0x7d98, /* (RW) */
		467	RV62_GENERIC_I2C_PIN_SELECTION = 0x7d9c, /* (RW) */
		468	RV62_DC_GPIO_DDC4_MASK = 0x7e20, /* (RW) */
		469	RV62_DC_GPIO_DDC1_MASK = 0x7e40, /* (RW) */
		470	RV62_DC_GPIO_DDC2_MASK = 0x7e50, /* (RW) */
		471	RV62_DC_GPIO_DDC3_MASK = 0x7e60, /* (RW) */
		472
		473	/* ?? */
		474	RV620_DCIO_LINK_STEER_CNTL = 0x7FA4,
		475
		476	RV620_LVTMA_TRANSMITTER_CONTROL= 0x7F00,
		477	RV620_LVTMA_TRANSMITTER_ENABLE = 0x7F04,
		478	RV620_LVTMA_TRANSMITTER_ADJUST = 0x7F18,
		479	RV620_LVTMA_PREEMPHASIS_CONTROL= 0x7F1C,
		480	RV620_LVTMA_MACRO_CONTROL = 0x7F0C,
		481	RV620_LVTMA_PWRSEQ_CNTL = 0x7F80,
		482	RV620_LVTMA_PWRSEQ_STATE = 0x7f84,
		483	RV620_LVTMA_PWRSEQ_REF_DIV = 0x7f88,
		484	RV620_LVTMA_PWRSEQ_DELAY1 = 0x7f8C,
		485	RV620_LVTMA_PWRSEQ_DELAY2 = 0x7f90,
		486	RV620_LVTMA_BL_MOD_CNTL = 0x7F94,
		487	RV620_LVTMA_DATA_SYNCHRONIZATION = 0x7F98,
		488	RV620_FMT1_CONTROL = 0x6700,
		489	RV620_FMT1_BIT_DEPTH_CONTROL= 0x6710,
		490	RV620_FMT1_CLAMP_CNTL = 0x672C,
		491	RV620_FMT2_CONTROL = 0x6F00,
		492	RV620_FMT2_CNTL = 0x6F10,
		493	RV620_FMT2_CLAMP_CNTL = 0x6F2C,
		494
		495	RV620_EXT1_DIFF_POST_DIV_CNTL= 0x0420,
		496	RV620_EXT2_DIFF_POST_DIV_CNTL= 0x0424,
		497	RV620_DCCG_PCLK_DIGA_CNTL = 0x04b0,
		498	RV620_DCCG_PCLK_DIGB_CNTL = 0x04b4,
		499	RV620_DCCG_SYMCLK_CNTL = 0x04b8
		500	};
		501
		502	enum RV620_EXT1_DIFF_POST_DIV_CNTL_BITS {
		503	RV62_EXT1_DIFF_POST_DIV_RESET = 1 << 0,
		504	RV62_EXT1_DIFF_POST_DIV_SELECT = 1 << 4,
		505	RV62_EXT1_DIFF_DRIVER_ENABLE = 1 << 8
		506	};
		507
		508	enum RV620_EXT2_DIFF_POST_DIV_CNTL_BITS {
		509	RV62_EXT2_DIFF_POST_DIV_RESET = 1 << 0,
		510	RV62_EXT2_DIFF_POST_DIV_SELECT = 1 << 4,
		511	RV62_EXT2_DIFF_DRIVER_ENABLE = 1 << 8
		512	};
		513
		514	enum RV620_LVTMA_PWRSEQ_CNTL_BITS {
		515	RV62_LVTMA_PWRSEQ_EN = 1 << 0,
		516	RV62_LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_EN = 1 << 1,
		517	RV62_LVTMA_PLL_ENABLE_PWRSEQ_MASK = 1 << 2,
		518	RV62_LVTMA_PLL_RESET_PWRSEQ_MASK = 1 << 3,
		519	RV62_LVTMA_PWRSEQ_TARGET_STATE = 1 << 4,
		520	RV62_LVTMA_SYNCEN = 1 << 8,
		521	RV62_LVTMA_SYNCEN_OVRD = 1 << 9,
		522	RV62_LVTMA_SYNCEN_POL = 1 << 10,
		523	RV62_LVTMA_DIGON = 1 << 16,
		524	RV62_LVTMA_DIGON_OVRD = 1 << 17,
		525	RV62_LVTMA_DIGON_POL = 1 << 18,
		526	RV62_LVTMA_BLON = 1 << 24,
		527	RV62_LVTMA_BLON_OVRD = 1 << 25,
		528	RV62_LVTMA_BLON_POL = 1 << 26
		529	};
		530
		531	enum RV620_LVTMA_PWRSEQ_STATE_BITS {
		532	RV62_LVTMA_PWRSEQ_STATE_SHIFT = 8
		533	};
		534
		535	enum RV620_LVTMA_PWRSEQ_STATE_VAL {
		536	RV62_POWERUP_DONE = 4,
		537	RV62_POWERDOWN_DONE = 9
		538	};
		539
		540	enum RV620_LVTMA_TRANSMITTER_CONTROL_BITS {
		541	RV62_LVTMA_PLL_ENABLE = 1 << 0,
		542	RV62_LVTMA_PLL_RESET = 1 << 1,
		543	RV62_LVTMA_IDSCKSEL = 1 << 4,
		544	RV62_LVTMA_BGSLEEP = 1 << 5,
		545	RV62_LVTMA_IDCLK_SEL = 1 << 6,
		546	RV62_LVTMA_TMCLK = 1 << 8,
		547	RV62_LVTMA_TMCLK_FROM_PADS = 1 << 13,
		548	RV62_LVTMA_TDCLK = 1 << 14,
		549	RV62_LVTMA_TDCLK_FROM_PADS = 1 << 15,
		550	RV62_LVTMA_BYPASS_PLL = 1 << 28,
		551	RV62_LVTMA_USE_CLK_DATA = 1 << 29,
		552	RV62_LVTMA_MODE = 1 << 30,
		553	RV62_LVTMA_INPUT_TEST_CLK_SEL = 1 << 31
		554	};
		555
		556	enum RV620_DCCG_SYMCLK_CNTL {
		557	RV62_SYMCLKA_SRC_SHIFT = 8,
		558	RV62_SYMCLKB_SRC_SHIFT = 12
		559	};
		560
		561	enum RV620_DCCG_DIG_CNTL {
		562	RV62_PCLK_DIGA_ON = 0x1
		563	};
		564
		565	enum RV620_DCIO_LINK_STEER_CNTL {
		566	RV62_LINK_STEER_SWAP = 1 << 0,
		567	RV62_LINK_STEER_PLLSEL_OVERWRITE_EN = 1 << 16,
		568	RV62_LINK_STEER_PLLSELA = 1 << 17,
		569	RV62_LINK_STEER_PLLSELB = 1 << 18
		570	};
		571
		572	enum R620_LVTMA_TRANSMITTER_ENABLE_BITS {
		573	RV62_LVTMA_LNK0EN = 1 << 0,
		574	RV62_LVTMA_LNK1EN = 1 << 1,
		575	RV62_LVTMA_LNK2EN = 1 << 2,
		576	RV62_LVTMA_LNK3EN = 1 << 3,
		577	RV62_LVTMA_LNK4EN = 1 << 4,
		578	RV62_LVTMA_LNK5EN = 1 << 5,
		579	RV62_LVTMA_LNK6EN = 1 << 6,
		580	RV62_LVTMA_LNK7EN = 1 << 7,
		581	RV62_LVTMA_LNK8EN = 1 << 8,
		582	RV62_LVTMA_LNK9EN = 1 << 9,
		583	RV62_LVTMA_LNKL = RV62_LVTMA_LNK0EN \| RV62_LVTMA_LNK1EN
		584	\| RV62_LVTMA_LNK2EN \| RV62_LVTMA_LNK3EN,
		585	RV62_LVTMA_LNKU = RV62_LVTMA_LNK4EN \| RV62_LVTMA_LNK5EN
		586	\| RV62_LVTMA_LNK6EN \| RV62_LVTMA_LNK7EN,
		587	RV62_LVTMA_LNK_ALL = RV62_LVTMA_LNKL \| RV62_LVTMA_LNKU
		588	\| RV62_LVTMA_LNK8EN \| RV62_LVTMA_LNK9EN,
		589	RV62_LVTMA_LNKEN_HPD_MASK = 1 << 16
		590	};
		591
		592	enum RV620_LVTMA_DATA_SYNCHRONIZATION {
		593	RV62_LVTMA_DSYNSEL = (1 << 0),
		594	RV62_LVTMA_PFREQCHG = (1 << 8)
		595	};
		596
		597	enum RV620_LVTMA_PWRSEQ_REF_DIV_BITS {
		598	LVTMA_PWRSEQ_REF_DI_SHIFT = 0,
		599	LVTMA_BL_MOD_REF_DI_SHIFT = 16
		600	};
		601
		602	enum RV620_LVTMA_BL_MOD_CNTL_BITS {
		603	LVTMA_BL_MOD_EN = 1 << 0,
		604	LVTMA_BL_MOD_LEVEL_SHIFT = 8,
		605	LVTMA_BL_MOD_RES_SHIFT = 16
		606	};
		607
		608	enum RV620_DIG_CNTL_BITS {
		609	/* 0x75A0 */
		610	RV62_DIG_SWAP = (0x1 << 16),
		611	RV62_DIG_DUAL_LINK_ENABLE = (0x1 << 12),
		612	RV62_DIG_START = (0x1 << 6),
		613	RV62_DIG_MODE = (0x7 << 8),
		614	RV62_DIG_STEREOSYNC_SELECT = (1 << 2),
		615	RV62_DIG_SOURCE_SELECT = (1 << 0)
		616	};
		617
		618	enum RV620_DIG_LVDS_DATA_CNTL_BITS {
		619	/* 0x75BC */
		620	RV62_LVDS_24BIT_ENABLE = (0x1 << 0),
		621	RV62_LVDS_24BIT_FORMAT = (0x1 << 4)
		622	};
		623
		624	enum RV620_TMDS_CNTL_BITS {
		625	/* 0x75C0 */
		626	RV62_TMDS_PIXEL_ENCODING = (0x1 << 4),
		627	RV62_TMDS_COLOR_FORMAT = (0x3 << 8)
		628	};
		629
		630	enum RV620_FMT_BIT_DEPTH_CONTROL {
		631	RV62_FMT_TRUNCATE_EN = 1 << 0,
		632	RV62_FMT_TRUNCATE_DEPTH = 1 << 4,
		633	RV62_FMT_SPATIAL_DITHER_EN = 1 << 8,
		634	RV62_FMT_SPATIAL_DITHER_MODE = 1 << 9,
		635	RV62_FMT_SPATIAL_DITHER_DEPTH = 1 << 12,
		636	RV62_FMT_FRAME_RANDOM_ENABLE = 1 << 13,
		637	RV62_FMT_RGB_RANDOM_ENABLE = 1 << 14,
		638	RV62_FMT_HIGHPASS_RANDOM_ENABLE = 1 << 15,
		639	RV62_FMT_TEMPORAL_DITHER_EN = 1 << 16,
		640	RV62_FMT_TEMPORAL_DITHER_DEPTH = 1 << 20,
		641	RV62_FMT_TEMPORAL_DITHER_OFFSET = 3 << 21,
		642	RV62_FMT_TEMPORAL_LEVEL = 1 << 24,
		643	RV62_FMT_TEMPORAL_DITHER_RESET = 1 << 25,
		644	RV62_FMT_25FRC_SEL = 3 << 26,
		645	RV62_FMT_50FRC_SEL = 3 << 28,
		646	RV62_FMT_75FRC_SEL = 3 << 30
		647	};
		648
		649	enum RV620_FMT_CONTROL {
		650	RV62_FMT_PIXEL_ENCODING = 1 << 16
		651	};
		652
		653	enum _r5xxMCRegs {
		654	R5XX_MC_STATUS = 0x0000,
		655	RV515_MC_FB_LOCATION = 0x0001,
		656	R5XX_MC_FB_LOCATION = 0x0004,
		657	RV515_MC_STATUS = 0x0008,
		658	RV515_MC_MISC_LAT_TIMER = 0x0009
		659	};
		660
		661	enum _r5xxRegs {
		662	/* I2C */
		663	R5_DC_I2C_STATUS1 = 0x7D30, /* (RW) */
		664	R5_DC_I2C_RESET = 0x7D34, /* (RW) */
		665	R5_DC_I2C_CONTROL1 = 0x7D38, /* (RW) */
		666	R5_DC_I2C_CONTROL2 = 0x7D3C, /* (RW) */
		667	R5_DC_I2C_CONTROL3 = 0x7D40, /* (RW) */
		668	R5_DC_I2C_DATA = 0x7D44, /* (RW) */
		669	R5_DC_I2C_INTERRUPT_CONTROL = 0x7D48, /* (RW) */
		670	R5_DC_I2C_ARBITRATION = 0x7D50, /* (RW) */
		671
		672	R5_DC_GPIO_DDC1_MASK = 0x7E40, /* (RW) */
		673	R5_DC_GPIO_DDC1_A = 0x7E44, /* (RW) */
		674	R5_DC_GPIO_DDC1_EN = 0x7E48, /* (RW) */
		675	R5_DC_GPIO_DDC2_MASK = 0x7E50, /* (RW) */
		676	R5_DC_GPIO_DDC2_A = 0x7E54, /* (RW) */
		677	R5_DC_GPIO_DDC2_EN = 0x7E58, /* (RW) */
		678	R5_DC_GPIO_DDC3_MASK = 0x7E60, /* (RW) */
		679	R5_DC_GPIO_DDC3_A = 0x7E64, /* (RW) */
		680	R5_DC_GPIO_DDC3_EN = 0x7E68 /* (RW) */
		681	};
		682
		683	enum _r5xxSPLLRegs {
		684	SPLL_FUNC_CNTL = 0x0 /* (RW) */
		685	};
		686
		687	enum _r6xxRegs {
		688	/* MCLK */
		689	R6_MCLK_PWRMGT_CNTL = 0x620,
		690	/* I2C */
		691	R6_DC_I2C_CONTROL = 0x7D30, /* (RW) */
		692	R6_DC_I2C_ARBITRATION = 0x7D34, /* (RW) */
		693	R6_DC_I2C_INTERRUPT_CONTROL = 0x7D38, /* (RW) */
		694	R6_DC_I2C_SW_STATUS = 0x7d3c, /* (RW) */
		695	R6_DC_I2C_DDC1_SPEED = 0x7D4C, /* (RW) */
		696	R6_DC_I2C_DDC1_SETUP = 0x7D50, /* (RW) */
		697	R6_DC_I2C_DDC2_SPEED = 0x7D54, /* (RW) */
		698	R6_DC_I2C_DDC2_SETUP = 0x7D58, /* (RW) */
		699	R6_DC_I2C_DDC3_SPEED = 0x7D5C, /* (RW) */
		700	R6_DC_I2C_DDC3_SETUP = 0x7D60, /* (RW) */
		701	R6_DC_I2C_TRANSACTION0 = 0x7D64, /* (RW) */
		702	R6_DC_I2C_TRANSACTION1 = 0x7D68, /* (RW) */
		703	R6_DC_I2C_DATA = 0x7D74, /* (RW) */
		704	R6_DC_I2C_DDC4_SPEED = 0x7DB4, /* (RW) */
		705	R6_DC_I2C_DDC4_SETUP = 0x7DBC, /* (RW) */
		706	R6_DC_GPIO_DDC4_MASK = 0x7E00, /* (RW) */
		707	R6_DC_GPIO_DDC4_A = 0x7E04, /* (RW) */
		708	R6_DC_GPIO_DDC4_EN = 0x7E08, /* (RW) */
		709	R6_DC_GPIO_DDC1_MASK = 0x7E40, /* (RW) */
		710	R6_DC_GPIO_DDC1_A = 0x7E44, /* (RW) */
		711	R6_DC_GPIO_DDC1_EN = 0x7E48, /* (RW) */
		712	R6_DC_GPIO_DDC1_Y = 0x7E4C, /* (RW) */
		713	R6_DC_GPIO_DDC2_MASK = 0x7E50, /* (RW) */
		714	R6_DC_GPIO_DDC2_A = 0x7E54, /* (RW) */
		715	R6_DC_GPIO_DDC2_EN = 0x7E58, /* (RW) */
		716	R6_DC_GPIO_DDC2_Y = 0x7E5C, /* (RW) */
		717	R6_DC_GPIO_DDC3_MASK = 0x7E60, /* (RW) */
		718	R6_DC_GPIO_DDC3_A = 0x7E64, /* (RW) */
		719	R6_DC_GPIO_DDC3_EN = 0x7E68, /* (RW) */
		720	R6_DC_GPIO_DDC3_Y = 0x7E6C /* (RW) */
		721	};
		722
		723	enum R6_MCLK_PWRMGT_CNTL {
		724	R6_MC_BUSY = (1 << 5)
		725	};
		726
		727
		728	/* _Q: questionbable /
		729	enum _rs69xRegs {
		730	/* I2C */
		731	RS69_DC_I2C_CONTROL = 0x7D30, /* (RW) // */
		732	RS69_DC_I2C_UNKNOWN_2 = 0x7D34, /* (RW) */
		733	RS69_DC_I2C_INTERRUPT_CONTROL = 0x7D38, /* (RW) */
		734	RS69_DC_I2C_SW_STATUS = 0x7d3c, /* (RW) //*/
		735	RS69_DC_I2C_UNKNOWN_1 = 0x7d40,
		736	RS69_DC_I2C_DDC_SETUP_Q = 0x7D44, /* (RW) */
		737	RS69_DC_I2C_DATA = 0x7D58, /* (RW) //*/
		738	RS69_DC_I2C_TRANSACTION0 = 0x7D48, /* (RW) //*/
		739	RS69_DC_I2C_TRANSACTION1 = 0x7D4C, /* (RW) //*/
		740	/* DDIA */
		741	RS69_DDIA_CNTL = 0x7200,
		742	RS69_DDIA_SOURCE_SELECT = 0x7204,
		743	RS69_DDIA_BIT_DEPTH_CONTROL = 0x7214,
		744	RS69_DDIA_DCBALANCER_CONTROL = 0x7250,
		745	RS69_DDIA_PATH_CONTROL = 0x7264,
		746	RS69_DDIA_PCIE_LINK_CONTROL2 = 0x7278,
		747	RS69_DDIA_PCIE_LINK_CONTROL3 = 0x727c,
		748	RS69_DDIA_PCIE_PHY_CONTROL1 = 0x728c,
		749	RS69_DDIA_PCIE_PHY_CONTROL2 = 0x7290
		750	};
		751
		752	enum RS69_DDIA_CNTL_BITS {
		753	RS69_DDIA_ENABLE = 1 << 0,
		754	RS69_DDIA_HDMI_EN = 1 << 2,
		755	RS69_DDIA_ENABLE_HPD_MASK = 1 << 4,
		756	RS69_DDIA_HPD_SELECT = 1 << 8,
		757	RS69_DDIA_SYNC_PHASE = 1 << 12,
		758	RS69_DDIA_PIXEL_ENCODING = 1 << 16,
		759	RS69_DDIA_DUAL_LINK_ENABLE = 1 << 24,
		760	RS69_DDIA_SWAP = 1 << 28
		761	};
		762
		763	enum RS69_DDIA_SOURCE_SELECT_BITS {
		764	RS69_DDIA_SOURCE_SELECT_BIT = 1 << 0,
		765	RS69_DDIA_SYNC_SELECT = 1 << 8,
		766	RS69_DDIA_STEREOSYNC_SELECT = 1 << 16
		767	};
		768
		769	enum RS69_DDIA_LINK_CONTROL2_SHIFT {
		770	RS69_DDIA_PCIE_OUTPUT_MUX_SEL0 = 0,
		771	RS69_DDIA_PCIE_OUTPUT_MUX_SEL1 = 4,
		772	RS69_DDIA_PCIE_OUTPUT_MUX_SEL2 = 8,
		773	RS69_DDIA_PCIE_OUTPUT_MUX_SEL3 = 12
		774	};
		775
		776	enum RS69_DDIA_BIT_DEPTH_CONTROL_BITS {
		777	RS69_DDIA_TRUNCATE_EN = 1 << 0,
		778	RS69_DDIA_TRUNCATE_DEPTH = 1 << 4,
		779	RS69_DDIA_SPATIAL_DITHER_EN = 1 << 8,
		780	RS69_DDIA_SPATIAL_DITHER_DEPTH = 1 << 12,
		781	RS69_DDIA_TEMPORAL_DITHER_EN = 1 << 16,
		782	RS69_DDIA_TEMPORAL_DITHER_DEPTH = 1 << 20,
		783	RS69_DDIA_TEMPORAL_LEVEL = 1 << 24,
		784	RS69_DDIA_TEMPORAL_DITHER_RESET = 1 << 25
		785	};
		786
		787	enum RS69_DDIA_DCBALANCER_CONTROL_BITS {
		788	RS69_DDIA_DCBALANCER_EN = 1 << 0,
		789	RS69_DDIA_SYNC_DCBAL_EN_SHIFT = 4,
		790	RS69_DDIA_SYNC_DCBAL_EN_MASK = 7 << RS69_DDIA_SYNC_DCBAL_EN_SHIFT,
		791	RS69_DDIA_DCBALANCER_TEST_EN = 1 << 8,
		792	RS69_DDIA_DCBALANCER_TEST_IN_SHIFT = 16,
		793	RS69_DDIA_DCBALANCER_FORCE = 1 << 24
		794	};
		795
		796	enum RS69_DDIA_PATH_CONTROL_BITS {
		797	RS69_DDIA_PATH_SELECT_SHIFT = 0,
		798	RS69_DDIA_DDPII_DE_ALIGN_EN = 1 << 4,
		799	RS69_DDIA_DDPII_TRAIN_EN = 1 << 8,
		800	RS69_DDIA_DDPII_TRAIN_SELECT = 1 << 12,
		801	RS69_DDIA_DDPII_SCRAMBLE_EN = 1 << 16,
		802	RS69_DDIA_REPL_MODE_SELECT = 1 << 20,
		803	RS69_DDIA_RB_30b_SWAP_EN = 1 << 24,
		804	RS69_DDIA_PIXVLD_RESET = 1 << 28,
		805	RS69_DDIA_REARRANGER_EN = 1 << 30
		806	};
		807
		808	enum RS69_DDIA_PCIE_LINK_CONTROL3_BITS {
		809	RS69_DDIA_PCIE_MIRROR_EN = 1 << 0,
		810	RS69_DDIA_PCIE_CFGDUALLINK = 1 << 4,
		811	RS69_DDIA_PCIE_NCHG3EN = 1 << 8,
		812	RS69_DDIA_PCIE_RX_PDNB_SHIFT = 12
		813	};
		814
		815	enum RS69_MC_INDEX_BITS {
		816	RS69_MC_IND_ADDR = (0x1 << 0),
		817	RS69_MC_IND_WR_EN = (0x1 << 9)
		818	};
		819
		820	enum RS60_MC_NB_MC_INDEX_BITS {
		821	RS60_NB_MC_IND_ADDR = (0x1 << 0),
		822	RS60_NB_MC_IND_WR_EN = (0x1 << 8)
		823	};
		824
		825	enum _rs690MCRegs {
		826	RS69_K8_FB_LOCATION = 0x1E,
		827	RS69_MC_MISC_UMA_CNTL = 0x5f,
		828	RS69_MC_SYSTEM_STATUS = 0x90, /* (RW) */
		829	RS69_MCCFG_FB_LOCATION = 0x100,
		830	RS69MCCFG_AGP_LOCATION = 0x101,
		831	RS69_MC_INIT_MISC_LAT_TIMER = 0x104
		832	};
		833
		834	enum MC_MISC_LAT_TIMER_BITS {
		835	MC_CPR_INIT_LAT_SHIFT = 0,
		836	MC_VF_INIT_LAT = 4,
		837	MC_DISP0R_INIT_LAT_SHIFT = 8,
		838	MC_DISP1R_INIT_LAT_SHIFT = 12,
		839	MC_FIXED_INIT_LAT_SHIFT = 16,
		840	MC_E2R_INIT_LAT_SHIFT = 20,
		841	SAME_PAGE_PRIO_SHIFT = 24,
		842	MC_GLOBW_INIT_LAT_SHIFT = 28
		843	};
		844
		845	enum RS69_MC_MISC_UMA_CNTL_BITS {
		846	RS69_K8_40BIT_ADDR_EXTENSION = (0x1 << 0),
		847	RS69_GART_BYPASS = (0x1 << 8),
		848	RS69_GFX_64BYTE_MODE = (0x1 << 9),
		849	RS69_GFX_64BYTE_LAT = (0x1 << 10),
		850	RS69_GTW_COHERENCY = (0x1 << 15),
		851	RS69_READ_BUFFER_SIZE = (0x1 << 16),
		852	RS69_HDR_ROUTE_TO_DSP = (0x1 << 24),
		853	RS69_GTW_ROUTE_TO_DSP = (0x1 << 25),
		854	RS69_DSP_ROUTE_TO_GFX = (0x1 << 26),
		855	RS69_USE_HDPW_LAT_INIT = (0x1 << 27),
		856	RS69_USE_GFXW_LAT_INIT = (0x1 << 28),
		857	RS69_MCIFR_COHERENT = (0x1 << 29),
		858	RS69_NON_SNOOP_AZR_AIC_BP = (0x1 << 30),
		859	RS69_SIDE_PORT_PRESENT_R = (0x1 << 31)
		860	};
		861
		862	enum _rs600MCRegs {
		863	RS60_MC_SYSTEM_STATUS = 0x0,
		864	RS60_NB_FB_LOCATION = 0xa
		865	};
		866
		867	enum _rs780NBRegs {
		868	RS78_NB_MC_IND_INDEX = 0x70,
		869	RS78_NB_MC_IND_DATA = 0x74
		870	};
		871
		872	enum RS78_NB_IND_INDEX_BITS {
		873	RS78_NB_MC_IND_INDEX_MASK = (0xffff << 0),
		874	RS78_MC_IND_SEQ_RBS_0 = (0x1 << 16),
		875	RS78_MC_IND_SEQ_RBS_1 = (0x1 << 17),
		876	RS78_MC_IND_SEQ_RBS_2 = (0x1 << 18),
		877	RS78_MC_IND_SEQ_RBS_3 = (0x1 << 19),
		878	RS78_MC_IND_AIC_RBS = (0x1 << 20),
		879	RS78_MC_IND_CITF_ARB0 = (0x1 << 21),
		880	RS78_MC_IND_CITF_ARB1 = (0x1 << 22),
		881	RS78_MC_IND_WR_EN = (0x1 << 23),
		882	RS78_MC_IND_RD_INV = (0x1 << 24)
		883	};
		884
		885	enum _rs780MCRegs {
		886	RS78_MC_SYSTEM_STATUS = 0x0,
		887	RS78_MC_FB_LOCATION = 0x10,
		888	RS78_K8_FB_LOCATION = 0x11,
		889	RS78_MC_MISC_UMA_CNTL = 0x12
		890	};
		891
		892	enum RS6X_MC_SYSTEM_STATUS_BITS {
		893	RS6X_MC_SYSTEM_IDLE = (0x1 << 0),
		894	RS6X_MC_SEQUENCER_IDLE = (0x1 << 1),
		895	RS6X_MC_ARBITER_IDLE = (0x1 << 2),
		896	RS6X_MC_SELECT_PM = (0x1 << 3),
		897	RS6X_RESERVED4 = (0xf << 4),
		898	RS6X_RESERVED8 = (0xf << 8),
		899	RS6X_RESERVED12_SYSTEM_STATUS = (0xf << 12),
		900	RS6X_MCA_INIT_EXECUTED = (0x1 << 16),
		901	RS6X_MCA_IDLE = (0x1 << 17),
		902	RS6X_MCA_SEQ_IDLE = (0x1 << 18),
		903	RS6X_MCA_ARB_IDLE = (0x1 << 19),
		904	RS6X_RESERVED20_SYSTEM_STATUS = (0xfff << 20)
		905	};
		906
		907	enum RS78_MC_MISC_UMA_CNTL_BITS {
		908	RS78_K8_40BIT_ADDR_EXTENSION = ( 0x1 << 0),
		909	RS78_BANKGROUP_SEL = ( 0x1 << 8),
		910	RS78_CNTL_SPARE = ( 0x1 << 15),
		911	RS78_SIDE_PORT_PRESENT_R = ( 0x1 << 31)
		912	};
		913
		914	enum R5XX_MC_STATUS_BITS {
		915	R5XX_MEM_PWRUP_COMPL = (0x1 << 0),
		916	R5XX_MC_IDLE = (0x1 << 1)
		917	};
		918
		919	enum RV515_MC_STATUS_BITS {
		920	RV515_MC_IDLE = (0x1 << 4)
		921	};
		922
		923	enum RS78_MC_SYSTEM_STATUS_BITS {
		924	RS78_MC_SYSTEM_IDLE = 1 << 0,
		925	RS78_MC_SEQUENCER_IDLE = 1 << 1,
		926	RS78_MC_ARBITER_IDLE = 1 << 2,
		927	RS78_MC_SELECT_PM = 1 << 3,
		928	RS78_MC_STATUS_15_4_SHIFT = 4,
		929	RS78_MCA_INIT_EXECUTED = 1 << 16,
		930	RS78_MCA_IDLE = 1 << 17,
		931	RS78_MCA_SEQ_IDLE = 1 << 18,
		932	RS78_MCA_ARB_IDLE = 1 << 19,
		933	RS78_MC_STATUS_31_20_SHIFT = 20
		934	};
		935
		936	enum BUS_CNTL_BITS {
		937	/* BUS_CNTL */
		938	BUS_DBL_RESYNC = (0x1 << 0),
		939	BIOS_ROM_WRT_EN = (0x1 << 1),
		940	BIOS_ROM_DIS = (0x1 << 2),
		941	PMI_IO_DIS = (0x1 << 3),
		942	PMI_MEM_DIS = (0x1 << 4),
		943	PMI_BM_DIS = (0x1 << 5),
		944	PMI_INT_DIS = (0x1 << 6)
		945	};
		946
		947	enum SEPROM_SNTL1_BITS {
		948	/* SEPROM_CNTL1 */
		949	WRITE_ENABLE = (0x1 << 0),
		950	WRITE_DISABLE = (0x1 << 1),
		951	READ_CONFIG = (0x1 << 2),
		952	WRITE_CONFIG = (0x1 << 3),
		953	READ_STATUS = (0x1 << 4),
		954	SECT_TO_SRAM = (0x1 << 5),
		955	READY_BUSY = (0x1 << 7),
		956	SEPROM_BUSY = (0x1 << 8),
		957	BCNT_OVER_WTE_EN = (0x1 << 9),
		958	RB_MASKB = (0x1 << 10),
		959	SOFT_RESET = (0x1 << 11),
		960	STATE_IDLEb = (0x1 << 12),
		961	SECTOR_ERASE = (0x1 << 13),
		962	BYTE_CNT = (0xff << 16),
		963	SCK_PRESCALE = (0xff << 24)
		964	};
		965
		966	enum VIPH_CONTROL_BITS {
		967	/* VIPH_CONTROL */
		968	VIPH_CLK_SEL = (0xff << 0),
		969	VIPH_REG_RDY = (0x1 << 13),
		970	VIPH_MAX_WAIT = (0xf << 16),
		971	VIPH_DMA_MODE = (0x1 << 20),
		972	VIPH_EN = (0x1 << 21),
		973	VIPH_DV0_WID = (0x1 << 24),
		974	VIPH_DV1_WID = (0x1 << 25),
		975	VIPH_DV2_WID = (0x1 << 26),
		976	VIPH_DV3_WID = (0x1 << 27),
		977	VIPH_PWR_DOWN = (0x1 << 28),
		978	VIPH_PWR_DOWN_AK = (0x1 << 28),
		979	VIPH_VIPCLK_DIS = (0x1 << 29)
		980	};
		981
		982	enum ROM_CNTL_BITS {
		983	SCK_OVERWRITE = 1 << 1,
		984	CLOCK_GATING_EN = 1 << 2,
		985	CSB_ACTIVE_TO_SCK_SETUP_TIME_SHIFT = 8,
		986	CSB_ACTIVE_TO_SCK_HOLD_TIME_SHIFT = 16,
		987	SCK_PRESCALE_REFCLK_SHIFT = 24,
		988	SCK_PRESCALE_CRYSTAL_CLK_SHIFT = 28
		989	};
		990
		991	enum GENERAL_PWRMGT_BITS {
		992	GLOBAL_PWRMGT_EN = 1 << 0,
		993	STATIC_PM_EN = 1 << 1,
		994	MOBILE_SU = 1 << 2,
		995	THERMAL_PROTECTION_DIS = 1 << 3,
		996	THERMAL_PROTECTION_TYPE = 1 << 4,
		997	ENABLE_GEN2PCIE = 1 << 5,
		998	SW_GPIO_INDEX_SHIFT = 1 << 6,
		999	LOW_VOLT_D2_ACPI = 1 << 8,
		1000	LOW_VOLT_D3_ACPI = 1 << 9,
		1001	VOLT_PWRMGT_EN = 1 << 10,
		1002	OPEN_DRAIN_PADS = 1 << 11,
		1003	AVP_SCLK_EN = 1 << 12,
		1004	IDCT_SCLK_EN = 1 << 13,
		1005	GPU_COUNTER_ACPI = 1 << 14,
		1006	GPU_COUNTER_CLK = 1 << 15,
		1007	BACKBIAS_PAD_EN = 1 << 16,
		1008	BACKBIAS_VALUE = 1 << 17,
		1009	BACKBIAS_DPM_CNTL = 1 << 18,
		1010	SPREAD_SPECTRUM_INDEX_SHIFT = 19,
		1011	DYN_SPREAD_SPECTRUM_EN = 1 << 2
		1012	};
		1013
		1014	enum VGA_RENDER_CONTROL_BITS {
		1015	/* VGA_RENDER_CONTROL */
		1016	VGA_BLINK_RATE = (0x1f << 0),
		1017	VGA_BLINK_MODE = (0x3 << 5),
		1018	VGA_CURSOR_BLINK_INVERT = (0x1 << 7),
		1019	VGA_EXTD_ADDR_COUNT_ENABLE = (0x1 << 8),
		1020	VGA_VSTATUS_CNTL = (0x3 << 16),
		1021	VGA_LOCK_8DOT = (0x1 << 24),
		1022	VGAREG_LINECMP_COMPATIBILITY_SEL = (0x1 << 25)
		1023	};
		1024
		1025	enum D1VGA_CONTROL_BITS {
		1026	/* D1VGA_CONTROL */
		1027	D1VGA_MODE_ENABLE = (0x1 << 0),
		1028	D1VGA_TIMING_SELECT = (0x1 << 8),
		1029	D1VGA_SYNC_POLARITY_SELECT = (0x1 << 9),
		1030	D1VGA_OVERSCAN_TIMING_SELECT = (0x1 << 10),
		1031	D1VGA_OVERSCAN_COLOR_EN = (0x1 << 16),
		1032	D1VGA_ROTATE = (0x3 << 24)
		1033	};
		1034
		1035	enum D2VGA_CONTROL_BITS {
		1036	/* D2VGA_CONTROL */
		1037	D2VGA_MODE_ENABLE = (0x1 << 0),
		1038	D2VGA_TIMING_SELECT = (0x1 << 8),
		1039	D2VGA_SYNC_POLARITY_SELECT = (0x1 << 9),
		1040	D2VGA_OVERSCAN_TIMING_SELECT = (0x1 << 10),
		1041	D2VGA_OVERSCAN_COLOR_EN = (0x1 << 16),
		1042	D2VGA_ROTATE = (0x3 << 24)
		1043	};
		1044
		1045	enum {
		1046	/* CLOCK_CNTL_INDEX */
		1047	PLL_ADDR = (0x3f << 0),
		1048	PLL_WR_EN = (0x1 << 7),
		1049	PPLL_DIV_SEL = (0x3 << 8),
		1050
		1051	/* CLOCK_CNTL_DATA */
		1052	#define PLL_DATA 0xffffffff
		1053
		1054	/* SPLL_FUNC_CNTL */
		1055	SPLL_CHG_STATUS = (0x1 << 29),
		1056	SPLL_BYPASS_EN = (0x1 << 25),
		1057
		1058	/* MC_IND_INDEX */
		1059	MC_IND_ADDR = (0xffff << 0),
		1060	MC_IND_SEQ_RBS_0 = (0x1 << 16),
		1061	MC_IND_SEQ_RBS_1 = (0x1 << 17),
		1062	MC_IND_SEQ_RBS_2 = (0x1 << 18),
		1063	MC_IND_SEQ_RBS_3 = (0x1 << 19),
		1064	MC_IND_AIC_RBS = (0x1 << 20),
		1065	MC_IND_CITF_ARB0 = (0x1 << 21),
		1066	MC_IND_CITF_ARB1 = (0x1 << 22),
		1067	MC_IND_WR_EN = (0x1 << 23),
		1068	MC_IND_RD_INV = (0x1 << 24)
		1069	#define MC_IND_ALL (MC_IND_SEQ_RBS_0 \| MC_IND_SEQ_RBS_1 \
		1070	\| MC_IND_SEQ_RBS_2 \| MC_IND_SEQ_RBS_3 \
		1071	\| MC_IND_AIC_RBS \| MC_IND_CITF_ARB0 \| MC_IND_CITF_ARB1)
		1072
		1073	/* MC_IND_DATA */
		1074	#define MC_IND_DATA_BIT 0xffffffff
		1075	};
		1076
		1077	enum AGP_STATUS_BITS {
		1078	AGP_1X_MODE = 0x01,
		1079	AGP_2X_MODE = 0x02,
		1080	AGP_4X_MODE = 0x04,
		1081	AGP_FW_MODE = 0x10,
		1082	AGP_MODE_MASK = 0x17,
		1083	AGPv3_MODE = 0x08,
		1084	AGPv3_4X_MODE = 0x01,
		1085	AGPv3_8X_MODE = 0x02
		1086	};
		1087
		1088	enum {
		1089	/* HDMI registers */
		1090	HDMI_ENABLE = 0x00,
		1091	HDMI_CNTL = 0x08,
		1092	HDMI_UNKNOWN_0 = 0x0C,
		1093	HDMI_AUDIOCNTL = 0x10,
		1094	HDMI_VIDEOCNTL = 0x14,
		1095	HDMI_VERSION = 0x18,
		1096	HDMI_UNKNOWN_1 = 0x28,
		1097	HDMI_VIDEOINFOFRAME_0 = 0x54,
		1098	HDMI_VIDEOINFOFRAME_1 = 0x58,
		1099	HDMI_VIDEOINFOFRAME_2 = 0x5c,
		1100	HDMI_VIDEOINFOFRAME_3 = 0x60,
		1101	HDMI_32kHz_CTS = 0xac,
		1102	HDMI_32kHz_N = 0xb0,
		1103	HDMI_44_1kHz_CTS = 0xb4,
		1104	HDMI_44_1kHz_N = 0xb8,
		1105	HDMI_48kHz_CTS = 0xbc,
		1106	HDMI_48kHz_N = 0xc0,
		1107	HDMI_AUDIOINFOFRAME_0 = 0xcc,
		1108	HDMI_AUDIOINFOFRAME_1 = 0xd0,
		1109	HDMI_IEC60958_1 = 0xd4,
		1110	HDMI_IEC60958_2 = 0xd8,
		1111	HDMI_UNKNOWN_2 = 0xdc,
		1112	HDMI_AUDIO_DEBUG = 0xe0
		1113	};
		1114
		1115	#endif /* _RHD_REGS_H */

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(root)/drivers/video/radeonhd/rhd_regs.h @ 1029 – Rev