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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 3769 | Serge | 1 | #ifndef _INTEL_DRIVER_H_ |
| 2 | #define _INTEL_DRIVER_H_ |
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| 3 | |||
| 4 | #include |
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| 5 | #include |
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| 6 | #include |
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| 7 | |||
| 8 | #include |
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| 9 | #include |
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| 10 | #include |
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| 11 | |||
| 12 | #include |
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| 13 | #include "va_backend_compat.h" |
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| 14 | |||
| 15 | #include "intel_compiler.h" |
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| 16 | |||
| 17 | #define BATCH_SIZE 0x80000 |
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| 18 | #define BATCH_RESERVED 0x10 |
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| 19 | |||
| 20 | #define CMD_MI (0x0 << 29) |
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| 21 | #define CMD_2D (0x2 << 29) |
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| 22 | #define CMD_3D (0x3 << 29) |
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| 23 | |||
| 24 | #define MI_NOOP (CMD_MI | 0) |
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| 25 | |||
| 26 | #define MI_BATCH_BUFFER_END (CMD_MI | (0xA << 23)) |
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| 27 | #define MI_BATCH_BUFFER_START (CMD_MI | (0x31 << 23)) |
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| 28 | |||
| 29 | #define MI_FLUSH (CMD_MI | (0x4 << 23)) |
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| 30 | #define MI_FLUSH_STATE_INSTRUCTION_CACHE_INVALIDATE (0x1 << 0) |
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| 31 | |||
| 32 | #define MI_FLUSH_DW (CMD_MI | (0x26 << 23) | 0x2) |
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| 33 | #define MI_FLUSH_DW_VIDEO_PIPELINE_CACHE_INVALIDATE (0x1 << 7) |
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| 34 | |||
| 35 | #define XY_COLOR_BLT_CMD (CMD_2D | (0x50 << 22) | 0x04) |
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| 36 | #define XY_COLOR_BLT_WRITE_ALPHA (1 << 21) |
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| 37 | #define XY_COLOR_BLT_WRITE_RGB (1 << 20) |
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| 38 | #define XY_COLOR_BLT_DST_TILED (1 << 11) |
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| 39 | |||
| 40 | /* BR13 */ |
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| 41 | #define BR13_8 (0x0 << 24) |
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| 42 | #define BR13_565 (0x1 << 24) |
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| 43 | #define BR13_1555 (0x2 << 24) |
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| 44 | #define BR13_8888 (0x3 << 24) |
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| 45 | |||
| 46 | #define CMD_PIPE_CONTROL (CMD_3D | (3 << 27) | (2 << 24) | (0 << 16)) |
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| 47 | #define CMD_PIPE_CONTROL_NOWRITE (0 << 14) |
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| 48 | #define CMD_PIPE_CONTROL_WRITE_QWORD (1 << 14) |
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| 49 | #define CMD_PIPE_CONTROL_WRITE_DEPTH (2 << 14) |
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| 50 | #define CMD_PIPE_CONTROL_WRITE_TIME (3 << 14) |
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| 51 | #define CMD_PIPE_CONTROL_DEPTH_STALL (1 << 13) |
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| 52 | #define CMD_PIPE_CONTROL_WC_FLUSH (1 << 12) |
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| 53 | #define CMD_PIPE_CONTROL_IS_FLUSH (1 << 11) |
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| 54 | #define CMD_PIPE_CONTROL_TC_FLUSH (1 << 10) |
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| 55 | #define CMD_PIPE_CONTROL_NOTIFY_ENABLE (1 << 8) |
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| 56 | #define CMD_PIPE_CONTROL_DC_FLUSH (1 << 5) |
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| 57 | #define CMD_PIPE_CONTROL_GLOBAL_GTT (1 << 2) |
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| 58 | #define CMD_PIPE_CONTROL_LOCAL_PGTT (0 << 2) |
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| 59 | #define CMD_PIPE_CONTROL_DEPTH_CACHE_FLUSH (1 << 0) |
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| 60 | |||
| 61 | |||
| 62 | struct intel_batchbuffer; |
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| 63 | |||
| 64 | #define ALIGN(i, n) (((i) + (n) - 1) & ~((n) - 1)) |
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| 65 | #define MIN(a, b) ((a) < (b) ? (a) : (b)) |
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| 66 | #define MAX(a, b) ((a) > (b) ? (a) : (b)) |
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| 67 | #define ARRAY_ELEMS(a) (sizeof(a) / sizeof((a)[0])) |
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| 68 | |||
| 69 | #define Bool int |
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| 70 | #define True 1 |
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| 71 | #define False 0 |
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| 72 | |||
| 73 | #define SET_BLOCKED_SIGSET() do { \ |
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| 74 | sigset_t bl_mask; \ |
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| 75 | sigfillset(&bl_mask); \ |
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| 76 | sigdelset(&bl_mask, SIGFPE); \ |
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| 77 | sigdelset(&bl_mask, SIGILL); \ |
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| 78 | sigdelset(&bl_mask, SIGSEGV); \ |
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| 79 | sigdelset(&bl_mask, SIGBUS); \ |
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| 80 | sigdelset(&bl_mask, SIGKILL); \ |
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| 81 | pthread_sigmask(SIG_SETMASK, &bl_mask, &intel->sa_mask); \ |
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| 82 | } while (0) |
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| 83 | |||
| 84 | #define RESTORE_BLOCKED_SIGSET() do { \ |
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| 85 | pthread_sigmask(SIG_SETMASK, &intel->sa_mask, NULL); \ |
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| 86 | } while (0) |
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| 87 | |||
| 88 | #define PPTHREAD_MUTEX_LOCK() do { \ |
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| 89 | SET_BLOCKED_SIGSET(); \ |
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| 90 | pthread_mutex_lock(&intel->ctxmutex); \ |
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| 91 | } while (0) |
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| 92 | |||
| 93 | #define PPTHREAD_MUTEX_UNLOCK() do { \ |
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| 94 | pthread_mutex_unlock(&intel->ctxmutex); \ |
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| 95 | RESTORE_BLOCKED_SIGSET(); \ |
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| 96 | } while (0) |
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| 97 | |||
| 98 | #define WARN_ONCE(...) do { \ |
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| 99 | static int g_once = 1; \ |
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| 100 | if (g_once) { \ |
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| 101 | g_once = 0; \ |
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| 102 | printf("WARNING: " __VA_ARGS__); \ |
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| 103 | } \ |
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| 104 | } while (0) |
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| 105 | |||
| 106 | struct intel_driver_data |
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| 107 | { |
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| 108 | int fd; |
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| 109 | int device_id; |
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| 110 | int revision; |
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| 111 | |||
| 112 | int dri2Enabled; |
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| 113 | |||
| 114 | sigset_t sa_mask; |
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| 115 | // pthread_mutex_t ctxmutex; |
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| 116 | int locked; |
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| 117 | |||
| 118 | dri_bufmgr *bufmgr; |
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| 119 | |||
| 120 | unsigned int has_exec2 : 1; /* Flag: has execbuffer2? */ |
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| 121 | unsigned int has_bsd : 1; /* Flag: has bitstream decoder for H.264? */ |
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| 122 | unsigned int has_blt : 1; /* Flag: has BLT unit? */ |
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| 123 | }; |
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| 124 | |||
| 125 | Bool intel_driver_init(VADriverContextP ctx); |
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| 126 | Bool intel_driver_terminate(VADriverContextP ctx); |
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| 127 | |||
| 128 | static INLINE struct intel_driver_data * |
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| 129 | intel_driver_data(VADriverContextP ctx) |
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| 130 | { |
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| 131 | return (struct intel_driver_data *)ctx->pDriverData; |
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| 132 | } |
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| 133 | |||
| 134 | struct intel_region |
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| 135 | { |
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| 136 | int x; |
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| 137 | int y; |
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| 138 | unsigned int width; |
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| 139 | unsigned int height; |
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| 140 | unsigned int cpp; |
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| 141 | unsigned int pitch; |
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| 142 | unsigned int tiling; |
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| 143 | unsigned int swizzle; |
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| 144 | dri_bo *bo; |
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| 145 | }; |
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| 146 | |||
| 147 | #define PCI_CHIP_GM45_GM 0x2A42 |
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| 148 | #define PCI_CHIP_IGD_E_G 0x2E02 |
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| 149 | #define PCI_CHIP_Q45_G 0x2E12 |
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| 150 | #define PCI_CHIP_G45_G 0x2E22 |
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| 151 | #define PCI_CHIP_G41_G 0x2E32 |
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| 152 | #define PCI_CHIP_B43_G 0x2E42 |
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| 153 | #define PCI_CHIP_B43_G1 0x2E92 |
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| 154 | |||
| 155 | #define PCI_CHIP_IRONLAKE_D_G 0x0042 |
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| 156 | #define PCI_CHIP_IRONLAKE_M_G 0x0046 |
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| 157 | |||
| 158 | #ifndef PCI_CHIP_SANDYBRIDGE_GT1 |
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| 159 | #define PCI_CHIP_SANDYBRIDGE_GT1 0x0102 /* Desktop */ |
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| 160 | #define PCI_CHIP_SANDYBRIDGE_GT2 0x0112 |
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| 161 | #define PCI_CHIP_SANDYBRIDGE_GT2_PLUS 0x0122 |
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| 162 | #define PCI_CHIP_SANDYBRIDGE_M_GT1 0x0106 /* Mobile */ |
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| 163 | #define PCI_CHIP_SANDYBRIDGE_M_GT2 0x0116 |
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| 164 | #define PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS 0x0126 |
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| 165 | #define PCI_CHIP_SANDYBRIDGE_S_GT 0x010A /* Server */ |
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| 166 | #endif |
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| 167 | |||
| 168 | #define PCI_CHIP_IVYBRIDGE_GT1 0x0152 /* Desktop */ |
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| 169 | #define PCI_CHIP_IVYBRIDGE_GT2 0x0162 |
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| 170 | #define PCI_CHIP_IVYBRIDGE_M_GT1 0x0156 /* Mobile */ |
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| 171 | #define PCI_CHIP_IVYBRIDGE_M_GT2 0x0166 |
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| 172 | #define PCI_CHIP_IVYBRIDGE_S_GT1 0x015a /* Server */ |
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| 173 | #define PCI_CHIP_IVYBRIDGE_S_GT2 0x016a |
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| 174 | |||
| 175 | #define PCI_CHIP_HASWELL_GT1 0x0402 /* Desktop */ |
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| 176 | #define PCI_CHIP_HASWELL_GT2 0x0412 |
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| 177 | #define PCI_CHIP_HASWELL_GT2_PLUS 0x0422 |
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| 178 | #define PCI_CHIP_HASWELL_M_GT1 0x0406 /* Mobile */ |
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| 179 | #define PCI_CHIP_HASWELL_M_GT2 0x0416 |
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| 180 | #define PCI_CHIP_HASWELL_M_GT2_PLUS 0x0426 |
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| 181 | #define PCI_CHIP_HASWELL_S_GT1 0x040a /* Server */ |
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| 182 | #define PCI_CHIP_HASWELL_S_GT2 0x041a |
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| 183 | #define PCI_CHIP_HASWELL_S_GT2_PLUS 0x042a |
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| 184 | |||
| 185 | #define PCI_CHIP_HASWELL_SDV_GT1 0x0c02 /* Desktop */ |
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| 186 | #define PCI_CHIP_HASWELL_SDV_GT2 0x0c12 |
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| 187 | #define PCI_CHIP_HASWELL_SDV_GT2_PLUS 0x0c22 |
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| 188 | #define PCI_CHIP_HASWELL_SDV_M_GT1 0x0c06 /* Mobile */ |
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| 189 | #define PCI_CHIP_HASWELL_SDV_M_GT2 0x0c16 |
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| 190 | #define PCI_CHIP_HASWELL_SDV_M_GT2_PLUS 0x0c26 |
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| 191 | #define PCI_CHIP_HASWELL_SDV_S_GT1 0x0c0a /* Server */ |
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| 192 | #define PCI_CHIP_HASWELL_SDV_S_GT2 0x0c1a |
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| 193 | #define PCI_CHIP_HASWELL_SDV_S_GT2_PLUS 0x0c2a |
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| 194 | |||
| 195 | #define PCI_CHIP_HASWELL_ULT_GT1 0x0A02 /* Desktop */ |
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| 196 | #define PCI_CHIP_HASWELL_ULT_GT2 0x0A12 |
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| 197 | #define PCI_CHIP_HASWELL_ULT_GT2_PLUS 0x0A22 |
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| 198 | #define PCI_CHIP_HASWELL_ULT_M_GT1 0x0A06 /* Mobile */ |
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| 199 | #define PCI_CHIP_HASWELL_ULT_M_GT2 0x0A16 |
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| 200 | #define PCI_CHIP_HASWELL_ULT_M_GT2_PLUS 0x0A26 |
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| 201 | #define PCI_CHIP_HASWELL_ULT_S_GT1 0x0A0A /* Server */ |
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| 202 | #define PCI_CHIP_HASWELL_ULT_S_GT2 0x0A1A |
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| 203 | #define PCI_CHIP_HASWELL_ULT_S_GT2_PLUS 0x0A2A |
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| 204 | |||
| 205 | #define PCI_CHIP_HASWELL_CRW_GT1 0x0D12 /* Desktop */ |
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| 206 | #define PCI_CHIP_HASWELL_CRW_GT2 0x0D22 |
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| 207 | #define PCI_CHIP_HASWELL_CRW_GT2_PLUS 0x0D32 |
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| 208 | #define PCI_CHIP_HASWELL_CRW_M_GT1 0x0D16 /* Mobile */ |
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| 209 | #define PCI_CHIP_HASWELL_CRW_M_GT2 0x0D26 |
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| 210 | #define PCI_CHIP_HASWELL_CRW_M_GT2_PLUS 0x0D36 |
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| 211 | #define PCI_CHIP_HASWELL_CRW_S_GT1 0x0D1A /* Server */ |
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| 212 | #define PCI_CHIP_HASWELL_CRW_S_GT2 0x0D2A |
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| 213 | #define PCI_CHIP_HASWELL_CRW_S_GT2_PLUS 0x0D3A |
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| 214 | |||
| 215 | #define IS_G45(devid) (devid == PCI_CHIP_IGD_E_G || \ |
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| 216 | devid == PCI_CHIP_Q45_G || \ |
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| 217 | devid == PCI_CHIP_G45_G || \ |
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| 218 | devid == PCI_CHIP_G41_G || \ |
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| 219 | devid == PCI_CHIP_B43_G || \ |
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| 220 | devid == PCI_CHIP_B43_G1) |
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| 221 | |||
| 222 | #define IS_GM45(devid) (devid == PCI_CHIP_GM45_GM) |
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| 223 | #define IS_G4X(devid) (IS_G45(devid) || IS_GM45(devid)) |
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| 224 | |||
| 225 | #define IS_IRONLAKE_D(devid) (devid == PCI_CHIP_IRONLAKE_D_G) |
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| 226 | #define IS_IRONLAKE_M(devid) (devid == PCI_CHIP_IRONLAKE_M_G) |
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| 227 | #define IS_IRONLAKE(devid) (IS_IRONLAKE_D(devid) || IS_IRONLAKE_M(devid)) |
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| 228 | |||
| 229 | #define IS_SNB_GT1(devid) (devid == PCI_CHIP_SANDYBRIDGE_GT1 || \ |
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| 230 | devid == PCI_CHIP_SANDYBRIDGE_M_GT1 || \ |
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| 231 | devid == PCI_CHIP_SANDYBRIDGE_S_GT) |
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| 232 | |||
| 233 | #define IS_SNB_GT2(devid) (devid == PCI_CHIP_SANDYBRIDGE_GT2 || \ |
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| 234 | devid == PCI_CHIP_SANDYBRIDGE_GT2_PLUS || \ |
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| 235 | devid == PCI_CHIP_SANDYBRIDGE_M_GT2 || \ |
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| 236 | devid == PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS) |
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| 237 | |||
| 238 | #define IS_GEN6(devid) (IS_SNB_GT1(devid) || \ |
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| 239 | IS_SNB_GT2(devid)) |
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| 240 | |||
| 241 | #define IS_IVB_GT1(devid) (devid == PCI_CHIP_IVYBRIDGE_GT1 || \ |
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| 242 | devid == PCI_CHIP_IVYBRIDGE_M_GT1 || \ |
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| 243 | devid == PCI_CHIP_IVYBRIDGE_S_GT1) |
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| 244 | |||
| 245 | #define IS_IVB_GT2(devid) (devid == PCI_CHIP_IVYBRIDGE_GT2 || \ |
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| 246 | devid == PCI_CHIP_IVYBRIDGE_M_GT2 || \ |
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| 247 | devid == PCI_CHIP_IVYBRIDGE_S_GT2) |
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| 248 | |||
| 249 | #define IS_IVYBRIDGE(devid) (IS_IVB_GT1(devid) || \ |
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| 250 | IS_IVB_GT2(devid)) |
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| 251 | |||
| 252 | #define IS_HSW_GT1(devid) (devid == PCI_CHIP_HASWELL_GT1 || \ |
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| 253 | devid == PCI_CHIP_HASWELL_M_GT1 || \ |
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| 254 | devid == PCI_CHIP_HASWELL_S_GT1 || \ |
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| 255 | devid == PCI_CHIP_HASWELL_SDV_GT1 || \ |
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| 256 | devid == PCI_CHIP_HASWELL_SDV_M_GT1 || \ |
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| 257 | devid == PCI_CHIP_HASWELL_SDV_S_GT1 || \ |
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| 258 | devid == PCI_CHIP_HASWELL_CRW_GT1 || \ |
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| 259 | devid == PCI_CHIP_HASWELL_CRW_M_GT1 || \ |
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| 260 | devid == PCI_CHIP_HASWELL_CRW_S_GT1 || \ |
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| 261 | devid == PCI_CHIP_HASWELL_ULT_GT1 || \ |
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| 262 | devid == PCI_CHIP_HASWELL_ULT_M_GT1 || \ |
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| 263 | devid == PCI_CHIP_HASWELL_ULT_S_GT1) |
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| 264 | |||
| 265 | #define IS_HSW_GT2(devid) (devid == PCI_CHIP_HASWELL_GT2|| \ |
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| 266 | devid == PCI_CHIP_HASWELL_M_GT2|| \ |
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| 267 | devid == PCI_CHIP_HASWELL_S_GT2|| \ |
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| 268 | devid == PCI_CHIP_HASWELL_SDV_GT2|| \ |
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| 269 | devid == PCI_CHIP_HASWELL_SDV_M_GT2|| \ |
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| 270 | devid == PCI_CHIP_HASWELL_SDV_S_GT2|| \ |
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| 271 | devid == PCI_CHIP_HASWELL_CRW_GT2|| \ |
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| 272 | devid == PCI_CHIP_HASWELL_CRW_M_GT2|| \ |
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| 273 | devid == PCI_CHIP_HASWELL_CRW_S_GT2|| \ |
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| 274 | devid == PCI_CHIP_HASWELL_ULT_GT2|| \ |
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| 275 | devid == PCI_CHIP_HASWELL_ULT_GT2_PLUS|| \ |
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| 276 | devid == PCI_CHIP_HASWELL_ULT_M_GT2|| \ |
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| 277 | devid == PCI_CHIP_HASWELL_ULT_M_GT2_PLUS|| \ |
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| 278 | devid == PCI_CHIP_HASWELL_ULT_S_GT2 || \ |
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| 279 | devid == PCI_CHIP_HASWELL_ULT_S_GT2_PLUS || \ |
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| 280 | devid == PCI_CHIP_HASWELL_GT2_PLUS|| \ |
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| 281 | devid == PCI_CHIP_HASWELL_M_GT2_PLUS || \ |
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| 282 | devid == PCI_CHIP_HASWELL_S_GT2_PLUS || \ |
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| 283 | devid == PCI_CHIP_HASWELL_SDV_GT2_PLUS|| \ |
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| 284 | devid == PCI_CHIP_HASWELL_SDV_M_GT2_PLUS|| \ |
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| 285 | devid == PCI_CHIP_HASWELL_SDV_S_GT2_PLUS|| \ |
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| 286 | devid == PCI_CHIP_HASWELL_CRW_GT2_PLUS|| \ |
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| 287 | devid == PCI_CHIP_HASWELL_CRW_M_GT2_PLUS|| \ |
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| 288 | devid == PCI_CHIP_HASWELL_CRW_S_GT2_PLUS) |
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| 289 | |||
| 290 | #define IS_HASWELL(devid) (IS_HSW_GT1(devid) || \ |
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| 291 | IS_HSW_GT2(devid)) |
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| 292 | |||
| 293 | #define IS_GEN7(devid) (IS_IVYBRIDGE(devid) || \ |
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| 294 | IS_HASWELL(devid)) |
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| 295 | |||
| 296 | #ifndef I915_EXEC_VEBOX |
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| 297 | #define I915_EXEC_VEBOX 4 |
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| 298 | #endif |
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| 299 | |||
| 300 | #endif /* _INTEL_DRIVER_H_ */ |