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3769 | Serge | 1 | /* |
2 | * Copyright © 2010 Intel Corporation |
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3 | * |
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4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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5 | * copy of this software and associated documentation files (the |
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6 | * "Software"), to deal in the Software without restriction, including |
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7 | * without limitation the rights to use, copy, modify, merge, publish, |
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8 | * distribute, sub license, and/or sell copies of the Software, and to |
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9 | * permit persons to whom the Software is furnished to do so, subject to |
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10 | * the following conditions: |
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11 | * |
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12 | * The above copyright notice and this permission notice (including the |
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13 | * next paragraph) shall be included in all copies or substantial portions |
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14 | * of the Software. |
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15 | * |
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16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
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17 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
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18 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. |
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19 | * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR |
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20 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
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21 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
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22 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
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23 | * |
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24 | * Authors: |
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25 | * Xiang Haihao |
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26 | * |
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27 | */ |
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28 | |||
29 | #include |
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30 | #include |
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31 | #include |
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32 | |||
33 | #include "intel_batchbuffer.h" |
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34 | #include "intel_driver.h" |
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35 | |||
36 | #include "i965_defines.h" |
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37 | #include "i965_drv_video.h" |
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38 | #include "i965_avc_hw_scoreboard.h" |
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39 | #include "i965_media_h264.h" |
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40 | #include "i965_media.h" |
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41 | |||
42 | /* On Ironlake */ |
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43 | #include "shaders/h264/mc/export.inc.gen5" |
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44 | |||
45 | enum { |
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46 | AVC_HW_SCOREBOARD = 0, |
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47 | AVC_HW_SCOREBOARD_MBAFF |
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48 | }; |
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49 | |||
50 | static unsigned long avc_hw_scoreboard_kernel_offset[] = { |
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51 | SETHWSCOREBOARD_IP_GEN5 * INST_UNIT_GEN5, |
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52 | SETHWSCOREBOARD_MBAFF_IP_GEN5 * INST_UNIT_GEN5 |
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53 | }; |
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54 | |||
55 | static unsigned int avc_hw_scoreboard_constants[] = { |
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56 | 0x08040201, |
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57 | 0x00000010, |
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58 | 0x08000210, |
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59 | 0x00000000, |
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60 | 0x08040201, |
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61 | 0x08040210, |
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62 | 0x01000010, |
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63 | 0x08040200 |
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64 | }; |
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65 | |||
66 | static void |
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67 | i965_avc_hw_scoreboard_surface_state(struct i965_h264_context *i965_h264_context) |
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68 | { |
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69 | struct i965_avc_hw_scoreboard_context *avc_hw_scoreboard_context = &i965_h264_context->avc_hw_scoreboard_context; |
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70 | struct i965_surface_state *ss; |
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71 | dri_bo *bo; |
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72 | |||
73 | bo = avc_hw_scoreboard_context->surface.ss_bo; |
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74 | dri_bo_map(bo, 1); |
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75 | assert(bo->virtual); |
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76 | ss = bo->virtual; |
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77 | memset(ss, 0, sizeof(*ss)); |
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78 | ss->ss0.surface_type = I965_SURFACE_BUFFER; |
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79 | ss->ss1.base_addr = avc_hw_scoreboard_context->surface.s_bo->offset; |
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80 | ss->ss2.width = ((avc_hw_scoreboard_context->surface.total_mbs * MB_CMD_IN_OWS - 1) & 0x7f); |
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81 | ss->ss2.height = (((avc_hw_scoreboard_context->surface.total_mbs * MB_CMD_IN_OWS - 1) >> 7) & 0x1fff); |
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82 | ss->ss3.depth = (((avc_hw_scoreboard_context->surface.total_mbs * MB_CMD_IN_OWS - 1) >> 20) & 0x7f); |
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83 | dri_bo_emit_reloc(bo, |
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84 | I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, |
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85 | 0, |
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86 | offsetof(struct i965_surface_state, ss1), |
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87 | avc_hw_scoreboard_context->surface.s_bo); |
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88 | dri_bo_unmap(bo); |
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89 | } |
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90 | |||
91 | static void |
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92 | i965_avc_hw_scoreboard_interface_descriptor_table(struct i965_h264_context *i965_h264_context) |
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93 | { |
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94 | struct i965_avc_hw_scoreboard_context *avc_hw_scoreboard_context = &i965_h264_context->avc_hw_scoreboard_context; |
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95 | struct i965_interface_descriptor *desc; |
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96 | dri_bo *bo; |
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97 | |||
98 | bo = avc_hw_scoreboard_context->idrt.bo; |
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99 | dri_bo_map(bo, 1); |
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100 | assert(bo->virtual); |
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101 | desc = bo->virtual; |
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102 | memset(desc, 0, sizeof(*desc)); |
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103 | desc->desc0.grf_reg_blocks = 7; |
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104 | desc->desc0.kernel_start_pointer = (avc_hw_scoreboard_context->hw_kernel.bo->offset + |
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105 | avc_hw_scoreboard_context->hw_kernel.offset) >> 6; /* reloc */ |
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106 | desc->desc1.const_urb_entry_read_offset = 0; |
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107 | desc->desc1.const_urb_entry_read_len = 1; |
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108 | desc->desc3.binding_table_entry_count = 0; |
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109 | desc->desc3.binding_table_pointer = |
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110 | avc_hw_scoreboard_context->binding_table.bo->offset >> 5; /*reloc */ |
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111 | |||
112 | dri_bo_emit_reloc(bo, |
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113 | I915_GEM_DOMAIN_INSTRUCTION, 0, |
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114 | desc->desc0.grf_reg_blocks + avc_hw_scoreboard_context->hw_kernel.offset, |
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115 | offsetof(struct i965_interface_descriptor, desc0), |
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116 | avc_hw_scoreboard_context->hw_kernel.bo); |
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117 | |||
118 | dri_bo_emit_reloc(bo, |
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119 | I915_GEM_DOMAIN_INSTRUCTION, 0, |
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120 | desc->desc3.binding_table_entry_count, |
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121 | offsetof(struct i965_interface_descriptor, desc3), |
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122 | avc_hw_scoreboard_context->binding_table.bo); |
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123 | |||
124 | dri_bo_unmap(bo); |
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125 | } |
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126 | |||
127 | static void |
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128 | i965_avc_hw_scoreboard_binding_table(struct i965_h264_context *i965_h264_context) |
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129 | { |
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130 | struct i965_avc_hw_scoreboard_context *avc_hw_scoreboard_context = &i965_h264_context->avc_hw_scoreboard_context; |
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131 | unsigned int *binding_table; |
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132 | dri_bo *bo = avc_hw_scoreboard_context->binding_table.bo; |
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133 | |||
134 | dri_bo_map(bo, 1); |
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135 | assert(bo->virtual); |
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136 | binding_table = bo->virtual; |
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137 | memset(binding_table, 0, bo->size); |
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138 | binding_table[0] = avc_hw_scoreboard_context->surface.ss_bo->offset; |
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139 | dri_bo_emit_reloc(bo, |
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140 | I915_GEM_DOMAIN_INSTRUCTION, 0, |
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141 | 0, |
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142 | 0, |
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143 | avc_hw_scoreboard_context->surface.ss_bo); |
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144 | dri_bo_unmap(bo); |
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145 | } |
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146 | |||
147 | static void |
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148 | i965_avc_hw_scoreboard_vfe_state(struct i965_h264_context *i965_h264_context) |
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149 | { |
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150 | struct i965_avc_hw_scoreboard_context *avc_hw_scoreboard_context = &i965_h264_context->avc_hw_scoreboard_context; |
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151 | struct i965_vfe_state *vfe_state; |
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152 | dri_bo *bo; |
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153 | |||
154 | bo = avc_hw_scoreboard_context->vfe_state.bo; |
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155 | dri_bo_map(bo, 1); |
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156 | assert(bo->virtual); |
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157 | vfe_state = bo->virtual; |
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158 | memset(vfe_state, 0, sizeof(*vfe_state)); |
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159 | vfe_state->vfe1.max_threads = avc_hw_scoreboard_context->urb.num_vfe_entries - 1; |
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160 | vfe_state->vfe1.urb_entry_alloc_size = avc_hw_scoreboard_context->urb.size_vfe_entry - 1; |
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161 | vfe_state->vfe1.num_urb_entries = avc_hw_scoreboard_context->urb.num_vfe_entries; |
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162 | vfe_state->vfe1.vfe_mode = VFE_GENERIC_MODE; |
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163 | vfe_state->vfe1.children_present = 0; |
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164 | vfe_state->vfe2.interface_descriptor_base = |
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165 | avc_hw_scoreboard_context->idrt.bo->offset >> 4; /* reloc */ |
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166 | dri_bo_emit_reloc(bo, |
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167 | I915_GEM_DOMAIN_INSTRUCTION, 0, |
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168 | 0, |
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169 | offsetof(struct i965_vfe_state, vfe2), |
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170 | avc_hw_scoreboard_context->idrt.bo); |
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171 | dri_bo_unmap(bo); |
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172 | } |
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173 | |||
174 | static void |
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175 | i965_avc_hw_scoreboard_upload_constants(struct i965_h264_context *i965_h264_context) |
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176 | { |
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177 | struct i965_avc_hw_scoreboard_context *avc_hw_scoreboard_context = &i965_h264_context->avc_hw_scoreboard_context; |
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178 | unsigned char *constant_buffer; |
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179 | |||
180 | if (avc_hw_scoreboard_context->curbe.upload) |
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181 | return; |
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182 | |||
183 | dri_bo_map(avc_hw_scoreboard_context->curbe.bo, 1); |
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184 | assert(avc_hw_scoreboard_context->curbe.bo->virtual); |
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185 | constant_buffer = avc_hw_scoreboard_context->curbe.bo->virtual; |
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186 | memcpy(constant_buffer, avc_hw_scoreboard_constants, sizeof(avc_hw_scoreboard_constants)); |
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187 | dri_bo_unmap(avc_hw_scoreboard_context->curbe.bo); |
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188 | avc_hw_scoreboard_context->curbe.upload = 1; |
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189 | } |
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190 | |||
191 | static void |
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192 | i965_avc_hw_scoreboard_states_setup(struct i965_h264_context *i965_h264_context) |
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193 | { |
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194 | i965_avc_hw_scoreboard_surface_state(i965_h264_context); |
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195 | i965_avc_hw_scoreboard_binding_table(i965_h264_context); |
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196 | i965_avc_hw_scoreboard_interface_descriptor_table(i965_h264_context); |
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197 | i965_avc_hw_scoreboard_vfe_state(i965_h264_context); |
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198 | i965_avc_hw_scoreboard_upload_constants(i965_h264_context); |
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199 | } |
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200 | |||
201 | static void |
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202 | i965_avc_hw_scoreboard_pipeline_select(VADriverContextP ctx, struct i965_h264_context *i965_h264_context) |
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203 | { |
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204 | struct intel_batchbuffer *batch = i965_h264_context->batch; |
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205 | |||
206 | BEGIN_BATCH(batch, 1); |
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207 | OUT_BATCH(batch, CMD_PIPELINE_SELECT | PIPELINE_SELECT_MEDIA); |
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208 | ADVANCE_BATCH(batch); |
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209 | } |
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210 | |||
211 | static void |
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212 | i965_avc_hw_scoreboard_urb_layout(VADriverContextP ctx, struct i965_h264_context *i965_h264_context) |
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213 | { |
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214 | struct i965_avc_hw_scoreboard_context *avc_hw_scoreboard_context = &i965_h264_context->avc_hw_scoreboard_context; |
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215 | struct i965_driver_data *i965 = i965_driver_data(ctx); |
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216 | struct intel_batchbuffer *batch = i965_h264_context->batch; |
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217 | unsigned int vfe_fence, cs_fence; |
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218 | |||
219 | vfe_fence = avc_hw_scoreboard_context->urb.cs_start; |
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220 | cs_fence = URB_SIZE((&i965->intel)); |
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221 | |||
222 | BEGIN_BATCH(batch, 3); |
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223 | OUT_BATCH(batch, CMD_URB_FENCE | UF0_VFE_REALLOC | UF0_CS_REALLOC | 1); |
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224 | OUT_BATCH(batch, 0); |
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225 | OUT_BATCH(batch, |
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226 | (vfe_fence << UF2_VFE_FENCE_SHIFT) | /* VFE_SIZE */ |
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227 | (cs_fence << UF2_CS_FENCE_SHIFT)); /* CS_SIZE */ |
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228 | ADVANCE_BATCH(batch); |
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229 | } |
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230 | |||
231 | static void |
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232 | i965_avc_hw_scoreboard_state_base_address(VADriverContextP ctx, struct i965_h264_context *i965_h264_context) |
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233 | { |
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234 | struct intel_batchbuffer *batch = i965_h264_context->batch; |
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235 | |||
236 | BEGIN_BATCH(batch, 8); |
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237 | OUT_BATCH(batch, CMD_STATE_BASE_ADDRESS | 6); |
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238 | OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY); |
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239 | OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY); |
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240 | OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY); |
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241 | OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY); |
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242 | OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY); |
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243 | OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY); |
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244 | OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY); |
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245 | ADVANCE_BATCH(batch); |
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246 | } |
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247 | |||
248 | static void |
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249 | i965_avc_hw_scoreboard_state_pointers(VADriverContextP ctx, struct i965_h264_context *i965_h264_context) |
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250 | { |
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251 | struct i965_avc_hw_scoreboard_context *avc_hw_scoreboard_context = &i965_h264_context->avc_hw_scoreboard_context; |
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252 | struct intel_batchbuffer *batch = i965_h264_context->batch; |
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253 | |||
254 | BEGIN_BATCH(batch, 3); |
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255 | OUT_BATCH(batch, CMD_MEDIA_STATE_POINTERS | 1); |
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256 | OUT_BATCH(batch, 0); |
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257 | OUT_RELOC(batch, avc_hw_scoreboard_context->vfe_state.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); |
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258 | ADVANCE_BATCH(batch); |
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259 | } |
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260 | |||
261 | static void |
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262 | i965_avc_hw_scoreboard_cs_urb_layout(VADriverContextP ctx, struct i965_h264_context *i965_h264_context) |
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263 | { |
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264 | struct i965_avc_hw_scoreboard_context *avc_hw_scoreboard_context = &i965_h264_context->avc_hw_scoreboard_context; |
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265 | struct intel_batchbuffer *batch = i965_h264_context->batch; |
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266 | |||
267 | BEGIN_BATCH(batch, 2); |
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268 | OUT_BATCH(batch, CMD_CS_URB_STATE | 0); |
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269 | OUT_BATCH(batch, |
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270 | ((avc_hw_scoreboard_context->urb.size_cs_entry - 1) << 4) | /* URB Entry Allocation Size */ |
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271 | (avc_hw_scoreboard_context->urb.num_cs_entries << 0)); /* Number of URB Entries */ |
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272 | ADVANCE_BATCH(batch); |
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273 | } |
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274 | |||
275 | static void |
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276 | i965_avc_hw_scoreboard_constant_buffer(VADriverContextP ctx, struct i965_h264_context *i965_h264_context) |
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277 | { |
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278 | struct i965_avc_hw_scoreboard_context *avc_hw_scoreboard_context = &i965_h264_context->avc_hw_scoreboard_context; |
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279 | struct intel_batchbuffer *batch = i965_h264_context->batch; |
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280 | |||
281 | BEGIN_BATCH(batch, 2); |
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282 | OUT_BATCH(batch, CMD_CONSTANT_BUFFER | (1 << 8) | (2 - 2)); |
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283 | OUT_RELOC(batch, avc_hw_scoreboard_context->curbe.bo, |
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284 | I915_GEM_DOMAIN_INSTRUCTION, 0, |
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285 | avc_hw_scoreboard_context->urb.size_cs_entry - 1); |
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286 | ADVANCE_BATCH(batch); |
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287 | } |
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288 | |||
289 | static void |
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290 | i965_avc_hw_scoreboard_objects(VADriverContextP ctx, struct i965_h264_context *i965_h264_context) |
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291 | { |
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292 | struct i965_avc_hw_scoreboard_context *avc_hw_scoreboard_context = &i965_h264_context->avc_hw_scoreboard_context; |
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293 | struct intel_batchbuffer *batch = i965_h264_context->batch; |
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294 | int number_mb_cmds = 512; |
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295 | int starting_mb_number = avc_hw_scoreboard_context->inline_data.starting_mb_number; |
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296 | int i; |
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297 | |||
298 | for (i = 0; i < avc_hw_scoreboard_context->inline_data.num_mb_cmds / 512; i++) { |
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299 | BEGIN_BATCH(batch, 6); |
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300 | OUT_BATCH(batch, CMD_MEDIA_OBJECT | 4); |
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301 | OUT_BATCH(batch, 0); /* interface descriptor offset: 0 */ |
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302 | OUT_BATCH(batch, 0); /* no indirect data */ |
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303 | OUT_BATCH(batch, 0); |
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304 | OUT_BATCH(batch, ((number_mb_cmds << 16) | |
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305 | (starting_mb_number << 0))); |
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306 | OUT_BATCH(batch, avc_hw_scoreboard_context->inline_data.pic_width_in_mbs); |
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307 | ADVANCE_BATCH(batch); |
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308 | |||
309 | starting_mb_number += 512; |
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310 | } |
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311 | |||
312 | number_mb_cmds = avc_hw_scoreboard_context->inline_data.num_mb_cmds % 512; |
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313 | |||
314 | if (number_mb_cmds) { |
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315 | BEGIN_BATCH(batch, 6); |
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316 | OUT_BATCH(batch, CMD_MEDIA_OBJECT | 4); |
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317 | OUT_BATCH(batch, 0); /* interface descriptor offset: 0 */ |
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318 | OUT_BATCH(batch, 0); /* no indirect data */ |
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319 | OUT_BATCH(batch, 0); |
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320 | OUT_BATCH(batch, ((number_mb_cmds << 16) | |
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321 | (starting_mb_number << 0))); |
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322 | OUT_BATCH(batch, avc_hw_scoreboard_context->inline_data.pic_width_in_mbs); |
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323 | ADVANCE_BATCH(batch); |
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324 | } |
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325 | } |
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326 | |||
327 | static void |
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328 | i965_avc_hw_scoreboard_pipeline_setup(VADriverContextP ctx, struct i965_h264_context *i965_h264_context) |
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329 | { |
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330 | struct intel_batchbuffer *batch = i965_h264_context->batch; |
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331 | |||
332 | intel_batchbuffer_start_atomic(batch, 0x1000); |
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333 | intel_batchbuffer_emit_mi_flush(batch); |
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334 | i965_avc_hw_scoreboard_pipeline_select(ctx, i965_h264_context); |
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335 | i965_avc_hw_scoreboard_state_base_address(ctx, i965_h264_context); |
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336 | i965_avc_hw_scoreboard_state_pointers(ctx, i965_h264_context); |
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337 | i965_avc_hw_scoreboard_urb_layout(ctx, i965_h264_context); |
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338 | i965_avc_hw_scoreboard_cs_urb_layout(ctx, i965_h264_context); |
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339 | i965_avc_hw_scoreboard_constant_buffer(ctx, i965_h264_context); |
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340 | i965_avc_hw_scoreboard_objects(ctx, i965_h264_context); |
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341 | intel_batchbuffer_end_atomic(batch); |
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342 | } |
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343 | |||
344 | void |
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345 | i965_avc_hw_scoreboard(VADriverContextP ctx, struct decode_state *decode_state, void *h264_context) |
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346 | { |
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347 | struct i965_h264_context *i965_h264_context = (struct i965_h264_context *)h264_context; |
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348 | |||
349 | if (i965_h264_context->use_avc_hw_scoreboard) { |
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350 | struct i965_avc_hw_scoreboard_context *avc_hw_scoreboard_context = &i965_h264_context->avc_hw_scoreboard_context; |
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351 | |||
352 | avc_hw_scoreboard_context->inline_data.num_mb_cmds = i965_h264_context->avc_it_command_mb_info.mbs; |
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353 | avc_hw_scoreboard_context->inline_data.starting_mb_number = i965_h264_context->avc_it_command_mb_info.mbs; |
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354 | avc_hw_scoreboard_context->inline_data.pic_width_in_mbs = i965_h264_context->picture.width_in_mbs; |
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355 | avc_hw_scoreboard_context->surface.total_mbs = i965_h264_context->avc_it_command_mb_info.mbs * 2; |
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356 | |||
357 | dri_bo_unreference(avc_hw_scoreboard_context->hw_kernel.bo); |
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358 | avc_hw_scoreboard_context->hw_kernel.bo = i965_h264_context->avc_kernels[H264_AVC_COMBINED].bo; |
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359 | assert(avc_hw_scoreboard_context->hw_kernel.bo != NULL); |
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360 | dri_bo_reference(avc_hw_scoreboard_context->hw_kernel.bo); |
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361 | |||
362 | if (i965_h264_context->picture.mbaff_frame_flag) |
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363 | avc_hw_scoreboard_context->hw_kernel.offset = avc_hw_scoreboard_kernel_offset[AVC_HW_SCOREBOARD_MBAFF]; |
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364 | else |
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365 | avc_hw_scoreboard_context->hw_kernel.offset = avc_hw_scoreboard_kernel_offset[AVC_HW_SCOREBOARD]; |
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366 | |||
367 | i965_avc_hw_scoreboard_states_setup(i965_h264_context); |
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368 | i965_avc_hw_scoreboard_pipeline_setup(ctx, i965_h264_context); |
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369 | } |
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370 | } |
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371 | |||
372 | void |
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373 | i965_avc_hw_scoreboard_decode_init(VADriverContextP ctx, void *h264_context) |
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374 | { |
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375 | struct i965_driver_data *i965 = i965_driver_data(ctx); |
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376 | struct i965_h264_context *i965_h264_context = (struct i965_h264_context *)h264_context; |
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377 | |||
378 | if (i965_h264_context->use_avc_hw_scoreboard) { |
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379 | struct i965_avc_hw_scoreboard_context *avc_hw_scoreboard_context = &i965_h264_context->avc_hw_scoreboard_context; |
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380 | dri_bo *bo; |
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381 | |||
382 | if (avc_hw_scoreboard_context->curbe.bo == NULL) { |
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383 | bo = dri_bo_alloc(i965->intel.bufmgr, |
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384 | "constant buffer", |
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385 | 4096, 64); |
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386 | assert(bo); |
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387 | avc_hw_scoreboard_context->curbe.bo = bo; |
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388 | avc_hw_scoreboard_context->curbe.upload = 0; |
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389 | } |
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390 | |||
391 | dri_bo_unreference(avc_hw_scoreboard_context->surface.s_bo); |
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392 | avc_hw_scoreboard_context->surface.s_bo = i965_h264_context->avc_it_command_mb_info.bo; |
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393 | assert(avc_hw_scoreboard_context->surface.s_bo != NULL); |
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394 | dri_bo_reference(avc_hw_scoreboard_context->surface.s_bo); |
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395 | |||
396 | dri_bo_unreference(avc_hw_scoreboard_context->surface.ss_bo); |
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397 | bo = dri_bo_alloc(i965->intel.bufmgr, |
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398 | "surface state", |
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399 | sizeof(struct i965_surface_state), 32); |
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400 | assert(bo); |
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401 | avc_hw_scoreboard_context->surface.ss_bo = bo; |
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402 | |||
403 | dri_bo_unreference(avc_hw_scoreboard_context->binding_table.bo); |
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404 | bo = dri_bo_alloc(i965->intel.bufmgr, |
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405 | "binding table", |
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406 | MAX_MEDIA_SURFACES * sizeof(unsigned int), 32); |
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407 | assert(bo); |
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408 | avc_hw_scoreboard_context->binding_table.bo = bo; |
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409 | |||
410 | dri_bo_unreference(avc_hw_scoreboard_context->idrt.bo); |
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411 | bo = dri_bo_alloc(i965->intel.bufmgr, |
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412 | "interface discriptor", |
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413 | MAX_INTERFACE_DESC * sizeof(struct i965_interface_descriptor), 16); |
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414 | assert(bo); |
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415 | avc_hw_scoreboard_context->idrt.bo = bo; |
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416 | |||
417 | dri_bo_unreference(avc_hw_scoreboard_context->vfe_state.bo); |
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418 | bo = dri_bo_alloc(i965->intel.bufmgr, |
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419 | "vfe state", |
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420 | sizeof(struct i965_vfe_state), 32); |
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421 | assert(bo); |
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422 | avc_hw_scoreboard_context->vfe_state.bo = bo; |
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423 | |||
424 | avc_hw_scoreboard_context->urb.num_vfe_entries = 32; |
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425 | avc_hw_scoreboard_context->urb.size_vfe_entry = 2; |
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426 | avc_hw_scoreboard_context->urb.num_cs_entries = 1; |
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427 | avc_hw_scoreboard_context->urb.size_cs_entry = 1; |
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428 | avc_hw_scoreboard_context->urb.vfe_start = 0; |
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429 | avc_hw_scoreboard_context->urb.cs_start = avc_hw_scoreboard_context->urb.vfe_start + |
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430 | avc_hw_scoreboard_context->urb.num_vfe_entries * avc_hw_scoreboard_context->urb.size_vfe_entry; |
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431 | assert(avc_hw_scoreboard_context->urb.cs_start + |
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432 | avc_hw_scoreboard_context->urb.num_cs_entries * avc_hw_scoreboard_context->urb.size_cs_entry <= URB_SIZE((&i965->intel))); |
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433 | } |
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434 | } |
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435 | |||
436 | Bool |
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437 | i965_avc_hw_scoreboard_ternimate(struct i965_avc_hw_scoreboard_context *avc_hw_scoreboard_context) |
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438 | { |
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439 | dri_bo_unreference(avc_hw_scoreboard_context->curbe.bo); |
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440 | avc_hw_scoreboard_context->curbe.bo = NULL; |
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441 | |||
442 | dri_bo_unreference(avc_hw_scoreboard_context->surface.ss_bo); |
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443 | avc_hw_scoreboard_context->surface.ss_bo = NULL; |
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444 | |||
445 | dri_bo_unreference(avc_hw_scoreboard_context->surface.s_bo); |
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446 | avc_hw_scoreboard_context->surface.s_bo = NULL; |
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447 | |||
448 | dri_bo_unreference(avc_hw_scoreboard_context->binding_table.bo); |
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449 | avc_hw_scoreboard_context->binding_table.bo = NULL; |
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450 | |||
451 | dri_bo_unreference(avc_hw_scoreboard_context->idrt.bo); |
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452 | avc_hw_scoreboard_context->idrt.bo = NULL; |
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453 | |||
454 | dri_bo_unreference(avc_hw_scoreboard_context->vfe_state.bo); |
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455 | avc_hw_scoreboard_context->vfe_state.bo = NULL; |
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456 | |||
457 | dri_bo_unreference(avc_hw_scoreboard_context->hw_kernel.bo); |
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458 | avc_hw_scoreboard_context->hw_kernel.bo = NULL; |
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459 | |||
460 | return True; |
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461 | }=>><>><>><>><>>><>><>><>><>><> |