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4075 | Serge | 1 | /************************************************************************** |
2 | * |
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3 | * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA |
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4 | * All Rights Reserved. |
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5 | * |
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6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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7 | * copy of this software and associated documentation files (the |
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8 | * "Software"), to deal in the Software without restriction, including |
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9 | * without limitation the rights to use, copy, modify, merge, publish, |
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10 | * distribute, sub license, and/or sell copies of the Software, and to |
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11 | * permit persons to whom the Software is furnished to do so, subject to |
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12 | * the following conditions: |
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13 | * |
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14 | * The above copyright notice and this permission notice (including the |
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15 | * next paragraph) shall be included in all copies or substantial portions |
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16 | * of the Software. |
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17 | * |
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18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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20 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL |
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21 | * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, |
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22 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR |
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23 | * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE |
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24 | * USE OR OTHER DEALINGS IN THE SOFTWARE. |
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25 | * |
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26 | **************************************************************************/ |
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27 | |||
28 | #include |
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29 | #include "vmwgfx_drv.h" |
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30 | |||
31 | #define TASK_INTERRUPTIBLE 1 |
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32 | #define TASK_UNINTERRUPTIBLE 2 |
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33 | |||
34 | #define VMW_FENCE_WRAP (1 << 24) |
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35 | |||
4569 | Serge | 36 | irqreturn_t vmw_irq_handler(int irq, void *arg) |
4075 | Serge | 37 | { |
38 | struct drm_device *dev = (struct drm_device *)arg; |
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39 | struct vmw_private *dev_priv = vmw_priv(dev); |
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40 | uint32_t status, masked_status; |
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41 | |||
42 | spin_lock(&dev_priv->irq_lock); |
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43 | status = inl(dev_priv->io_start + VMWGFX_IRQSTATUS_PORT); |
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44 | masked_status = status & dev_priv->irq_mask; |
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45 | spin_unlock(&dev_priv->irq_lock); |
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46 | |||
47 | if (likely(status)) |
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48 | outl(status, dev_priv->io_start + VMWGFX_IRQSTATUS_PORT); |
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49 | |||
50 | if (!masked_status) |
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51 | return IRQ_NONE; |
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52 | |||
53 | if (masked_status & (SVGA_IRQFLAG_ANY_FENCE | |
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54 | SVGA_IRQFLAG_FENCE_GOAL)) { |
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55 | vmw_fences_update(dev_priv->fman); |
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56 | wake_up_all(&dev_priv->fence_queue); |
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57 | } |
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58 | |||
59 | if (masked_status & SVGA_IRQFLAG_FIFO_PROGRESS) |
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60 | wake_up_all(&dev_priv->fifo_queue); |
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61 | |||
62 | |||
63 | return IRQ_HANDLED; |
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64 | } |
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65 | |||
66 | static bool vmw_fifo_idle(struct vmw_private *dev_priv, uint32_t seqno) |
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67 | { |
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68 | uint32_t busy; |
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69 | |||
70 | mutex_lock(&dev_priv->hw_mutex); |
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71 | busy = vmw_read(dev_priv, SVGA_REG_BUSY); |
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72 | mutex_unlock(&dev_priv->hw_mutex); |
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73 | |||
74 | return (busy == 0); |
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75 | } |
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76 | |||
77 | void vmw_update_seqno(struct vmw_private *dev_priv, |
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78 | struct vmw_fifo_state *fifo_state) |
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79 | { |
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80 | __le32 __iomem *fifo_mem = dev_priv->mmio_virt; |
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81 | uint32_t seqno = ioread32(fifo_mem + SVGA_FIFO_FENCE); |
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82 | |||
83 | if (dev_priv->last_read_seqno != seqno) { |
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84 | dev_priv->last_read_seqno = seqno; |
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85 | vmw_marker_pull(&fifo_state->marker_queue, seqno); |
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86 | vmw_fences_update(dev_priv->fman); |
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87 | } |
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88 | } |
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89 | |||
90 | bool vmw_seqno_passed(struct vmw_private *dev_priv, |
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91 | uint32_t seqno) |
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92 | { |
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93 | struct vmw_fifo_state *fifo_state; |
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94 | bool ret; |
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95 | |||
96 | if (likely(dev_priv->last_read_seqno - seqno < VMW_FENCE_WRAP)) |
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97 | return true; |
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98 | |||
99 | fifo_state = &dev_priv->fifo; |
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100 | vmw_update_seqno(dev_priv, fifo_state); |
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101 | if (likely(dev_priv->last_read_seqno - seqno < VMW_FENCE_WRAP)) |
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102 | return true; |
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103 | |||
104 | if (!(fifo_state->capabilities & SVGA_FIFO_CAP_FENCE) && |
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105 | vmw_fifo_idle(dev_priv, seqno)) |
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106 | return true; |
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107 | |||
108 | /** |
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109 | * Then check if the seqno is higher than what we've actually |
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110 | * emitted. Then the fence is stale and signaled. |
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111 | */ |
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112 | |||
113 | ret = ((atomic_read(&dev_priv->marker_seq) - seqno) |
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114 | > VMW_FENCE_WRAP); |
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115 | |||
116 | return ret; |
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117 | } |
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118 | |||
119 | int vmw_fallback_wait(struct vmw_private *dev_priv, |
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120 | bool lazy, |
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121 | bool fifo_idle, |
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122 | uint32_t seqno, |
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123 | bool interruptible, |
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124 | unsigned long timeout) |
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125 | { |
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126 | struct vmw_fifo_state *fifo_state = &dev_priv->fifo; |
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127 | |||
128 | uint32_t count = 0; |
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129 | uint32_t signal_seq; |
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130 | int ret; |
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5078 | serge | 131 | unsigned long end_jiffies = jiffies + timeout; |
4075 | Serge | 132 | bool (*wait_condition)(struct vmw_private *, uint32_t); |
133 | DEFINE_WAIT(__wait); |
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134 | |||
135 | wait_condition = (fifo_idle) ? &vmw_fifo_idle : |
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136 | &vmw_seqno_passed; |
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137 | |||
138 | /** |
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139 | * Block command submission while waiting for idle. |
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140 | */ |
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141 | |||
142 | // if (fifo_idle) |
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143 | // down_read(&fifo_state->rwsem); |
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144 | signal_seq = atomic_read(&dev_priv->marker_seq); |
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145 | ret = 0; |
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146 | |||
147 | for (;;) { |
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148 | // prepare_to_wait(&dev_priv->fence_queue, &__wait, |
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149 | // (interruptible) ? |
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150 | // TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE); |
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151 | if (wait_condition(dev_priv, seqno)) |
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152 | break; |
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5078 | serge | 153 | if (time_after_eq(jiffies, end_jiffies)) { |
4075 | Serge | 154 | DRM_ERROR("SVGA device lockup.\n"); |
155 | break; |
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156 | } |
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157 | if (lazy) |
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158 | delay(1); |
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159 | else if ((++count & 0x0F) == 0) { |
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160 | /** |
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161 | * FIXME: Use schedule_hr_timeout here for |
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162 | * newer kernels and lower CPU utilization. |
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163 | */ |
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164 | |||
165 | delay(1); |
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166 | } |
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167 | } |
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168 | // finish_wait(&dev_priv->fence_queue, &__wait); |
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169 | if (ret == 0 && fifo_idle) { |
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170 | __le32 __iomem *fifo_mem = dev_priv->mmio_virt; |
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171 | iowrite32(signal_seq, fifo_mem + SVGA_FIFO_FENCE); |
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172 | } |
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173 | wake_up_all(&dev_priv->fence_queue); |
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174 | // if (fifo_idle) |
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175 | // up_read(&fifo_state->rwsem); |
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176 | |||
177 | return ret; |
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178 | } |
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179 | |||
180 | void vmw_seqno_waiter_add(struct vmw_private *dev_priv) |
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181 | { |
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182 | mutex_lock(&dev_priv->hw_mutex); |
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183 | if (dev_priv->fence_queue_waiters++ == 0) { |
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184 | unsigned long irq_flags; |
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185 | |||
186 | spin_lock_irqsave(&dev_priv->irq_lock, irq_flags); |
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187 | outl(SVGA_IRQFLAG_ANY_FENCE, |
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188 | dev_priv->io_start + VMWGFX_IRQSTATUS_PORT); |
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189 | dev_priv->irq_mask |= SVGA_IRQFLAG_ANY_FENCE; |
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190 | vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask); |
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191 | spin_unlock_irqrestore(&dev_priv->irq_lock, irq_flags); |
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192 | } |
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193 | mutex_unlock(&dev_priv->hw_mutex); |
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194 | } |
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195 | |||
196 | void vmw_seqno_waiter_remove(struct vmw_private *dev_priv) |
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197 | { |
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198 | mutex_lock(&dev_priv->hw_mutex); |
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199 | if (--dev_priv->fence_queue_waiters == 0) { |
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200 | unsigned long irq_flags; |
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201 | |||
202 | spin_lock_irqsave(&dev_priv->irq_lock, irq_flags); |
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203 | dev_priv->irq_mask &= ~SVGA_IRQFLAG_ANY_FENCE; |
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204 | vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask); |
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205 | spin_unlock_irqrestore(&dev_priv->irq_lock, irq_flags); |
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206 | } |
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207 | mutex_unlock(&dev_priv->hw_mutex); |
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208 | } |
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209 | |||
210 | |||
211 | void vmw_goal_waiter_add(struct vmw_private *dev_priv) |
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212 | { |
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213 | mutex_lock(&dev_priv->hw_mutex); |
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214 | if (dev_priv->goal_queue_waiters++ == 0) { |
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215 | unsigned long irq_flags; |
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216 | |||
217 | spin_lock_irqsave(&dev_priv->irq_lock, irq_flags); |
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218 | outl(SVGA_IRQFLAG_FENCE_GOAL, |
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219 | dev_priv->io_start + VMWGFX_IRQSTATUS_PORT); |
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220 | dev_priv->irq_mask |= SVGA_IRQFLAG_FENCE_GOAL; |
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221 | vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask); |
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222 | spin_unlock_irqrestore(&dev_priv->irq_lock, irq_flags); |
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223 | } |
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224 | mutex_unlock(&dev_priv->hw_mutex); |
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225 | } |
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226 | |||
227 | void vmw_goal_waiter_remove(struct vmw_private *dev_priv) |
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228 | { |
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229 | mutex_lock(&dev_priv->hw_mutex); |
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230 | if (--dev_priv->goal_queue_waiters == 0) { |
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231 | unsigned long irq_flags; |
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232 | |||
233 | spin_lock_irqsave(&dev_priv->irq_lock, irq_flags); |
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234 | dev_priv->irq_mask &= ~SVGA_IRQFLAG_FENCE_GOAL; |
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235 | vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask); |
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236 | spin_unlock_irqrestore(&dev_priv->irq_lock, irq_flags); |
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237 | } |
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238 | mutex_unlock(&dev_priv->hw_mutex); |
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239 | } |
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240 | |||
241 | int vmw_wait_seqno(struct vmw_private *dev_priv, |
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242 | bool lazy, uint32_t seqno, |
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243 | bool interruptible, unsigned long timeout) |
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244 | { |
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245 | long ret; |
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246 | struct vmw_fifo_state *fifo = &dev_priv->fifo; |
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247 | |||
248 | if (likely(dev_priv->last_read_seqno - seqno < VMW_FENCE_WRAP)) |
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249 | return 0; |
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250 | |||
251 | if (likely(vmw_seqno_passed(dev_priv, seqno))) |
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252 | return 0; |
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253 | |||
254 | vmw_fifo_ping_host(dev_priv, SVGA_SYNC_GENERIC); |
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255 | |||
256 | if (!(fifo->capabilities & SVGA_FIFO_CAP_FENCE)) |
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257 | return vmw_fallback_wait(dev_priv, lazy, true, seqno, |
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258 | interruptible, timeout); |
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259 | |||
260 | if (!(dev_priv->capabilities & SVGA_CAP_IRQMASK)) |
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261 | return vmw_fallback_wait(dev_priv, lazy, false, seqno, |
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262 | interruptible, timeout); |
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263 | |||
264 | vmw_seqno_waiter_add(dev_priv); |
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265 | |||
266 | if (interruptible) |
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267 | ret = wait_event_interruptible_timeout |
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268 | (dev_priv->fence_queue, |
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269 | vmw_seqno_passed(dev_priv, seqno), |
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270 | timeout); |
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271 | else |
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272 | ret = wait_event_timeout |
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273 | (dev_priv->fence_queue, |
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274 | vmw_seqno_passed(dev_priv, seqno), |
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275 | timeout); |
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276 | |||
277 | vmw_seqno_waiter_remove(dev_priv); |
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278 | |||
279 | if (unlikely(ret == 0)) |
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280 | ret = -EBUSY; |
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281 | else if (likely(ret > 0)) |
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282 | ret = 0; |
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283 | |||
284 | return ret; |
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285 | } |
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286 | |||
287 | void vmw_irq_preinstall(struct drm_device *dev) |
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288 | { |
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289 | struct vmw_private *dev_priv = vmw_priv(dev); |
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290 | uint32_t status; |
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291 | |||
292 | if (!(dev_priv->capabilities & SVGA_CAP_IRQMASK)) |
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293 | return; |
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294 | |||
295 | spin_lock_init(&dev_priv->irq_lock); |
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296 | status = inl(dev_priv->io_start + VMWGFX_IRQSTATUS_PORT); |
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297 | outl(status, dev_priv->io_start + VMWGFX_IRQSTATUS_PORT); |
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298 | } |
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299 | |||
300 | int vmw_irq_postinstall(struct drm_device *dev) |
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301 | { |
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302 | return 0; |
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303 | } |
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304 | |||
305 | void vmw_irq_uninstall(struct drm_device *dev) |
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306 | { |
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307 | struct vmw_private *dev_priv = vmw_priv(dev); |
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308 | uint32_t status; |
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309 | |||
310 | if (!(dev_priv->capabilities & SVGA_CAP_IRQMASK)) |
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311 | return; |
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312 | |||
313 | mutex_lock(&dev_priv->hw_mutex); |
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314 | vmw_write(dev_priv, SVGA_REG_IRQMASK, 0); |
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315 | mutex_unlock(&dev_priv->hw_mutex); |
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316 | |||
317 | status = inl(dev_priv->io_start + VMWGFX_IRQSTATUS_PORT); |
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318 | outl(status, dev_priv->io_start + VMWGFX_IRQSTATUS_PORT); |
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319 | } |
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320 | |||
321 | int autoremove_wake_function(wait_queue_t *wait, unsigned mode, int sync, void *key) |
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322 | { |
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323 | list_del_init(&wait->task_list); |
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324 | return 1; |
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325 | }>>>><> |
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326 |