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Rev | Author | Line No. | Line |
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4075 | Serge | 1 | /************************************************************************** |
2 | * |
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6296 | serge | 3 | * Copyright © 2009-2015 VMware, Inc., Palo Alto, CA., USA |
4075 | Serge | 4 | * All Rights Reserved. |
5 | * |
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6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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7 | * copy of this software and associated documentation files (the |
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8 | * "Software"), to deal in the Software without restriction, including |
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9 | * without limitation the rights to use, copy, modify, merge, publish, |
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10 | * distribute, sub license, and/or sell copies of the Software, and to |
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11 | * permit persons to whom the Software is furnished to do so, subject to |
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12 | * the following conditions: |
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13 | * |
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14 | * The above copyright notice and this permission notice (including the |
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15 | * next paragraph) shall be included in all copies or substantial portions |
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16 | * of the Software. |
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17 | * |
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18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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20 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL |
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21 | * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, |
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22 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR |
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23 | * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE |
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24 | * USE OR OTHER DEALINGS IN THE SOFTWARE. |
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25 | * |
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26 | **************************************************************************/ |
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27 | #include |
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28 | |||
29 | #include |
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30 | #include "vmwgfx_drv.h" |
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6296 | serge | 31 | #include "vmwgfx_binding.h" |
4075 | Serge | 32 | #include |
33 | #include |
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34 | #include |
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6296 | serge | 35 | #include |
4569 | Serge | 36 | #include |
4075 | Serge | 37 | |
38 | #define VMWGFX_DRIVER_NAME "vmwgfx" |
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39 | #define VMWGFX_DRIVER_DESC "Linux drm driver for VMware graphics devices" |
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40 | #define VMWGFX_CHIP_SVGAII 0 |
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41 | #define VMW_FB_RESERVATION 0 |
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42 | |||
43 | #define VMW_MIN_INITIAL_WIDTH 800 |
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44 | #define VMW_MIN_INITIAL_HEIGHT 600 |
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45 | |||
46 | #if 0 |
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47 | /** |
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48 | * Fully encoded drm commands. Might move to vmw_drm.h |
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49 | */ |
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50 | |||
51 | #define DRM_IOCTL_VMW_GET_PARAM \ |
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52 | DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GET_PARAM, \ |
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53 | struct drm_vmw_getparam_arg) |
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54 | #define DRM_IOCTL_VMW_ALLOC_DMABUF \ |
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55 | DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_ALLOC_DMABUF, \ |
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56 | union drm_vmw_alloc_dmabuf_arg) |
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57 | #define DRM_IOCTL_VMW_UNREF_DMABUF \ |
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58 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_DMABUF, \ |
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59 | struct drm_vmw_unref_dmabuf_arg) |
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60 | #define DRM_IOCTL_VMW_CURSOR_BYPASS \ |
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61 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CURSOR_BYPASS, \ |
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62 | struct drm_vmw_cursor_bypass_arg) |
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63 | |||
64 | #define DRM_IOCTL_VMW_CONTROL_STREAM \ |
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65 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CONTROL_STREAM, \ |
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66 | struct drm_vmw_control_stream_arg) |
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67 | #define DRM_IOCTL_VMW_CLAIM_STREAM \ |
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68 | DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CLAIM_STREAM, \ |
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69 | struct drm_vmw_stream_arg) |
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70 | #define DRM_IOCTL_VMW_UNREF_STREAM \ |
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71 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_STREAM, \ |
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72 | struct drm_vmw_stream_arg) |
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73 | |||
74 | #define DRM_IOCTL_VMW_CREATE_CONTEXT \ |
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75 | DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CREATE_CONTEXT, \ |
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76 | struct drm_vmw_context_arg) |
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77 | #define DRM_IOCTL_VMW_UNREF_CONTEXT \ |
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78 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_CONTEXT, \ |
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79 | struct drm_vmw_context_arg) |
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80 | #define DRM_IOCTL_VMW_CREATE_SURFACE \ |
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81 | DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SURFACE, \ |
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82 | union drm_vmw_surface_create_arg) |
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83 | #define DRM_IOCTL_VMW_UNREF_SURFACE \ |
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84 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SURFACE, \ |
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85 | struct drm_vmw_surface_arg) |
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86 | #define DRM_IOCTL_VMW_REF_SURFACE \ |
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87 | DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_REF_SURFACE, \ |
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88 | union drm_vmw_surface_reference_arg) |
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89 | #define DRM_IOCTL_VMW_EXECBUF \ |
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90 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_EXECBUF, \ |
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91 | struct drm_vmw_execbuf_arg) |
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92 | #define DRM_IOCTL_VMW_GET_3D_CAP \ |
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93 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_GET_3D_CAP, \ |
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94 | struct drm_vmw_get_3d_cap_arg) |
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95 | #define DRM_IOCTL_VMW_FENCE_WAIT \ |
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96 | DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_WAIT, \ |
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97 | struct drm_vmw_fence_wait_arg) |
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98 | #define DRM_IOCTL_VMW_FENCE_SIGNALED \ |
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99 | DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_SIGNALED, \ |
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100 | struct drm_vmw_fence_signaled_arg) |
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101 | #define DRM_IOCTL_VMW_FENCE_UNREF \ |
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102 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_UNREF, \ |
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103 | struct drm_vmw_fence_arg) |
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104 | #define DRM_IOCTL_VMW_FENCE_EVENT \ |
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105 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_EVENT, \ |
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106 | struct drm_vmw_fence_event_arg) |
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107 | #define DRM_IOCTL_VMW_PRESENT \ |
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108 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT, \ |
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109 | struct drm_vmw_present_arg) |
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110 | #define DRM_IOCTL_VMW_PRESENT_READBACK \ |
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111 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT_READBACK, \ |
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112 | struct drm_vmw_present_readback_arg) |
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113 | #define DRM_IOCTL_VMW_UPDATE_LAYOUT \ |
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114 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT, \ |
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115 | struct drm_vmw_update_layout_arg) |
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4569 | Serge | 116 | #define DRM_IOCTL_VMW_CREATE_SHADER \ |
117 | DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SHADER, \ |
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118 | struct drm_vmw_shader_create_arg) |
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119 | #define DRM_IOCTL_VMW_UNREF_SHADER \ |
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120 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SHADER, \ |
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121 | struct drm_vmw_shader_arg) |
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122 | #define DRM_IOCTL_VMW_GB_SURFACE_CREATE \ |
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123 | DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_CREATE, \ |
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124 | union drm_vmw_gb_surface_create_arg) |
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125 | #define DRM_IOCTL_VMW_GB_SURFACE_REF \ |
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126 | DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_REF, \ |
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127 | union drm_vmw_gb_surface_reference_arg) |
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128 | #define DRM_IOCTL_VMW_SYNCCPU \ |
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129 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_SYNCCPU, \ |
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130 | struct drm_vmw_synccpu_arg) |
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6296 | serge | 131 | #define DRM_IOCTL_VMW_CREATE_EXTENDED_CONTEXT \ |
132 | DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_EXTENDED_CONTEXT, \ |
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133 | struct drm_vmw_context_arg) |
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4075 | Serge | 134 | |
135 | /** |
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136 | * The core DRM version of this macro doesn't account for |
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137 | * DRM_COMMAND_BASE. |
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138 | */ |
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139 | |||
140 | #define VMW_IOCTL_DEF(ioctl, func, flags) \ |
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6296 | serge | 141 | [DRM_IOCTL_NR(DRM_IOCTL_##ioctl) - DRM_COMMAND_BASE] = {DRM_IOCTL_##ioctl, flags, func} |
4075 | Serge | 142 | |
143 | /** |
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144 | * Ioctl definitions. |
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145 | */ |
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146 | |||
4111 | Serge | 147 | static const struct drm_ioctl_desc vmw_ioctls[] = { |
4075 | Serge | 148 | VMW_IOCTL_DEF(VMW_GET_PARAM, vmw_getparam_ioctl, |
6296 | serge | 149 | DRM_AUTH | DRM_RENDER_ALLOW), |
4075 | Serge | 150 | VMW_IOCTL_DEF(VMW_ALLOC_DMABUF, vmw_dmabuf_alloc_ioctl, |
6296 | serge | 151 | DRM_AUTH | DRM_RENDER_ALLOW), |
4075 | Serge | 152 | VMW_IOCTL_DEF(VMW_UNREF_DMABUF, vmw_dmabuf_unref_ioctl, |
6296 | serge | 153 | DRM_RENDER_ALLOW), |
4075 | Serge | 154 | VMW_IOCTL_DEF(VMW_CURSOR_BYPASS, |
155 | vmw_kms_cursor_bypass_ioctl, |
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6296 | serge | 156 | DRM_MASTER | DRM_CONTROL_ALLOW), |
4075 | Serge | 157 | |
158 | VMW_IOCTL_DEF(VMW_CONTROL_STREAM, vmw_overlay_ioctl, |
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6296 | serge | 159 | DRM_MASTER | DRM_CONTROL_ALLOW), |
4075 | Serge | 160 | VMW_IOCTL_DEF(VMW_CLAIM_STREAM, vmw_stream_claim_ioctl, |
6296 | serge | 161 | DRM_MASTER | DRM_CONTROL_ALLOW), |
4075 | Serge | 162 | VMW_IOCTL_DEF(VMW_UNREF_STREAM, vmw_stream_unref_ioctl, |
6296 | serge | 163 | DRM_MASTER | DRM_CONTROL_ALLOW), |
4075 | Serge | 164 | |
165 | VMW_IOCTL_DEF(VMW_CREATE_CONTEXT, vmw_context_define_ioctl, |
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6296 | serge | 166 | DRM_AUTH | DRM_RENDER_ALLOW), |
4075 | Serge | 167 | VMW_IOCTL_DEF(VMW_UNREF_CONTEXT, vmw_context_destroy_ioctl, |
6296 | serge | 168 | DRM_RENDER_ALLOW), |
4075 | Serge | 169 | VMW_IOCTL_DEF(VMW_CREATE_SURFACE, vmw_surface_define_ioctl, |
6296 | serge | 170 | DRM_AUTH | DRM_RENDER_ALLOW), |
4075 | Serge | 171 | VMW_IOCTL_DEF(VMW_UNREF_SURFACE, vmw_surface_destroy_ioctl, |
6296 | serge | 172 | DRM_RENDER_ALLOW), |
4075 | Serge | 173 | VMW_IOCTL_DEF(VMW_REF_SURFACE, vmw_surface_reference_ioctl, |
6296 | serge | 174 | DRM_AUTH | DRM_RENDER_ALLOW), |
175 | VMW_IOCTL_DEF(VMW_EXECBUF, NULL, DRM_AUTH | |
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176 | DRM_RENDER_ALLOW), |
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4075 | Serge | 177 | VMW_IOCTL_DEF(VMW_FENCE_WAIT, vmw_fence_obj_wait_ioctl, |
6296 | serge | 178 | DRM_RENDER_ALLOW), |
4075 | Serge | 179 | VMW_IOCTL_DEF(VMW_FENCE_SIGNALED, |
180 | vmw_fence_obj_signaled_ioctl, |
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6296 | serge | 181 | DRM_RENDER_ALLOW), |
4075 | Serge | 182 | VMW_IOCTL_DEF(VMW_FENCE_UNREF, vmw_fence_obj_unref_ioctl, |
6296 | serge | 183 | DRM_RENDER_ALLOW), |
5078 | serge | 184 | VMW_IOCTL_DEF(VMW_FENCE_EVENT, vmw_fence_event_ioctl, |
6296 | serge | 185 | DRM_AUTH | DRM_RENDER_ALLOW), |
4075 | Serge | 186 | VMW_IOCTL_DEF(VMW_GET_3D_CAP, vmw_get_cap_3d_ioctl, |
6296 | serge | 187 | DRM_AUTH | DRM_RENDER_ALLOW), |
4075 | Serge | 188 | |
189 | /* these allow direct access to the framebuffers mark as master only */ |
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190 | VMW_IOCTL_DEF(VMW_PRESENT, vmw_present_ioctl, |
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6296 | serge | 191 | DRM_MASTER | DRM_AUTH), |
4075 | Serge | 192 | VMW_IOCTL_DEF(VMW_PRESENT_READBACK, |
193 | vmw_present_readback_ioctl, |
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6296 | serge | 194 | DRM_MASTER | DRM_AUTH), |
4075 | Serge | 195 | VMW_IOCTL_DEF(VMW_UPDATE_LAYOUT, |
196 | vmw_kms_update_layout_ioctl, |
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6296 | serge | 197 | DRM_MASTER), |
4569 | Serge | 198 | VMW_IOCTL_DEF(VMW_CREATE_SHADER, |
199 | vmw_shader_define_ioctl, |
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6296 | serge | 200 | DRM_AUTH | DRM_RENDER_ALLOW), |
4569 | Serge | 201 | VMW_IOCTL_DEF(VMW_UNREF_SHADER, |
202 | vmw_shader_destroy_ioctl, |
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6296 | serge | 203 | DRM_RENDER_ALLOW), |
4569 | Serge | 204 | VMW_IOCTL_DEF(VMW_GB_SURFACE_CREATE, |
205 | vmw_gb_surface_define_ioctl, |
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6296 | serge | 206 | DRM_AUTH | DRM_RENDER_ALLOW), |
4569 | Serge | 207 | VMW_IOCTL_DEF(VMW_GB_SURFACE_REF, |
208 | vmw_gb_surface_reference_ioctl, |
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6296 | serge | 209 | DRM_AUTH | DRM_RENDER_ALLOW), |
4569 | Serge | 210 | VMW_IOCTL_DEF(VMW_SYNCCPU, |
211 | vmw_user_dmabuf_synccpu_ioctl, |
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6296 | serge | 212 | DRM_RENDER_ALLOW), |
213 | VMW_IOCTL_DEF(VMW_CREATE_EXTENDED_CONTEXT, |
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214 | vmw_extended_context_define_ioctl, |
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215 | DRM_AUTH | DRM_RENDER_ALLOW), |
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4075 | Serge | 216 | }; |
217 | #endif |
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218 | |||
219 | static struct pci_device_id vmw_pci_id_list[] = { |
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220 | {0x15ad, 0x0405, PCI_ANY_ID, PCI_ANY_ID, 0, 0, VMWGFX_CHIP_SVGAII}, |
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221 | {0, 0, 0} |
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222 | }; |
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223 | |||
224 | static int enable_fbdev = 1; |
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4569 | Serge | 225 | static int vmw_force_iommu; |
226 | static int vmw_restrict_iommu; |
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227 | static int vmw_force_coherent; |
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228 | static int vmw_restrict_dma_mask; |
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4075 | Serge | 229 | |
230 | static int vmw_probe(struct pci_dev *, const struct pci_device_id *); |
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231 | static void vmw_master_init(struct vmw_master *); |
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232 | |||
233 | MODULE_PARM_DESC(enable_fbdev, "Enable vmwgfx fbdev"); |
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234 | module_param_named(enable_fbdev, enable_fbdev, int, 0600); |
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4569 | Serge | 235 | MODULE_PARM_DESC(force_dma_api, "Force using the DMA API for TTM pages"); |
236 | module_param_named(force_dma_api, vmw_force_iommu, int, 0600); |
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237 | MODULE_PARM_DESC(restrict_iommu, "Try to limit IOMMU usage for TTM pages"); |
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238 | module_param_named(restrict_iommu, vmw_restrict_iommu, int, 0600); |
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239 | MODULE_PARM_DESC(force_coherent, "Force coherent TTM pages"); |
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240 | module_param_named(force_coherent, vmw_force_coherent, int, 0600); |
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241 | MODULE_PARM_DESC(restrict_dma_mask, "Restrict DMA mask to 44 bits with IOMMU"); |
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242 | module_param_named(restrict_dma_mask, vmw_restrict_dma_mask, int, 0600); |
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4075 | Serge | 243 | |
4569 | Serge | 244 | |
4075 | Serge | 245 | static void vmw_print_capabilities(uint32_t capabilities) |
246 | { |
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247 | DRM_INFO("Capabilities:\n"); |
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248 | if (capabilities & SVGA_CAP_RECT_COPY) |
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249 | DRM_INFO(" Rect copy.\n"); |
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250 | if (capabilities & SVGA_CAP_CURSOR) |
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251 | DRM_INFO(" Cursor.\n"); |
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252 | if (capabilities & SVGA_CAP_CURSOR_BYPASS) |
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253 | DRM_INFO(" Cursor bypass.\n"); |
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254 | if (capabilities & SVGA_CAP_CURSOR_BYPASS_2) |
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255 | DRM_INFO(" Cursor bypass 2.\n"); |
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256 | if (capabilities & SVGA_CAP_8BIT_EMULATION) |
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257 | DRM_INFO(" 8bit emulation.\n"); |
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258 | if (capabilities & SVGA_CAP_ALPHA_CURSOR) |
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259 | DRM_INFO(" Alpha cursor.\n"); |
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260 | if (capabilities & SVGA_CAP_3D) |
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261 | DRM_INFO(" 3D.\n"); |
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262 | if (capabilities & SVGA_CAP_EXTENDED_FIFO) |
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263 | DRM_INFO(" Extended Fifo.\n"); |
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264 | if (capabilities & SVGA_CAP_MULTIMON) |
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265 | DRM_INFO(" Multimon.\n"); |
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266 | if (capabilities & SVGA_CAP_PITCHLOCK) |
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267 | DRM_INFO(" Pitchlock.\n"); |
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268 | if (capabilities & SVGA_CAP_IRQMASK) |
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269 | DRM_INFO(" Irq mask.\n"); |
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270 | if (capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) |
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271 | DRM_INFO(" Display Topology.\n"); |
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272 | if (capabilities & SVGA_CAP_GMR) |
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273 | DRM_INFO(" GMR.\n"); |
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274 | if (capabilities & SVGA_CAP_TRACES) |
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275 | DRM_INFO(" Traces.\n"); |
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276 | if (capabilities & SVGA_CAP_GMR2) |
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277 | DRM_INFO(" GMR2.\n"); |
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278 | if (capabilities & SVGA_CAP_SCREEN_OBJECT_2) |
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279 | DRM_INFO(" Screen Object 2.\n"); |
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4569 | Serge | 280 | if (capabilities & SVGA_CAP_COMMAND_BUFFERS) |
281 | DRM_INFO(" Command Buffers.\n"); |
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282 | if (capabilities & SVGA_CAP_CMD_BUFFERS_2) |
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283 | DRM_INFO(" Command Buffers 2.\n"); |
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284 | if (capabilities & SVGA_CAP_GBOBJECTS) |
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285 | DRM_INFO(" Guest Backed Resources.\n"); |
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6296 | serge | 286 | if (capabilities & SVGA_CAP_DX) |
287 | DRM_INFO(" DX Features.\n"); |
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4075 | Serge | 288 | } |
289 | |||
290 | /** |
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4569 | Serge | 291 | * vmw_dummy_query_bo_create - create a bo to hold a dummy query result |
4075 | Serge | 292 | * |
4569 | Serge | 293 | * @dev_priv: A device private structure. |
4075 | Serge | 294 | * |
4569 | Serge | 295 | * This function creates a small buffer object that holds the query |
296 | * result for dummy queries emitted as query barriers. |
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297 | * The function will then map the first page and initialize a pending |
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298 | * occlusion query result structure, Finally it will unmap the buffer. |
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299 | * No interruptible waits are done within this function. |
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4075 | Serge | 300 | * |
4569 | Serge | 301 | * Returns an error if bo creation or initialization fails. |
4075 | Serge | 302 | */ |
4569 | Serge | 303 | static int vmw_dummy_query_bo_create(struct vmw_private *dev_priv) |
4075 | Serge | 304 | { |
4569 | Serge | 305 | int ret; |
6296 | serge | 306 | struct vmw_dma_buffer *vbo; |
4075 | Serge | 307 | struct ttm_bo_kmap_obj map; |
308 | volatile SVGA3dQueryResult *result; |
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309 | bool dummy; |
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310 | |||
4569 | Serge | 311 | /* |
6296 | serge | 312 | * Create the vbo as pinned, so that a tryreserve will |
4569 | Serge | 313 | * immediately succeed. This is because we're the only |
314 | * user of the bo currently. |
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315 | */ |
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6296 | serge | 316 | vbo = kzalloc(sizeof(*vbo), GFP_KERNEL); |
317 | if (!vbo) |
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318 | return -ENOMEM; |
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4569 | Serge | 319 | |
6296 | serge | 320 | ret = vmw_dmabuf_init(dev_priv, vbo, PAGE_SIZE, |
321 | &vmw_sys_ne_placement, false, |
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322 | &vmw_dmabuf_bo_free); |
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4075 | Serge | 323 | if (unlikely(ret != 0)) |
4569 | Serge | 324 | return ret; |
325 | |||
6296 | serge | 326 | ret = ttm_bo_reserve(&vbo->base, false, true, false, NULL); |
4569 | Serge | 327 | BUG_ON(ret != 0); |
6296 | serge | 328 | vmw_bo_pin_reserved(vbo, true); |
4569 | Serge | 329 | |
6296 | serge | 330 | ret = ttm_bo_kmap(&vbo->base, 0, 1, &map); |
4075 | Serge | 331 | if (likely(ret == 0)) { |
332 | result = ttm_kmap_obj_virtual(&map, &dummy); |
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333 | result->totalSize = sizeof(*result); |
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334 | result->state = SVGA3D_QUERYSTATE_PENDING; |
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335 | result->result32 = 0xff; |
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336 | ttm_bo_kunmap(&map); |
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4569 | Serge | 337 | } |
6296 | serge | 338 | vmw_bo_pin_reserved(vbo, false); |
339 | ttm_bo_unreserve(&vbo->base); |
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4075 | Serge | 340 | |
4569 | Serge | 341 | if (unlikely(ret != 0)) { |
342 | DRM_ERROR("Dummy query buffer map failed.\n"); |
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6296 | serge | 343 | vmw_dmabuf_unreference(&vbo); |
4569 | Serge | 344 | } else |
6296 | serge | 345 | dev_priv->dummy_query_bo = vbo; |
4075 | Serge | 346 | |
4569 | Serge | 347 | return ret; |
4075 | Serge | 348 | } |
349 | |||
6296 | serge | 350 | /** |
351 | * vmw_request_device_late - Perform late device setup |
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352 | * |
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353 | * @dev_priv: Pointer to device private. |
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354 | * |
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355 | * This function performs setup of otables and enables large command |
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356 | * buffer submission. These tasks are split out to a separate function |
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357 | * because it reverts vmw_release_device_early and is intended to be used |
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358 | * by an error path in the hibernation code. |
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359 | */ |
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360 | static int vmw_request_device_late(struct vmw_private *dev_priv) |
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361 | { |
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362 | int ret; |
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363 | |||
364 | if (dev_priv->has_mob) { |
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365 | ret = vmw_otables_setup(dev_priv); |
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366 | if (unlikely(ret != 0)) { |
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367 | DRM_ERROR("Unable to initialize " |
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368 | "guest Memory OBjects.\n"); |
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369 | return ret; |
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370 | } |
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371 | } |
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372 | |||
373 | if (dev_priv->cman) { |
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374 | ret = vmw_cmdbuf_set_pool_size(dev_priv->cman, |
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375 | 256*4096, 2*4096); |
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376 | if (ret) { |
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377 | struct vmw_cmdbuf_man *man = dev_priv->cman; |
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378 | |||
379 | dev_priv->cman = NULL; |
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380 | vmw_cmdbuf_man_destroy(man); |
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381 | } |
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382 | } |
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383 | |||
384 | return 0; |
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385 | } |
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386 | |||
4075 | Serge | 387 | static int vmw_request_device(struct vmw_private *dev_priv) |
388 | { |
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389 | int ret; |
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390 | |||
391 | ret = vmw_fifo_init(dev_priv, &dev_priv->fifo); |
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392 | if (unlikely(ret != 0)) { |
||
393 | DRM_ERROR("Unable to initialize FIFO.\n"); |
||
394 | return ret; |
||
395 | } |
||
6296 | serge | 396 | vmw_fence_fifo_up(dev_priv->fman); |
397 | dev_priv->cman = vmw_cmdbuf_man_create(dev_priv); |
||
398 | if (IS_ERR(dev_priv->cman)) { |
||
399 | dev_priv->cman = NULL; |
||
400 | dev_priv->has_dx = false; |
||
401 | } |
||
4075 | Serge | 402 | |
6296 | serge | 403 | ret = vmw_request_device_late(dev_priv); |
404 | if (ret) |
||
405 | goto out_no_mob; |
||
4075 | Serge | 406 | |
6296 | serge | 407 | ret = vmw_dummy_query_bo_create(dev_priv); |
408 | if (unlikely(ret != 0)) |
||
409 | goto out_no_query_bo; |
||
5078 | serge | 410 | |
4075 | Serge | 411 | return 0; |
412 | |||
413 | out_no_query_bo: |
||
6296 | serge | 414 | if (dev_priv->cman) |
415 | vmw_cmdbuf_remove_pool(dev_priv->cman); |
||
416 | if (dev_priv->has_mob) { |
||
417 | // (void) ttm_bo_evict_mm(&dev_priv->bdev, VMW_PL_MOB); |
||
418 | vmw_otables_takedown(dev_priv); |
||
419 | } |
||
420 | if (dev_priv->cman) |
||
421 | vmw_cmdbuf_man_destroy(dev_priv->cman); |
||
422 | out_no_mob: |
||
4075 | Serge | 423 | vmw_fence_fifo_down(dev_priv->fman); |
424 | vmw_fifo_release(dev_priv, &dev_priv->fifo); |
||
425 | return ret; |
||
426 | } |
||
427 | |||
6296 | serge | 428 | /** |
429 | * vmw_release_device_early - Early part of fifo takedown. |
||
430 | * |
||
431 | * @dev_priv: Pointer to device private struct. |
||
432 | * |
||
433 | * This is the first part of command submission takedown, to be called before |
||
434 | * buffer management is taken down. |
||
435 | */ |
||
436 | static void vmw_release_device_early(struct vmw_private *dev_priv) |
||
4075 | Serge | 437 | { |
438 | /* |
||
439 | * Previous destructions should've released |
||
440 | * the pinned bo. |
||
441 | */ |
||
442 | |||
443 | BUG_ON(dev_priv->pinned_bo != NULL); |
||
444 | |||
6296 | serge | 445 | vmw_dmabuf_unreference(&dev_priv->dummy_query_bo); |
446 | if (dev_priv->cman) |
||
447 | vmw_cmdbuf_remove_pool(dev_priv->cman); |
||
4075 | Serge | 448 | |
6296 | serge | 449 | if (dev_priv->has_mob) { |
450 | ttm_bo_evict_mm(&dev_priv->bdev, VMW_PL_MOB); |
||
451 | vmw_otables_takedown(dev_priv); |
||
4075 | Serge | 452 | } |
453 | } |
||
454 | |||
455 | /** |
||
6296 | serge | 456 | * vmw_release_device_late - Late part of fifo takedown. |
457 | * |
||
458 | * @dev_priv: Pointer to device private struct. |
||
459 | * |
||
460 | * This is the last part of the command submission takedown, to be called when |
||
461 | * command submission is no longer needed. It may wait on pending fences. |
||
4075 | Serge | 462 | */ |
6296 | serge | 463 | static void vmw_release_device_late(struct vmw_private *dev_priv) |
4075 | Serge | 464 | { |
6296 | serge | 465 | vmw_fence_fifo_down(dev_priv->fman); |
466 | if (dev_priv->cman) |
||
467 | vmw_cmdbuf_man_destroy(dev_priv->cman); |
||
4075 | Serge | 468 | |
6296 | serge | 469 | vmw_fifo_release(dev_priv, &dev_priv->fifo); |
4075 | Serge | 470 | } |
471 | |||
472 | /** |
||
473 | * Sets the initial_[width|height] fields on the given vmw_private. |
||
474 | * |
||
475 | * It does so by reading SVGA_REG_[WIDTH|HEIGHT] regs and then |
||
476 | * clamping the value to fb_max_[width|height] fields and the |
||
477 | * VMW_MIN_INITIAL_[WIDTH|HEIGHT]. |
||
478 | * If the values appear to be invalid, set them to |
||
479 | * VMW_MIN_INITIAL_[WIDTH|HEIGHT]. |
||
480 | */ |
||
481 | static void vmw_get_initial_size(struct vmw_private *dev_priv) |
||
482 | { |
||
483 | uint32_t width; |
||
484 | uint32_t height; |
||
485 | |||
486 | width = vmw_read(dev_priv, SVGA_REG_WIDTH); |
||
487 | height = vmw_read(dev_priv, SVGA_REG_HEIGHT); |
||
488 | |||
489 | width = max_t(uint32_t, width, VMW_MIN_INITIAL_WIDTH); |
||
490 | height = max_t(uint32_t, height, VMW_MIN_INITIAL_HEIGHT); |
||
491 | |||
492 | if (width > dev_priv->fb_max_width || |
||
493 | height > dev_priv->fb_max_height) { |
||
494 | |||
495 | /* |
||
496 | * This is a host error and shouldn't occur. |
||
497 | */ |
||
498 | |||
499 | width = VMW_MIN_INITIAL_WIDTH; |
||
500 | height = VMW_MIN_INITIAL_HEIGHT; |
||
501 | } |
||
502 | |||
503 | dev_priv->initial_width = width; |
||
504 | dev_priv->initial_height = height; |
||
505 | } |
||
506 | |||
4569 | Serge | 507 | /** |
4570 | Serge | 508 | * vmw_dma_select_mode - Determine how DMA mappings should be set up for this |
509 | * system. |
||
510 | * |
||
511 | * @dev_priv: Pointer to a struct vmw_private |
||
512 | * |
||
513 | * This functions tries to determine the IOMMU setup and what actions |
||
514 | * need to be taken by the driver to make system pages visible to the |
||
515 | * device. |
||
516 | * If this function decides that DMA is not possible, it returns -EINVAL. |
||
517 | * The driver may then try to disable features of the device that require |
||
518 | * DMA. |
||
519 | */ |
||
520 | static int vmw_dma_select_mode(struct vmw_private *dev_priv) |
||
521 | { |
||
522 | static const char *names[vmw_dma_map_max] = { |
||
523 | [vmw_dma_phys] = "Using physical TTM page addresses.", |
||
524 | [vmw_dma_alloc_coherent] = "Using coherent TTM pages.", |
||
525 | [vmw_dma_map_populate] = "Keeping DMA mappings.", |
||
526 | [vmw_dma_map_bind] = "Giving up DMA mappings early."}; |
||
6296 | serge | 527 | #ifdef CONFIG_X86 |
528 | const struct dma_map_ops *dma_ops = get_dma_ops(dev_priv->dev->dev); |
||
4570 | Serge | 529 | |
6296 | serge | 530 | #ifdef CONFIG_INTEL_IOMMU |
531 | if (intel_iommu_enabled) { |
||
532 | dev_priv->map_mode = vmw_dma_map_populate; |
||
533 | goto out_fixup; |
||
534 | } |
||
535 | #endif |
||
4570 | Serge | 536 | |
6296 | serge | 537 | if (!(vmw_force_iommu || vmw_force_coherent)) { |
538 | dev_priv->map_mode = vmw_dma_phys; |
||
539 | DRM_INFO("DMA map mode: %s\n", names[dev_priv->map_mode]); |
||
540 | return 0; |
||
541 | } |
||
542 | |||
543 | dev_priv->map_mode = vmw_dma_map_populate; |
||
544 | |||
545 | if (dma_ops->sync_single_for_cpu) |
||
546 | dev_priv->map_mode = vmw_dma_alloc_coherent; |
||
547 | #ifdef CONFIG_SWIOTLB |
||
548 | if (swiotlb_nr_tbl() == 0) |
||
549 | dev_priv->map_mode = vmw_dma_map_populate; |
||
550 | #endif |
||
551 | |||
552 | #ifdef CONFIG_INTEL_IOMMU |
||
553 | out_fixup: |
||
554 | #endif |
||
555 | if (dev_priv->map_mode == vmw_dma_map_populate && |
||
556 | vmw_restrict_iommu) |
||
557 | dev_priv->map_mode = vmw_dma_map_bind; |
||
558 | |||
559 | if (vmw_force_coherent) |
||
560 | dev_priv->map_mode = vmw_dma_alloc_coherent; |
||
561 | |||
562 | #if !defined(CONFIG_SWIOTLB) && !defined(CONFIG_INTEL_IOMMU) |
||
563 | /* |
||
564 | * No coherent page pool |
||
565 | */ |
||
566 | if (dev_priv->map_mode == vmw_dma_alloc_coherent) |
||
567 | return -EINVAL; |
||
568 | #endif |
||
569 | |||
570 | #else /* CONFIG_X86 */ |
||
571 | dev_priv->map_mode = vmw_dma_map_populate; |
||
572 | #endif /* CONFIG_X86 */ |
||
573 | |||
574 | DRM_INFO("DMA map mode: %s\n", names[dev_priv->map_mode]); |
||
575 | |||
4570 | Serge | 576 | return 0; |
577 | } |
||
578 | |||
579 | /** |
||
4569 | Serge | 580 | * vmw_dma_masks - set required page- and dma masks |
581 | * |
||
582 | * @dev: Pointer to struct drm-device |
||
583 | * |
||
584 | * With 32-bit we can only handle 32 bit PFNs. Optionally set that |
||
585 | * restriction also for 64-bit systems. |
||
586 | */ |
||
587 | #ifdef CONFIG_INTEL_IOMMU |
||
588 | static int vmw_dma_masks(struct vmw_private *dev_priv) |
||
589 | { |
||
590 | struct drm_device *dev = dev_priv->dev; |
||
591 | |||
592 | if (intel_iommu_enabled && |
||
593 | (sizeof(unsigned long) == 4 || vmw_restrict_dma_mask)) { |
||
594 | DRM_INFO("Restricting DMA addresses to 44 bits.\n"); |
||
595 | return dma_set_mask(dev->dev, DMA_BIT_MASK(44)); |
||
596 | } |
||
597 | return 0; |
||
598 | } |
||
599 | #else |
||
600 | static int vmw_dma_masks(struct vmw_private *dev_priv) |
||
601 | { |
||
602 | return 0; |
||
603 | } |
||
604 | #endif |
||
605 | |||
4075 | Serge | 606 | static int vmw_driver_load(struct drm_device *dev, unsigned long chipset) |
607 | { |
||
608 | struct vmw_private *dev_priv; |
||
609 | int ret; |
||
610 | uint32_t svga_id; |
||
611 | enum vmw_res_type i; |
||
4569 | Serge | 612 | bool refuse_dma = false; |
4075 | Serge | 613 | |
614 | dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL); |
||
615 | if (unlikely(dev_priv == NULL)) { |
||
616 | DRM_ERROR("Failed allocating a device private struct.\n"); |
||
617 | return -ENOMEM; |
||
618 | } |
||
619 | |||
620 | pci_set_master(dev->pdev); |
||
621 | |||
622 | dev_priv->dev = dev; |
||
623 | dev_priv->vmw_chipset = chipset; |
||
624 | dev_priv->last_read_seqno = (uint32_t) -100; |
||
625 | mutex_init(&dev_priv->cmdbuf_mutex); |
||
626 | mutex_init(&dev_priv->release_mutex); |
||
4569 | Serge | 627 | mutex_init(&dev_priv->binding_mutex); |
4075 | Serge | 628 | rwlock_init(&dev_priv->resource_lock); |
5078 | serge | 629 | ttm_lock_init(&dev_priv->reservation_sem); |
6296 | serge | 630 | spin_lock_init(&dev_priv->hw_lock); |
631 | spin_lock_init(&dev_priv->waiter_lock); |
||
632 | spin_lock_init(&dev_priv->cap_lock); |
||
633 | spin_lock_init(&dev_priv->svga_lock); |
||
4075 | Serge | 634 | |
635 | for (i = vmw_res_context; i < vmw_res_max; ++i) { |
||
636 | idr_init(&dev_priv->res_idr[i]); |
||
637 | INIT_LIST_HEAD(&dev_priv->res_lru[i]); |
||
638 | } |
||
639 | |||
640 | mutex_init(&dev_priv->init_mutex); |
||
641 | init_waitqueue_head(&dev_priv->fence_queue); |
||
642 | init_waitqueue_head(&dev_priv->fifo_queue); |
||
643 | dev_priv->fence_queue_waiters = 0; |
||
6296 | serge | 644 | dev_priv->fifo_queue_waiters = 0; |
4075 | Serge | 645 | |
646 | dev_priv->used_memory_size = 0; |
||
647 | |||
648 | dev_priv->io_start = pci_resource_start(dev->pdev, 0); |
||
649 | dev_priv->vram_start = pci_resource_start(dev->pdev, 1); |
||
650 | dev_priv->mmio_start = pci_resource_start(dev->pdev, 2); |
||
651 | |||
652 | dev_priv->enable_fb = enable_fbdev; |
||
653 | |||
6296 | serge | 654 | vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2); |
4075 | Serge | 655 | svga_id = vmw_read(dev_priv, SVGA_REG_ID); |
656 | if (svga_id != SVGA_ID_2) { |
||
657 | ret = -ENOSYS; |
||
658 | DRM_ERROR("Unsupported SVGA ID 0x%x\n", svga_id); |
||
659 | goto out_err0; |
||
660 | } |
||
661 | |||
662 | dev_priv->capabilities = vmw_read(dev_priv, SVGA_REG_CAPABILITIES); |
||
4570 | Serge | 663 | ret = vmw_dma_select_mode(dev_priv); |
664 | if (unlikely(ret != 0)) { |
||
665 | DRM_INFO("Restricting capabilities due to IOMMU setup.\n"); |
||
666 | refuse_dma = true; |
||
667 | } |
||
4075 | Serge | 668 | |
669 | dev_priv->vram_size = vmw_read(dev_priv, SVGA_REG_VRAM_SIZE); |
||
670 | dev_priv->mmio_size = vmw_read(dev_priv, SVGA_REG_MEM_SIZE); |
||
671 | dev_priv->fb_max_width = vmw_read(dev_priv, SVGA_REG_MAX_WIDTH); |
||
672 | dev_priv->fb_max_height = vmw_read(dev_priv, SVGA_REG_MAX_HEIGHT); |
||
673 | |||
674 | vmw_get_initial_size(dev_priv); |
||
675 | |||
4569 | Serge | 676 | if (dev_priv->capabilities & SVGA_CAP_GMR2) { |
4075 | Serge | 677 | dev_priv->max_gmr_ids = |
678 | vmw_read(dev_priv, SVGA_REG_GMR_MAX_IDS); |
||
679 | dev_priv->max_gmr_pages = |
||
680 | vmw_read(dev_priv, SVGA_REG_GMRS_MAX_PAGES); |
||
681 | dev_priv->memory_size = |
||
682 | vmw_read(dev_priv, SVGA_REG_MEMORY_SIZE); |
||
683 | dev_priv->memory_size -= dev_priv->vram_size; |
||
684 | } else { |
||
685 | /* |
||
686 | * An arbitrary limit of 512MiB on surface |
||
687 | * memory. But all HWV8 hardware supports GMR2. |
||
688 | */ |
||
689 | dev_priv->memory_size = 512*1024*1024; |
||
690 | } |
||
4569 | Serge | 691 | dev_priv->max_mob_pages = 0; |
5078 | serge | 692 | dev_priv->max_mob_size = 0; |
4569 | Serge | 693 | if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) { |
694 | uint64_t mem_size = |
||
695 | vmw_read(dev_priv, |
||
696 | SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB); |
||
4075 | Serge | 697 | |
4569 | Serge | 698 | dev_priv->max_mob_pages = mem_size * 1024 / PAGE_SIZE; |
699 | dev_priv->prim_bb_mem = |
||
700 | vmw_read(dev_priv, |
||
701 | SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM); |
||
5078 | serge | 702 | dev_priv->max_mob_size = |
703 | vmw_read(dev_priv, SVGA_REG_MOB_MAX_SIZE); |
||
6296 | serge | 704 | dev_priv->stdu_max_width = |
705 | vmw_read(dev_priv, SVGA_REG_SCREENTARGET_MAX_WIDTH); |
||
706 | dev_priv->stdu_max_height = |
||
707 | vmw_read(dev_priv, SVGA_REG_SCREENTARGET_MAX_HEIGHT); |
||
708 | |||
709 | vmw_write(dev_priv, SVGA_REG_DEV_CAP, |
||
710 | SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH); |
||
711 | dev_priv->texture_max_width = vmw_read(dev_priv, |
||
712 | SVGA_REG_DEV_CAP); |
||
713 | vmw_write(dev_priv, SVGA_REG_DEV_CAP, |
||
714 | SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT); |
||
715 | dev_priv->texture_max_height = vmw_read(dev_priv, |
||
716 | SVGA_REG_DEV_CAP); |
||
717 | } else { |
||
718 | dev_priv->texture_max_width = 8192; |
||
719 | dev_priv->texture_max_height = 8192; |
||
4569 | Serge | 720 | dev_priv->prim_bb_mem = dev_priv->vram_size; |
6296 | serge | 721 | } |
4569 | Serge | 722 | |
6296 | serge | 723 | vmw_print_capabilities(dev_priv->capabilities); |
724 | |||
4569 | Serge | 725 | ret = vmw_dma_masks(dev_priv); |
6296 | serge | 726 | if (unlikely(ret != 0)) |
4569 | Serge | 727 | goto out_err0; |
728 | |||
729 | if (dev_priv->capabilities & SVGA_CAP_GMR2) { |
||
4075 | Serge | 730 | DRM_INFO("Max GMR ids is %u\n", |
731 | (unsigned)dev_priv->max_gmr_ids); |
||
732 | DRM_INFO("Max number of GMR pages is %u\n", |
||
733 | (unsigned)dev_priv->max_gmr_pages); |
||
734 | DRM_INFO("Max dedicated hypervisor surface memory is %u kiB\n", |
||
735 | (unsigned)dev_priv->memory_size / 1024); |
||
736 | } |
||
4569 | Serge | 737 | DRM_INFO("Maximum display memory size is %u kiB\n", |
738 | dev_priv->prim_bb_mem / 1024); |
||
4075 | Serge | 739 | DRM_INFO("VRAM at 0x%08x size is %u kiB\n", |
740 | dev_priv->vram_start, dev_priv->vram_size / 1024); |
||
741 | DRM_INFO("MMIO at 0x%08x size is %u kiB\n", |
||
742 | dev_priv->mmio_start, dev_priv->mmio_size / 1024); |
||
743 | |||
744 | ret = vmw_ttm_global_init(dev_priv); |
||
745 | if (unlikely(ret != 0)) |
||
746 | goto out_err0; |
||
747 | |||
748 | |||
4569 | Serge | 749 | vmw_master_init(&dev_priv->fbdev_master); |
750 | dev_priv->active_master = &dev_priv->fbdev_master; |
||
4075 | Serge | 751 | |
752 | dev_priv->mmio_virt = ioremap_wc(dev_priv->mmio_start, |
||
753 | dev_priv->mmio_size); |
||
754 | |||
755 | if (unlikely(dev_priv->mmio_virt == NULL)) { |
||
756 | ret = -ENOMEM; |
||
757 | DRM_ERROR("Failed mapping MMIO.\n"); |
||
758 | goto out_err3; |
||
759 | } |
||
760 | |||
761 | /* Need mmio memory to check for fifo pitchlock cap. */ |
||
762 | if (!(dev_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) && |
||
763 | !(dev_priv->capabilities & SVGA_CAP_PITCHLOCK) && |
||
764 | !vmw_fifo_have_pitchlock(dev_priv)) { |
||
765 | ret = -ENOSYS; |
||
766 | DRM_ERROR("Hardware has no pitchlock\n"); |
||
767 | goto out_err4; |
||
768 | } |
||
769 | |||
5078 | serge | 770 | dev_priv->tdev = ttm_object_device_init |
771 | (dev_priv->mem_global_ref.object, 12, &vmw_prime_dmabuf_ops); |
||
4075 | Serge | 772 | |
5078 | serge | 773 | if (unlikely(dev_priv->tdev == NULL)) { |
774 | DRM_ERROR("Unable to initialize TTM object management.\n"); |
||
775 | ret = -ENOMEM; |
||
776 | goto out_err4; |
||
777 | } |
||
4075 | Serge | 778 | |
779 | dev->dev_private = dev_priv; |
||
780 | |||
781 | #if 0 |
||
6296 | serge | 782 | ret = pci_request_regions(dev->pdev, "vmwgfx probe"); |
783 | dev_priv->stealth = (ret != 0); |
||
784 | if (dev_priv->stealth) { |
||
785 | /** |
||
786 | * Request at least the mmio PCI resource. |
||
787 | */ |
||
4075 | Serge | 788 | |
6296 | serge | 789 | DRM_INFO("It appears like vesafb is loaded. " |
790 | "Ignore above error if any.\n"); |
||
791 | ret = pci_request_region(dev->pdev, 2, "vmwgfx stealth probe"); |
||
792 | if (unlikely(ret != 0)) { |
||
793 | DRM_ERROR("Failed reserving the SVGA MMIO resource.\n"); |
||
794 | goto out_no_device; |
||
795 | } |
||
796 | } |
||
797 | |||
4075 | Serge | 798 | if (dev_priv->capabilities & SVGA_CAP_IRQMASK) { |
5078 | serge | 799 | ret = drm_irq_install(dev, dev->pdev->irq); |
4075 | Serge | 800 | if (ret != 0) { |
801 | DRM_ERROR("Failed installing irq: %d\n", ret); |
||
802 | goto out_no_irq; |
||
803 | } |
||
804 | } |
||
6296 | serge | 805 | #endif |
4075 | Serge | 806 | |
807 | dev_priv->fman = vmw_fence_manager_init(dev_priv); |
||
4111 | Serge | 808 | if (unlikely(dev_priv->fman == NULL)) { |
809 | ret = -ENOMEM; |
||
4075 | Serge | 810 | goto out_no_fman; |
4111 | Serge | 811 | } |
4075 | Serge | 812 | |
6296 | serge | 813 | ret = ttm_bo_device_init(&dev_priv->bdev, |
814 | dev_priv->bo_global_ref.ref.object, |
||
815 | &vmw_bo_driver, |
||
816 | NULL, |
||
817 | VMWGFX_FILE_PAGE_OFFSET, |
||
818 | false); |
||
819 | if (unlikely(ret != 0)) { |
||
820 | DRM_ERROR("Failed initializing TTM buffer object driver.\n"); |
||
821 | goto out_no_bdev; |
||
822 | } |
||
4075 | Serge | 823 | |
6296 | serge | 824 | /* |
825 | * Enable VRAM, but initially don't use it until SVGA is enabled and |
||
826 | * unhidden. |
||
827 | */ |
||
828 | ret = ttm_bo_init_mm(&dev_priv->bdev, TTM_PL_VRAM, |
||
829 | (dev_priv->vram_size >> PAGE_SHIFT)); |
||
830 | if (unlikely(ret != 0)) { |
||
831 | DRM_ERROR("Failed initializing memory manager for VRAM.\n"); |
||
832 | goto out_no_vram; |
||
833 | } |
||
834 | dev_priv->bdev.man[TTM_PL_VRAM].use_type = false; |
||
835 | |||
836 | dev_priv->has_gmr = true; |
||
837 | if (((dev_priv->capabilities & (SVGA_CAP_GMR | SVGA_CAP_GMR2)) == 0) || |
||
838 | refuse_dma || ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_GMR, |
||
839 | VMW_PL_GMR) != 0) { |
||
840 | DRM_INFO("No GMR memory available. " |
||
841 | "Graphics memory resources are very limited.\n"); |
||
842 | dev_priv->has_gmr = false; |
||
843 | } |
||
844 | |||
845 | if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) { |
||
846 | dev_priv->has_mob = true; |
||
847 | if (ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_MOB, |
||
848 | VMW_PL_MOB) != 0) { |
||
849 | DRM_INFO("No MOB memory available. " |
||
850 | "3D will be disabled.\n"); |
||
851 | dev_priv->has_mob = false; |
||
852 | } |
||
853 | } |
||
854 | |||
855 | if (dev_priv->has_mob) { |
||
856 | spin_lock(&dev_priv->cap_lock); |
||
857 | vmw_write(dev_priv, SVGA_REG_DEV_CAP, SVGA3D_DEVCAP_DX); |
||
858 | dev_priv->has_dx = !!vmw_read(dev_priv, SVGA_REG_DEV_CAP); |
||
859 | spin_unlock(&dev_priv->cap_lock); |
||
860 | } |
||
861 | |||
862 | |||
4075 | Serge | 863 | ret = vmw_kms_init(dev_priv); |
864 | if (unlikely(ret != 0)) |
||
865 | goto out_no_kms; |
||
6296 | serge | 866 | vmw_overlay_init(dev_priv); |
4075 | Serge | 867 | |
6296 | serge | 868 | ret = vmw_request_device(dev_priv); |
869 | if (ret) |
||
870 | goto out_no_fifo; |
||
871 | |||
872 | DRM_INFO("DX: %s\n", dev_priv->has_dx ? "yes." : "no."); |
||
873 | |||
874 | system_wq = alloc_ordered_workqueue("vmwgfx", 0); |
||
875 | main_device = dev; |
||
876 | |||
4080 | Serge | 877 | if (dev_priv->enable_fb) { |
6296 | serge | 878 | vmw_fifo_resource_inc(dev_priv); |
879 | vmw_svga_enable(dev_priv); |
||
880 | vmw_fb_init(dev_priv); |
||
4080 | Serge | 881 | } |
6296 | serge | 882 | LINE(); |
4075 | Serge | 883 | |
884 | return 0; |
||
885 | |||
886 | out_no_fifo: |
||
6296 | serge | 887 | vmw_overlay_close(dev_priv); |
888 | vmw_kms_close(dev_priv); |
||
4075 | Serge | 889 | out_no_kms: |
6296 | serge | 890 | // if (dev_priv->has_mob) |
891 | // (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_MOB); |
||
892 | // if (dev_priv->has_gmr) |
||
893 | // (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR); |
||
894 | // (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM); |
||
895 | out_no_vram: |
||
896 | // (void)ttm_bo_device_release(&dev_priv->bdev); |
||
897 | out_no_bdev: |
||
898 | // vmw_fence_manager_takedown(dev_priv->fman); |
||
4075 | Serge | 899 | out_no_fman: |
6296 | serge | 900 | // if (dev_priv->capabilities & SVGA_CAP_IRQMASK) |
901 | // drm_irq_uninstall(dev_priv->dev); |
||
4075 | Serge | 902 | out_no_irq: |
6296 | serge | 903 | // if (dev_priv->stealth) |
904 | // pci_release_region(dev->pdev, 2); |
||
905 | // else |
||
906 | // pci_release_regions(dev->pdev); |
||
4075 | Serge | 907 | out_no_device: |
6296 | serge | 908 | // ttm_object_device_release(&dev_priv->tdev); |
4075 | Serge | 909 | out_err4: |
6296 | serge | 910 | // memunmap(dev_priv->mmio_virt); |
4075 | Serge | 911 | out_err3: |
6296 | serge | 912 | // vmw_ttm_global_release(dev_priv); |
4075 | Serge | 913 | out_err0: |
6296 | serge | 914 | // for (i = vmw_res_context; i < vmw_res_max; ++i) |
915 | // idr_destroy(&dev_priv->res_idr[i]); |
||
4075 | Serge | 916 | |
6296 | serge | 917 | // if (dev_priv->ctx.staged_bindings) |
918 | // vmw_binding_state_free(dev_priv->ctx.staged_bindings); |
||
4075 | Serge | 919 | kfree(dev_priv); |
920 | return ret; |
||
921 | } |
||
922 | |||
923 | #if 0 |
||
924 | static int vmw_driver_unload(struct drm_device *dev) |
||
925 | { |
||
926 | struct vmw_private *dev_priv = vmw_priv(dev); |
||
927 | enum vmw_res_type i; |
||
928 | |||
929 | unregister_pm_notifier(&dev_priv->pm_nb); |
||
930 | |||
931 | if (dev_priv->ctx.res_ht_initialized) |
||
932 | drm_ht_remove(&dev_priv->ctx.res_ht); |
||
933 | vfree(dev_priv->ctx.cmd_bounce); |
||
934 | if (dev_priv->enable_fb) { |
||
6296 | serge | 935 | vmw_fb_off(dev_priv); |
4075 | Serge | 936 | vmw_fb_close(dev_priv); |
6296 | serge | 937 | vmw_fifo_resource_dec(dev_priv); |
938 | vmw_svga_disable(dev_priv); |
||
4075 | Serge | 939 | } |
6296 | serge | 940 | |
4075 | Serge | 941 | vmw_kms_close(dev_priv); |
942 | vmw_overlay_close(dev_priv); |
||
6296 | serge | 943 | |
944 | if (dev_priv->has_gmr) |
||
945 | (void)ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR); |
||
946 | (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM); |
||
947 | |||
948 | vmw_release_device_early(dev_priv); |
||
949 | if (dev_priv->has_mob) |
||
950 | (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_MOB); |
||
951 | (void) ttm_bo_device_release(&dev_priv->bdev); |
||
952 | vmw_release_device_late(dev_priv); |
||
4075 | Serge | 953 | vmw_fence_manager_takedown(dev_priv->fman); |
954 | if (dev_priv->capabilities & SVGA_CAP_IRQMASK) |
||
955 | drm_irq_uninstall(dev_priv->dev); |
||
956 | if (dev_priv->stealth) |
||
957 | pci_release_region(dev->pdev, 2); |
||
958 | else |
||
959 | pci_release_regions(dev->pdev); |
||
960 | |||
961 | ttm_object_device_release(&dev_priv->tdev); |
||
6296 | serge | 962 | memunmap(dev_priv->mmio_virt); |
963 | if (dev_priv->ctx.staged_bindings) |
||
964 | vmw_binding_state_free(dev_priv->ctx.staged_bindings); |
||
4075 | Serge | 965 | vmw_ttm_global_release(dev_priv); |
966 | |||
967 | for (i = vmw_res_context; i < vmw_res_max; ++i) |
||
968 | idr_destroy(&dev_priv->res_idr[i]); |
||
969 | |||
970 | kfree(dev_priv); |
||
971 | |||
972 | return 0; |
||
973 | } |
||
974 | |||
975 | static void vmw_preclose(struct drm_device *dev, |
||
976 | struct drm_file *file_priv) |
||
977 | { |
||
978 | struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv); |
||
979 | struct vmw_private *dev_priv = vmw_priv(dev); |
||
980 | |||
981 | vmw_event_fence_fpriv_gone(dev_priv->fman, &vmw_fp->fence_events); |
||
982 | } |
||
983 | |||
984 | static void vmw_postclose(struct drm_device *dev, |
||
985 | struct drm_file *file_priv) |
||
986 | { |
||
987 | struct vmw_fpriv *vmw_fp; |
||
988 | |||
989 | vmw_fp = vmw_fpriv(file_priv); |
||
4569 | Serge | 990 | |
991 | if (vmw_fp->locked_master) { |
||
992 | struct vmw_master *vmaster = |
||
993 | vmw_master(vmw_fp->locked_master); |
||
994 | |||
995 | ttm_vt_unlock(&vmaster->lock); |
||
996 | drm_master_put(&vmw_fp->locked_master); |
||
997 | } |
||
998 | |||
4075 | Serge | 999 | ttm_object_file_release(&vmw_fp->tfile); |
1000 | kfree(vmw_fp); |
||
1001 | } |
||
1002 | #endif |
||
1003 | |||
1004 | static int vmw_driver_open(struct drm_device *dev, struct drm_file *file_priv) |
||
1005 | { |
||
1006 | struct vmw_private *dev_priv = vmw_priv(dev); |
||
1007 | struct vmw_fpriv *vmw_fp; |
||
1008 | int ret = -ENOMEM; |
||
1009 | |||
1010 | vmw_fp = kzalloc(sizeof(*vmw_fp), GFP_KERNEL); |
||
1011 | if (unlikely(vmw_fp == NULL)) |
||
1012 | return ret; |
||
1013 | |||
1014 | INIT_LIST_HEAD(&vmw_fp->fence_events); |
||
1015 | // vmw_fp->tfile = ttm_object_file_init(dev_priv->tdev, 10); |
||
1016 | // if (unlikely(vmw_fp->tfile == NULL)) |
||
1017 | // goto out_no_tfile; |
||
1018 | |||
1019 | file_priv->driver_priv = vmw_fp; |
||
1020 | |||
1021 | return 0; |
||
1022 | |||
1023 | out_no_tfile: |
||
1024 | kfree(vmw_fp); |
||
1025 | return ret; |
||
1026 | } |
||
1027 | |||
1028 | #if 0 |
||
6296 | serge | 1029 | static struct vmw_master *vmw_master_check(struct drm_device *dev, |
1030 | struct drm_file *file_priv, |
||
1031 | unsigned int flags) |
||
4075 | Serge | 1032 | { |
6296 | serge | 1033 | int ret; |
1034 | struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv); |
||
1035 | struct vmw_master *vmaster; |
||
1036 | |||
1037 | if (file_priv->minor->type != DRM_MINOR_LEGACY || |
||
1038 | !(flags & DRM_AUTH)) |
||
1039 | return NULL; |
||
1040 | |||
1041 | ret = mutex_lock_interruptible(&dev->master_mutex); |
||
1042 | if (unlikely(ret != 0)) |
||
1043 | return ERR_PTR(-ERESTARTSYS); |
||
1044 | |||
1045 | if (file_priv->is_master) { |
||
1046 | mutex_unlock(&dev->master_mutex); |
||
1047 | return NULL; |
||
1048 | } |
||
1049 | |||
1050 | /* |
||
1051 | * Check if we were previously master, but now dropped. In that |
||
1052 | * case, allow at least render node functionality. |
||
1053 | */ |
||
1054 | if (vmw_fp->locked_master) { |
||
1055 | mutex_unlock(&dev->master_mutex); |
||
1056 | |||
1057 | if (flags & DRM_RENDER_ALLOW) |
||
1058 | return NULL; |
||
1059 | |||
1060 | DRM_ERROR("Dropped master trying to access ioctl that " |
||
1061 | "requires authentication.\n"); |
||
1062 | return ERR_PTR(-EACCES); |
||
1063 | } |
||
1064 | mutex_unlock(&dev->master_mutex); |
||
1065 | |||
1066 | /* |
||
1067 | * Take the TTM lock. Possibly sleep waiting for the authenticating |
||
1068 | * master to become master again, or for a SIGTERM if the |
||
1069 | * authenticating master exits. |
||
1070 | */ |
||
1071 | vmaster = vmw_master(file_priv->master); |
||
1072 | ret = ttm_read_lock(&vmaster->lock, true); |
||
1073 | if (unlikely(ret != 0)) |
||
1074 | vmaster = ERR_PTR(ret); |
||
1075 | |||
1076 | return vmaster; |
||
1077 | } |
||
1078 | |||
1079 | static long vmw_generic_ioctl(struct file *filp, unsigned int cmd, |
||
1080 | unsigned long arg, |
||
1081 | long (*ioctl_func)(struct file *, unsigned int, |
||
1082 | unsigned long)) |
||
1083 | { |
||
4075 | Serge | 1084 | struct drm_file *file_priv = filp->private_data; |
1085 | struct drm_device *dev = file_priv->minor->dev; |
||
1086 | unsigned int nr = DRM_IOCTL_NR(cmd); |
||
6296 | serge | 1087 | struct vmw_master *vmaster; |
1088 | unsigned int flags; |
||
1089 | long ret; |
||
4075 | Serge | 1090 | |
1091 | /* |
||
1092 | * Do extra checking on driver private ioctls. |
||
1093 | */ |
||
1094 | |||
1095 | if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END) |
||
1096 | && (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls)) { |
||
4111 | Serge | 1097 | const struct drm_ioctl_desc *ioctl = |
4075 | Serge | 1098 | &vmw_ioctls[nr - DRM_COMMAND_BASE]; |
1099 | |||
6296 | serge | 1100 | if (nr == DRM_COMMAND_BASE + DRM_VMW_EXECBUF) { |
1101 | ret = (long) drm_ioctl_permit(ioctl->flags, file_priv); |
||
1102 | if (unlikely(ret != 0)) |
||
1103 | return ret; |
||
1104 | |||
1105 | if (unlikely((cmd & (IOC_IN | IOC_OUT)) != IOC_IN)) |
||
1106 | goto out_io_encoding; |
||
1107 | |||
1108 | return (long) vmw_execbuf_ioctl(dev, arg, file_priv, |
||
1109 | _IOC_SIZE(cmd)); |
||
1110 | } |
||
1111 | |||
1112 | if (unlikely(ioctl->cmd != cmd)) |
||
1113 | goto out_io_encoding; |
||
1114 | |||
1115 | flags = ioctl->flags; |
||
1116 | } else if (!drm_ioctl_flags(nr, &flags)) |
||
1117 | return -EINVAL; |
||
1118 | |||
1119 | vmaster = vmw_master_check(dev, file_priv, flags); |
||
1120 | if (IS_ERR(vmaster)) { |
||
1121 | ret = PTR_ERR(vmaster); |
||
1122 | |||
1123 | if (ret != -ERESTARTSYS) |
||
1124 | DRM_INFO("IOCTL ERROR Command %d, Error %ld.\n", |
||
1125 | nr, ret); |
||
1126 | return ret; |
||
1127 | } |
||
1128 | |||
1129 | ret = ioctl_func(filp, cmd, arg); |
||
1130 | if (vmaster) |
||
1131 | ttm_read_unlock(&vmaster->lock); |
||
1132 | |||
1133 | return ret; |
||
1134 | |||
1135 | out_io_encoding: |
||
4075 | Serge | 1136 | DRM_ERROR("Invalid command format, ioctl %d\n", |
1137 | nr - DRM_COMMAND_BASE); |
||
6296 | serge | 1138 | |
4075 | Serge | 1139 | return -EINVAL; |
6296 | serge | 1140 | } |
4075 | Serge | 1141 | |
6296 | serge | 1142 | static long vmw_unlocked_ioctl(struct file *filp, unsigned int cmd, |
1143 | unsigned long arg) |
||
1144 | { |
||
1145 | return vmw_generic_ioctl(filp, cmd, arg, &drm_ioctl); |
||
4075 | Serge | 1146 | } |
1147 | |||
6296 | serge | 1148 | #ifdef CONFIG_COMPAT |
1149 | static long vmw_compat_ioctl(struct file *filp, unsigned int cmd, |
||
1150 | unsigned long arg) |
||
1151 | { |
||
1152 | return vmw_generic_ioctl(filp, cmd, arg, &drm_compat_ioctl); |
||
1153 | } |
||
1154 | #endif |
||
1155 | |||
4075 | Serge | 1156 | static void vmw_lastclose(struct drm_device *dev) |
1157 | { |
||
1158 | } |
||
4569 | Serge | 1159 | #endif |
4075 | Serge | 1160 | |
1161 | static void vmw_master_init(struct vmw_master *vmaster) |
||
1162 | { |
||
4570 | Serge | 1163 | ttm_lock_init(&vmaster->lock); |
4075 | Serge | 1164 | } |
1165 | |||
1166 | static int vmw_master_create(struct drm_device *dev, |
||
1167 | struct drm_master *master) |
||
1168 | { |
||
1169 | struct vmw_master *vmaster; |
||
1170 | |||
1171 | vmaster = kzalloc(sizeof(*vmaster), GFP_KERNEL); |
||
1172 | if (unlikely(vmaster == NULL)) |
||
1173 | return -ENOMEM; |
||
1174 | |||
1175 | vmw_master_init(vmaster); |
||
4569 | Serge | 1176 | // ttm_lock_set_kill(&vmaster->lock, true, SIGTERM); |
4075 | Serge | 1177 | master->driver_priv = vmaster; |
1178 | |||
1179 | return 0; |
||
1180 | } |
||
1181 | |||
1182 | static void vmw_master_destroy(struct drm_device *dev, |
||
1183 | struct drm_master *master) |
||
1184 | { |
||
1185 | struct vmw_master *vmaster = vmw_master(master); |
||
1186 | |||
1187 | master->driver_priv = NULL; |
||
1188 | kfree(vmaster); |
||
1189 | } |
||
1190 | |||
4569 | Serge | 1191 | #if 0 |
4075 | Serge | 1192 | static int vmw_master_set(struct drm_device *dev, |
1193 | struct drm_file *file_priv, |
||
1194 | bool from_open) |
||
1195 | { |
||
1196 | struct vmw_private *dev_priv = vmw_priv(dev); |
||
1197 | struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv); |
||
1198 | struct vmw_master *active = dev_priv->active_master; |
||
1199 | struct vmw_master *vmaster = vmw_master(file_priv->master); |
||
1200 | int ret = 0; |
||
1201 | |||
1202 | if (active) { |
||
1203 | BUG_ON(active != &dev_priv->fbdev_master); |
||
1204 | ret = ttm_vt_lock(&active->lock, false, vmw_fp->tfile); |
||
1205 | if (unlikely(ret != 0)) |
||
6296 | serge | 1206 | return ret; |
4075 | Serge | 1207 | |
1208 | ttm_lock_set_kill(&active->lock, true, SIGTERM); |
||
1209 | dev_priv->active_master = NULL; |
||
1210 | } |
||
1211 | |||
1212 | ttm_lock_set_kill(&vmaster->lock, false, SIGTERM); |
||
1213 | if (!from_open) { |
||
1214 | ttm_vt_unlock(&vmaster->lock); |
||
1215 | BUG_ON(vmw_fp->locked_master != file_priv->master); |
||
1216 | drm_master_put(&vmw_fp->locked_master); |
||
1217 | } |
||
1218 | |||
1219 | dev_priv->active_master = vmaster; |
||
1220 | |||
1221 | return 0; |
||
1222 | } |
||
1223 | |||
1224 | static void vmw_master_drop(struct drm_device *dev, |
||
1225 | struct drm_file *file_priv, |
||
1226 | bool from_release) |
||
1227 | { |
||
1228 | struct vmw_private *dev_priv = vmw_priv(dev); |
||
1229 | struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv); |
||
1230 | struct vmw_master *vmaster = vmw_master(file_priv->master); |
||
1231 | int ret; |
||
1232 | |||
1233 | /** |
||
1234 | * Make sure the master doesn't disappear while we have |
||
1235 | * it locked. |
||
1236 | */ |
||
1237 | |||
1238 | vmw_fp->locked_master = drm_master_get(file_priv->master); |
||
1239 | ret = ttm_vt_lock(&vmaster->lock, false, vmw_fp->tfile); |
||
6296 | serge | 1240 | vmw_kms_legacy_hotspot_clear(dev_priv); |
4075 | Serge | 1241 | if (unlikely((ret != 0))) { |
1242 | DRM_ERROR("Unable to lock TTM at VT switch.\n"); |
||
1243 | drm_master_put(&vmw_fp->locked_master); |
||
1244 | } |
||
1245 | |||
1246 | |||
6296 | serge | 1247 | if (!dev_priv->enable_fb) |
1248 | vmw_svga_disable(dev_priv); |
||
4075 | Serge | 1249 | |
1250 | dev_priv->active_master = &dev_priv->fbdev_master; |
||
1251 | ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM); |
||
1252 | ttm_vt_unlock(&dev_priv->fbdev_master.lock); |
||
1253 | |||
1254 | if (dev_priv->enable_fb) |
||
1255 | vmw_fb_on(dev_priv); |
||
1256 | } |
||
6296 | serge | 1257 | #endif |
1258 | /** |
||
1259 | * __vmw_svga_enable - Enable SVGA mode, FIFO and use of VRAM. |
||
1260 | * |
||
1261 | * @dev_priv: Pointer to device private struct. |
||
1262 | * Needs the reservation sem to be held in non-exclusive mode. |
||
1263 | */ |
||
1264 | static void __vmw_svga_enable(struct vmw_private *dev_priv) |
||
1265 | { |
||
1266 | spin_lock(&dev_priv->svga_lock); |
||
1267 | if (!dev_priv->bdev.man[TTM_PL_VRAM].use_type) { |
||
1268 | vmw_write(dev_priv, SVGA_REG_ENABLE, SVGA_REG_ENABLE); |
||
1269 | dev_priv->bdev.man[TTM_PL_VRAM].use_type = true; |
||
1270 | } |
||
1271 | spin_unlock(&dev_priv->svga_lock); |
||
1272 | } |
||
4075 | Serge | 1273 | |
6296 | serge | 1274 | /** |
1275 | * vmw_svga_enable - Enable SVGA mode, FIFO and use of VRAM. |
||
1276 | * |
||
1277 | * @dev_priv: Pointer to device private struct. |
||
1278 | */ |
||
1279 | void vmw_svga_enable(struct vmw_private *dev_priv) |
||
1280 | { |
||
1281 | ttm_read_lock(&dev_priv->reservation_sem, false); |
||
1282 | __vmw_svga_enable(dev_priv); |
||
1283 | ttm_read_unlock(&dev_priv->reservation_sem); |
||
1284 | } |
||
4080 | Serge | 1285 | |
6296 | serge | 1286 | #if 0 |
4080 | Serge | 1287 | static void vmw_remove(struct pci_dev *pdev) |
1288 | { |
||
1289 | struct drm_device *dev = pci_get_drvdata(pdev); |
||
1290 | |||
1291 | drm_put_dev(dev); |
||
1292 | } |
||
1293 | |||
1294 | static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val, |
||
1295 | void *ptr) |
||
1296 | { |
||
1297 | struct vmw_private *dev_priv = |
||
1298 | container_of(nb, struct vmw_private, pm_nb); |
||
1299 | |||
1300 | switch (val) { |
||
1301 | case PM_HIBERNATION_PREPARE: |
||
6296 | serge | 1302 | if (dev_priv->enable_fb) |
1303 | vmw_fb_off(dev_priv); |
||
5078 | serge | 1304 | ttm_suspend_lock(&dev_priv->reservation_sem); |
4080 | Serge | 1305 | |
6296 | serge | 1306 | /* |
4080 | Serge | 1307 | * This empties VRAM and unbinds all GMR bindings. |
1308 | * Buffer contents is moved to swappable memory. |
||
1309 | */ |
||
1310 | vmw_execbuf_release_pinned_bo(dev_priv); |
||
1311 | vmw_resource_evict_all(dev_priv); |
||
6296 | serge | 1312 | vmw_release_device_early(dev_priv); |
4080 | Serge | 1313 | ttm_bo_swapout_all(&dev_priv->bdev); |
6296 | serge | 1314 | vmw_fence_fifo_down(dev_priv->fman); |
4080 | Serge | 1315 | break; |
1316 | case PM_POST_HIBERNATION: |
||
1317 | case PM_POST_RESTORE: |
||
6296 | serge | 1318 | vmw_fence_fifo_up(dev_priv->fman); |
5078 | serge | 1319 | ttm_suspend_unlock(&dev_priv->reservation_sem); |
6296 | serge | 1320 | if (dev_priv->enable_fb) |
1321 | vmw_fb_on(dev_priv); |
||
4080 | Serge | 1322 | break; |
1323 | case PM_RESTORE_PREPARE: |
||
1324 | break; |
||
1325 | default: |
||
1326 | break; |
||
1327 | } |
||
1328 | return 0; |
||
1329 | } |
||
1330 | |||
1331 | static int vmw_pci_suspend(struct pci_dev *pdev, pm_message_t state) |
||
1332 | { |
||
1333 | struct drm_device *dev = pci_get_drvdata(pdev); |
||
1334 | struct vmw_private *dev_priv = vmw_priv(dev); |
||
1335 | |||
6296 | serge | 1336 | if (dev_priv->refuse_hibernation) |
4080 | Serge | 1337 | return -EBUSY; |
1338 | |||
1339 | pci_save_state(pdev); |
||
1340 | pci_disable_device(pdev); |
||
1341 | pci_set_power_state(pdev, PCI_D3hot); |
||
1342 | return 0; |
||
1343 | } |
||
1344 | |||
1345 | static int vmw_pci_resume(struct pci_dev *pdev) |
||
1346 | { |
||
1347 | pci_set_power_state(pdev, PCI_D0); |
||
1348 | pci_restore_state(pdev); |
||
1349 | return pci_enable_device(pdev); |
||
1350 | } |
||
1351 | |||
1352 | static int vmw_pm_suspend(struct device *kdev) |
||
1353 | { |
||
1354 | struct pci_dev *pdev = to_pci_dev(kdev); |
||
1355 | struct pm_message dummy; |
||
1356 | |||
1357 | dummy.event = 0; |
||
1358 | |||
1359 | return vmw_pci_suspend(pdev, dummy); |
||
1360 | } |
||
1361 | |||
1362 | static int vmw_pm_resume(struct device *kdev) |
||
1363 | { |
||
1364 | struct pci_dev *pdev = to_pci_dev(kdev); |
||
1365 | |||
1366 | return vmw_pci_resume(pdev); |
||
1367 | } |
||
1368 | |||
6296 | serge | 1369 | static int vmw_pm_freeze(struct device *kdev) |
4080 | Serge | 1370 | { |
1371 | struct pci_dev *pdev = to_pci_dev(kdev); |
||
1372 | struct drm_device *dev = pci_get_drvdata(pdev); |
||
1373 | struct vmw_private *dev_priv = vmw_priv(dev); |
||
1374 | |||
1375 | dev_priv->suspended = true; |
||
1376 | if (dev_priv->enable_fb) |
||
6296 | serge | 1377 | vmw_fifo_resource_dec(dev_priv); |
4080 | Serge | 1378 | |
6296 | serge | 1379 | if (atomic_read(&dev_priv->num_fifo_resources) != 0) { |
1380 | DRM_ERROR("Can't hibernate while 3D resources are active.\n"); |
||
4080 | Serge | 1381 | if (dev_priv->enable_fb) |
6296 | serge | 1382 | vmw_fifo_resource_inc(dev_priv); |
1383 | WARN_ON(vmw_request_device_late(dev_priv)); |
||
4080 | Serge | 1384 | dev_priv->suspended = false; |
1385 | return -EBUSY; |
||
1386 | } |
||
1387 | |||
6296 | serge | 1388 | if (dev_priv->enable_fb) |
1389 | __vmw_svga_disable(dev_priv); |
||
1390 | |||
1391 | vmw_release_device_late(dev_priv); |
||
1392 | |||
4080 | Serge | 1393 | return 0; |
1394 | } |
||
1395 | |||
4075 | Serge | 1396 | #endif |
1397 | |||
1398 | static struct drm_driver driver = { |
||
1399 | .driver_features = DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | |
||
5078 | serge | 1400 | DRIVER_MODESET | DRIVER_RENDER, |
4111 | Serge | 1401 | .load = vmw_driver_load, |
4570 | Serge | 1402 | // .unload = vmw_driver_unload, |
1403 | // .lastclose = vmw_lastclose, |
||
4075 | Serge | 1404 | .irq_preinstall = vmw_irq_preinstall, |
1405 | .irq_postinstall = vmw_irq_postinstall, |
||
1406 | // .irq_uninstall = vmw_irq_uninstall, |
||
1407 | .irq_handler = vmw_irq_handler, |
||
6296 | serge | 1408 | .get_vblank_counter = vmw_get_vblank_counter, |
1409 | .enable_vblank = vmw_enable_vblank, |
||
1410 | .disable_vblank = vmw_disable_vblank, |
||
4075 | Serge | 1411 | // .ioctls = vmw_ioctls, |
1412 | // .num_ioctls = DRM_ARRAY_SIZE(vmw_ioctls), |
||
1413 | .open = vmw_driver_open, |
||
1414 | // .preclose = vmw_preclose, |
||
1415 | // .postclose = vmw_postclose, |
||
1416 | |||
1417 | // .dumb_create = vmw_dumb_create, |
||
1418 | // .dumb_map_offset = vmw_dumb_map_offset, |
||
1419 | // .dumb_destroy = vmw_dumb_destroy, |
||
1420 | |||
4570 | Serge | 1421 | |
4075 | Serge | 1422 | }; |
1423 | |||
4111 | Serge | 1424 | #if 0 |
1425 | static struct pci_driver vmw_pci_driver = { |
||
1426 | .name = VMWGFX_DRIVER_NAME, |
||
1427 | .id_table = vmw_pci_id_list, |
||
1428 | .probe = vmw_probe, |
||
1429 | .remove = vmw_remove, |
||
1430 | .driver = { |
||
1431 | .pm = &vmw_pm_ops |
||
1432 | } |
||
1433 | }; |
||
4080 | Serge | 1434 | |
4111 | Serge | 1435 | static int vmw_probe(struct pci_dev *pdev, const struct pci_device_id *ent) |
1436 | { |
||
1437 | return drm_get_pci_dev(pdev, ent, &driver); |
||
1438 | } |
||
1439 | #endif |
||
1440 | |||
4080 | Serge | 1441 | int vmw_init(void) |
1442 | { |
||
1443 | static pci_dev_t device; |
||
1444 | const struct pci_device_id *ent; |
||
1445 | int err; |
||
1446 | |||
1447 | |||
1448 | ent = find_pci_device(&device, vmw_pci_id_list); |
||
1449 | if( unlikely(ent == NULL) ) |
||
1450 | { |
||
1451 | dbgprintf("device not found\n"); |
||
1452 | return -ENODEV; |
||
1453 | }; |
||
1454 | |||
4111 | Serge | 1455 | drm_core_init(); |
1456 | |||
4080 | Serge | 1457 | DRM_INFO("device %x:%x\n", device.pci_dev.vendor, |
1458 | device.pci_dev.device); |
||
1459 | |||
4111 | Serge | 1460 | err = drm_get_pci_dev(&device.pci_dev, ent, &driver); |
4080 | Serge | 1461 | |
1462 | return err; |
||
1463 | } |
||
1464 | |||
1465 | |||
1466 | MODULE_AUTHOR("VMware Inc. and others"); |
||
1467 | MODULE_DESCRIPTION("Standalone drm driver for the VMware SVGA device"); |
||
1468 | MODULE_LICENSE("GPL and additional rights"); |
||
4569 | Serge | 1469 | |
1470 | |||
1471 | void *kmemdup(const void *src, size_t len, gfp_t gfp) |
||
1472 | { |
||
1473 | void *p; |
||
1474 | |||
1475 | p = kmalloc(len, gfp); |
||
1476 | if (p) |
||
1477 | memcpy(p, src, len); |
||
1478 | return p; |
||
1479 | }>>>>> |
||
1480 |