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4075 | Serge | 1 | /************************************************************************** |
2 | * |
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3 | * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA |
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4 | * All Rights Reserved. |
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5 | * |
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6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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7 | * copy of this software and associated documentation files (the |
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8 | * "Software"), to deal in the Software without restriction, including |
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9 | * without limitation the rights to use, copy, modify, merge, publish, |
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10 | * distribute, sub license, and/or sell copies of the Software, and to |
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11 | * permit persons to whom the Software is furnished to do so, subject to |
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12 | * the following conditions: |
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13 | * |
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14 | * The above copyright notice and this permission notice (including the |
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15 | * next paragraph) shall be included in all copies or substantial portions |
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16 | * of the Software. |
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17 | * |
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18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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20 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL |
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21 | * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, |
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22 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR |
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23 | * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE |
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24 | * USE OR OTHER DEALINGS IN THE SOFTWARE. |
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25 | * |
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26 | **************************************************************************/ |
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27 | #include |
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28 | |||
29 | #include |
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30 | #include "vmwgfx_drv.h" |
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31 | #include |
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32 | #include |
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33 | #include |
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34 | //#include |
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4569 | Serge | 35 | #include |
4075 | Serge | 36 | |
37 | #define VMWGFX_DRIVER_NAME "vmwgfx" |
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38 | #define VMWGFX_DRIVER_DESC "Linux drm driver for VMware graphics devices" |
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39 | #define VMWGFX_CHIP_SVGAII 0 |
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40 | #define VMW_FB_RESERVATION 0 |
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41 | |||
42 | #define VMW_MIN_INITIAL_WIDTH 800 |
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43 | #define VMW_MIN_INITIAL_HEIGHT 600 |
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44 | |||
45 | #if 0 |
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46 | /** |
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47 | * Fully encoded drm commands. Might move to vmw_drm.h |
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48 | */ |
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49 | |||
50 | #define DRM_IOCTL_VMW_GET_PARAM \ |
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51 | DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GET_PARAM, \ |
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52 | struct drm_vmw_getparam_arg) |
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53 | #define DRM_IOCTL_VMW_ALLOC_DMABUF \ |
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54 | DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_ALLOC_DMABUF, \ |
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55 | union drm_vmw_alloc_dmabuf_arg) |
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56 | #define DRM_IOCTL_VMW_UNREF_DMABUF \ |
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57 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_DMABUF, \ |
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58 | struct drm_vmw_unref_dmabuf_arg) |
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59 | #define DRM_IOCTL_VMW_CURSOR_BYPASS \ |
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60 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CURSOR_BYPASS, \ |
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61 | struct drm_vmw_cursor_bypass_arg) |
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62 | |||
63 | #define DRM_IOCTL_VMW_CONTROL_STREAM \ |
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64 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CONTROL_STREAM, \ |
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65 | struct drm_vmw_control_stream_arg) |
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66 | #define DRM_IOCTL_VMW_CLAIM_STREAM \ |
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67 | DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CLAIM_STREAM, \ |
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68 | struct drm_vmw_stream_arg) |
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69 | #define DRM_IOCTL_VMW_UNREF_STREAM \ |
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70 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_STREAM, \ |
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71 | struct drm_vmw_stream_arg) |
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72 | |||
73 | #define DRM_IOCTL_VMW_CREATE_CONTEXT \ |
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74 | DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CREATE_CONTEXT, \ |
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75 | struct drm_vmw_context_arg) |
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76 | #define DRM_IOCTL_VMW_UNREF_CONTEXT \ |
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77 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_CONTEXT, \ |
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78 | struct drm_vmw_context_arg) |
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79 | #define DRM_IOCTL_VMW_CREATE_SURFACE \ |
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80 | DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SURFACE, \ |
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81 | union drm_vmw_surface_create_arg) |
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82 | #define DRM_IOCTL_VMW_UNREF_SURFACE \ |
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83 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SURFACE, \ |
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84 | struct drm_vmw_surface_arg) |
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85 | #define DRM_IOCTL_VMW_REF_SURFACE \ |
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86 | DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_REF_SURFACE, \ |
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87 | union drm_vmw_surface_reference_arg) |
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88 | #define DRM_IOCTL_VMW_EXECBUF \ |
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89 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_EXECBUF, \ |
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90 | struct drm_vmw_execbuf_arg) |
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91 | #define DRM_IOCTL_VMW_GET_3D_CAP \ |
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92 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_GET_3D_CAP, \ |
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93 | struct drm_vmw_get_3d_cap_arg) |
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94 | #define DRM_IOCTL_VMW_FENCE_WAIT \ |
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95 | DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_WAIT, \ |
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96 | struct drm_vmw_fence_wait_arg) |
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97 | #define DRM_IOCTL_VMW_FENCE_SIGNALED \ |
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98 | DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_SIGNALED, \ |
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99 | struct drm_vmw_fence_signaled_arg) |
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100 | #define DRM_IOCTL_VMW_FENCE_UNREF \ |
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101 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_UNREF, \ |
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102 | struct drm_vmw_fence_arg) |
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103 | #define DRM_IOCTL_VMW_FENCE_EVENT \ |
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104 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_EVENT, \ |
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105 | struct drm_vmw_fence_event_arg) |
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106 | #define DRM_IOCTL_VMW_PRESENT \ |
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107 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT, \ |
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108 | struct drm_vmw_present_arg) |
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109 | #define DRM_IOCTL_VMW_PRESENT_READBACK \ |
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110 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT_READBACK, \ |
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111 | struct drm_vmw_present_readback_arg) |
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112 | #define DRM_IOCTL_VMW_UPDATE_LAYOUT \ |
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113 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT, \ |
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114 | struct drm_vmw_update_layout_arg) |
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4569 | Serge | 115 | #define DRM_IOCTL_VMW_CREATE_SHADER \ |
116 | DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SHADER, \ |
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117 | struct drm_vmw_shader_create_arg) |
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118 | #define DRM_IOCTL_VMW_UNREF_SHADER \ |
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119 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SHADER, \ |
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120 | struct drm_vmw_shader_arg) |
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121 | #define DRM_IOCTL_VMW_GB_SURFACE_CREATE \ |
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122 | DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_CREATE, \ |
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123 | union drm_vmw_gb_surface_create_arg) |
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124 | #define DRM_IOCTL_VMW_GB_SURFACE_REF \ |
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125 | DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_REF, \ |
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126 | union drm_vmw_gb_surface_reference_arg) |
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127 | #define DRM_IOCTL_VMW_SYNCCPU \ |
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128 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_SYNCCPU, \ |
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129 | struct drm_vmw_synccpu_arg) |
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4075 | Serge | 130 | |
131 | /** |
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132 | * The core DRM version of this macro doesn't account for |
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133 | * DRM_COMMAND_BASE. |
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134 | */ |
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135 | |||
136 | #define VMW_IOCTL_DEF(ioctl, func, flags) \ |
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137 | [DRM_IOCTL_NR(DRM_IOCTL_##ioctl) - DRM_COMMAND_BASE] = {DRM_##ioctl, flags, func, DRM_IOCTL_##ioctl} |
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138 | |||
139 | /** |
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140 | * Ioctl definitions. |
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141 | */ |
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142 | |||
4111 | Serge | 143 | static const struct drm_ioctl_desc vmw_ioctls[] = { |
4075 | Serge | 144 | VMW_IOCTL_DEF(VMW_GET_PARAM, vmw_getparam_ioctl, |
145 | DRM_AUTH | DRM_UNLOCKED), |
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146 | VMW_IOCTL_DEF(VMW_ALLOC_DMABUF, vmw_dmabuf_alloc_ioctl, |
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147 | DRM_AUTH | DRM_UNLOCKED), |
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148 | VMW_IOCTL_DEF(VMW_UNREF_DMABUF, vmw_dmabuf_unref_ioctl, |
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149 | DRM_AUTH | DRM_UNLOCKED), |
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150 | VMW_IOCTL_DEF(VMW_CURSOR_BYPASS, |
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151 | vmw_kms_cursor_bypass_ioctl, |
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152 | DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED), |
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153 | |||
154 | VMW_IOCTL_DEF(VMW_CONTROL_STREAM, vmw_overlay_ioctl, |
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155 | DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED), |
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156 | VMW_IOCTL_DEF(VMW_CLAIM_STREAM, vmw_stream_claim_ioctl, |
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157 | DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED), |
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158 | VMW_IOCTL_DEF(VMW_UNREF_STREAM, vmw_stream_unref_ioctl, |
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159 | DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED), |
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160 | |||
161 | VMW_IOCTL_DEF(VMW_CREATE_CONTEXT, vmw_context_define_ioctl, |
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162 | DRM_AUTH | DRM_UNLOCKED), |
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163 | VMW_IOCTL_DEF(VMW_UNREF_CONTEXT, vmw_context_destroy_ioctl, |
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164 | DRM_AUTH | DRM_UNLOCKED), |
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165 | VMW_IOCTL_DEF(VMW_CREATE_SURFACE, vmw_surface_define_ioctl, |
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166 | DRM_AUTH | DRM_UNLOCKED), |
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167 | VMW_IOCTL_DEF(VMW_UNREF_SURFACE, vmw_surface_destroy_ioctl, |
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168 | DRM_AUTH | DRM_UNLOCKED), |
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169 | VMW_IOCTL_DEF(VMW_REF_SURFACE, vmw_surface_reference_ioctl, |
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170 | DRM_AUTH | DRM_UNLOCKED), |
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171 | VMW_IOCTL_DEF(VMW_EXECBUF, vmw_execbuf_ioctl, |
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172 | DRM_AUTH | DRM_UNLOCKED), |
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173 | VMW_IOCTL_DEF(VMW_FENCE_WAIT, vmw_fence_obj_wait_ioctl, |
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174 | DRM_AUTH | DRM_UNLOCKED), |
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175 | VMW_IOCTL_DEF(VMW_FENCE_SIGNALED, |
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176 | vmw_fence_obj_signaled_ioctl, |
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177 | DRM_AUTH | DRM_UNLOCKED), |
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178 | VMW_IOCTL_DEF(VMW_FENCE_UNREF, vmw_fence_obj_unref_ioctl, |
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179 | DRM_AUTH | DRM_UNLOCKED), |
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180 | VMW_IOCTL_DEF(VMW_FENCE_EVENT, |
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181 | vmw_fence_event_ioctl, |
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182 | DRM_AUTH | DRM_UNLOCKED), |
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183 | VMW_IOCTL_DEF(VMW_GET_3D_CAP, vmw_get_cap_3d_ioctl, |
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184 | DRM_AUTH | DRM_UNLOCKED), |
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185 | |||
186 | /* these allow direct access to the framebuffers mark as master only */ |
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187 | VMW_IOCTL_DEF(VMW_PRESENT, vmw_present_ioctl, |
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188 | DRM_MASTER | DRM_AUTH | DRM_UNLOCKED), |
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189 | VMW_IOCTL_DEF(VMW_PRESENT_READBACK, |
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190 | vmw_present_readback_ioctl, |
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191 | DRM_MASTER | DRM_AUTH | DRM_UNLOCKED), |
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192 | VMW_IOCTL_DEF(VMW_UPDATE_LAYOUT, |
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193 | vmw_kms_update_layout_ioctl, |
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194 | DRM_MASTER | DRM_UNLOCKED), |
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4569 | Serge | 195 | VMW_IOCTL_DEF(VMW_CREATE_SHADER, |
196 | vmw_shader_define_ioctl, |
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197 | DRM_AUTH | DRM_UNLOCKED), |
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198 | VMW_IOCTL_DEF(VMW_UNREF_SHADER, |
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199 | vmw_shader_destroy_ioctl, |
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200 | DRM_AUTH | DRM_UNLOCKED), |
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201 | VMW_IOCTL_DEF(VMW_GB_SURFACE_CREATE, |
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202 | vmw_gb_surface_define_ioctl, |
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203 | DRM_AUTH | DRM_UNLOCKED), |
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204 | VMW_IOCTL_DEF(VMW_GB_SURFACE_REF, |
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205 | vmw_gb_surface_reference_ioctl, |
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206 | DRM_AUTH | DRM_UNLOCKED), |
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207 | VMW_IOCTL_DEF(VMW_SYNCCPU, |
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208 | vmw_user_dmabuf_synccpu_ioctl, |
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209 | DRM_AUTH | DRM_UNLOCKED), |
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4075 | Serge | 210 | }; |
211 | #endif |
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212 | |||
213 | static struct pci_device_id vmw_pci_id_list[] = { |
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214 | {0x15ad, 0x0405, PCI_ANY_ID, PCI_ANY_ID, 0, 0, VMWGFX_CHIP_SVGAII}, |
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215 | {0, 0, 0} |
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216 | }; |
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217 | |||
218 | static int enable_fbdev = 1; |
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4569 | Serge | 219 | static int vmw_force_iommu; |
220 | static int vmw_restrict_iommu; |
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221 | static int vmw_force_coherent; |
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222 | static int vmw_restrict_dma_mask; |
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4075 | Serge | 223 | |
224 | static int vmw_probe(struct pci_dev *, const struct pci_device_id *); |
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225 | static void vmw_master_init(struct vmw_master *); |
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226 | |||
227 | MODULE_PARM_DESC(enable_fbdev, "Enable vmwgfx fbdev"); |
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228 | module_param_named(enable_fbdev, enable_fbdev, int, 0600); |
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4569 | Serge | 229 | MODULE_PARM_DESC(force_dma_api, "Force using the DMA API for TTM pages"); |
230 | module_param_named(force_dma_api, vmw_force_iommu, int, 0600); |
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231 | MODULE_PARM_DESC(restrict_iommu, "Try to limit IOMMU usage for TTM pages"); |
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232 | module_param_named(restrict_iommu, vmw_restrict_iommu, int, 0600); |
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233 | MODULE_PARM_DESC(force_coherent, "Force coherent TTM pages"); |
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234 | module_param_named(force_coherent, vmw_force_coherent, int, 0600); |
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235 | MODULE_PARM_DESC(restrict_dma_mask, "Restrict DMA mask to 44 bits with IOMMU"); |
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236 | module_param_named(restrict_dma_mask, vmw_restrict_dma_mask, int, 0600); |
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4075 | Serge | 237 | |
4569 | Serge | 238 | |
4075 | Serge | 239 | static void vmw_print_capabilities(uint32_t capabilities) |
240 | { |
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241 | DRM_INFO("Capabilities:\n"); |
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242 | if (capabilities & SVGA_CAP_RECT_COPY) |
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243 | DRM_INFO(" Rect copy.\n"); |
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244 | if (capabilities & SVGA_CAP_CURSOR) |
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245 | DRM_INFO(" Cursor.\n"); |
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246 | if (capabilities & SVGA_CAP_CURSOR_BYPASS) |
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247 | DRM_INFO(" Cursor bypass.\n"); |
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248 | if (capabilities & SVGA_CAP_CURSOR_BYPASS_2) |
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249 | DRM_INFO(" Cursor bypass 2.\n"); |
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250 | if (capabilities & SVGA_CAP_8BIT_EMULATION) |
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251 | DRM_INFO(" 8bit emulation.\n"); |
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252 | if (capabilities & SVGA_CAP_ALPHA_CURSOR) |
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253 | DRM_INFO(" Alpha cursor.\n"); |
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254 | if (capabilities & SVGA_CAP_3D) |
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255 | DRM_INFO(" 3D.\n"); |
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256 | if (capabilities & SVGA_CAP_EXTENDED_FIFO) |
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257 | DRM_INFO(" Extended Fifo.\n"); |
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258 | if (capabilities & SVGA_CAP_MULTIMON) |
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259 | DRM_INFO(" Multimon.\n"); |
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260 | if (capabilities & SVGA_CAP_PITCHLOCK) |
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261 | DRM_INFO(" Pitchlock.\n"); |
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262 | if (capabilities & SVGA_CAP_IRQMASK) |
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263 | DRM_INFO(" Irq mask.\n"); |
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264 | if (capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) |
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265 | DRM_INFO(" Display Topology.\n"); |
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266 | if (capabilities & SVGA_CAP_GMR) |
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267 | DRM_INFO(" GMR.\n"); |
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268 | if (capabilities & SVGA_CAP_TRACES) |
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269 | DRM_INFO(" Traces.\n"); |
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270 | if (capabilities & SVGA_CAP_GMR2) |
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271 | DRM_INFO(" GMR2.\n"); |
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272 | if (capabilities & SVGA_CAP_SCREEN_OBJECT_2) |
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273 | DRM_INFO(" Screen Object 2.\n"); |
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4569 | Serge | 274 | if (capabilities & SVGA_CAP_COMMAND_BUFFERS) |
275 | DRM_INFO(" Command Buffers.\n"); |
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276 | if (capabilities & SVGA_CAP_CMD_BUFFERS_2) |
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277 | DRM_INFO(" Command Buffers 2.\n"); |
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278 | if (capabilities & SVGA_CAP_GBOBJECTS) |
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279 | DRM_INFO(" Guest Backed Resources.\n"); |
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4075 | Serge | 280 | } |
281 | |||
282 | /** |
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4569 | Serge | 283 | * vmw_dummy_query_bo_create - create a bo to hold a dummy query result |
4075 | Serge | 284 | * |
4569 | Serge | 285 | * @dev_priv: A device private structure. |
4075 | Serge | 286 | * |
4569 | Serge | 287 | * This function creates a small buffer object that holds the query |
288 | * result for dummy queries emitted as query barriers. |
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289 | * The function will then map the first page and initialize a pending |
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290 | * occlusion query result structure, Finally it will unmap the buffer. |
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291 | * No interruptible waits are done within this function. |
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4075 | Serge | 292 | * |
4569 | Serge | 293 | * Returns an error if bo creation or initialization fails. |
4075 | Serge | 294 | */ |
4569 | Serge | 295 | static int vmw_dummy_query_bo_create(struct vmw_private *dev_priv) |
4075 | Serge | 296 | { |
4569 | Serge | 297 | int ret; |
298 | struct ttm_buffer_object *bo; |
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4075 | Serge | 299 | struct ttm_bo_kmap_obj map; |
300 | volatile SVGA3dQueryResult *result; |
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301 | bool dummy; |
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302 | |||
4569 | Serge | 303 | /* |
304 | * Create the bo as pinned, so that a tryreserve will |
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305 | * immediately succeed. This is because we're the only |
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306 | * user of the bo currently. |
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307 | */ |
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308 | ret = ttm_bo_create(&dev_priv->bdev, |
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309 | PAGE_SIZE, |
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310 | ttm_bo_type_device, |
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311 | &vmw_sys_ne_placement, |
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312 | 0, false, NULL, |
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313 | &bo); |
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314 | |||
4075 | Serge | 315 | if (unlikely(ret != 0)) |
4569 | Serge | 316 | return ret; |
317 | |||
318 | ret = ttm_bo_reserve(bo, false, true, false, 0); |
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319 | BUG_ON(ret != 0); |
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320 | |||
4075 | Serge | 321 | ret = ttm_bo_kmap(bo, 0, 1, &map); |
322 | if (likely(ret == 0)) { |
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323 | result = ttm_kmap_obj_virtual(&map, &dummy); |
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324 | result->totalSize = sizeof(*result); |
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325 | result->state = SVGA3D_QUERYSTATE_PENDING; |
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326 | result->result32 = 0xff; |
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327 | ttm_bo_kunmap(&map); |
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4569 | Serge | 328 | } |
329 | vmw_bo_pin(bo, false); |
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4075 | Serge | 330 | ttm_bo_unreserve(bo); |
331 | |||
4569 | Serge | 332 | if (unlikely(ret != 0)) { |
333 | DRM_ERROR("Dummy query buffer map failed.\n"); |
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334 | ttm_bo_unref(&bo); |
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335 | } else |
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336 | dev_priv->dummy_query_bo = bo; |
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4075 | Serge | 337 | |
4569 | Serge | 338 | return ret; |
4075 | Serge | 339 | } |
340 | |||
341 | static int vmw_request_device(struct vmw_private *dev_priv) |
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342 | { |
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343 | int ret; |
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344 | ENTER(); |
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345 | |||
346 | ret = vmw_fifo_init(dev_priv, &dev_priv->fifo); |
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347 | if (unlikely(ret != 0)) { |
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348 | DRM_ERROR("Unable to initialize FIFO.\n"); |
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349 | return ret; |
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350 | } |
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351 | // vmw_fence_fifo_up(dev_priv->fman); |
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352 | // ret = vmw_dummy_query_bo_create(dev_priv); |
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353 | // if (unlikely(ret != 0)) |
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354 | // goto out_no_query_bo; |
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355 | // vmw_dummy_query_bo_prepare(dev_priv); |
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356 | |||
357 | LEAVE(); |
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358 | |||
359 | return 0; |
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360 | |||
361 | out_no_query_bo: |
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362 | vmw_fence_fifo_down(dev_priv->fman); |
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363 | vmw_fifo_release(dev_priv, &dev_priv->fifo); |
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364 | return ret; |
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365 | } |
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366 | |||
367 | static void vmw_release_device(struct vmw_private *dev_priv) |
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368 | { |
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369 | /* |
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370 | * Previous destructions should've released |
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371 | * the pinned bo. |
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372 | */ |
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373 | |||
374 | BUG_ON(dev_priv->pinned_bo != NULL); |
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375 | |||
376 | ttm_bo_unref(&dev_priv->dummy_query_bo); |
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377 | vmw_fence_fifo_down(dev_priv->fman); |
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378 | vmw_fifo_release(dev_priv, &dev_priv->fifo); |
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379 | } |
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380 | |||
4569 | Serge | 381 | |
4075 | Serge | 382 | /** |
383 | * Increase the 3d resource refcount. |
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384 | * If the count was prevously zero, initialize the fifo, switching to svga |
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385 | * mode. Note that the master holds a ref as well, and may request an |
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386 | * explicit switch to svga mode if fb is not running, using @unhide_svga. |
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387 | */ |
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388 | int vmw_3d_resource_inc(struct vmw_private *dev_priv, |
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389 | bool unhide_svga) |
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390 | { |
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391 | int ret = 0; |
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392 | |||
393 | mutex_lock(&dev_priv->release_mutex); |
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394 | if (unlikely(dev_priv->num_3d_resources++ == 0)) { |
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395 | ret = vmw_request_device(dev_priv); |
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396 | if (unlikely(ret != 0)) |
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397 | --dev_priv->num_3d_resources; |
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398 | } else if (unhide_svga) { |
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399 | mutex_lock(&dev_priv->hw_mutex); |
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400 | vmw_write(dev_priv, SVGA_REG_ENABLE, |
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401 | vmw_read(dev_priv, SVGA_REG_ENABLE) & |
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402 | ~SVGA_REG_ENABLE_HIDE); |
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403 | mutex_unlock(&dev_priv->hw_mutex); |
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404 | } |
||
405 | |||
406 | mutex_unlock(&dev_priv->release_mutex); |
||
407 | return ret; |
||
408 | } |
||
409 | |||
410 | /** |
||
411 | * Decrease the 3d resource refcount. |
||
412 | * If the count reaches zero, disable the fifo, switching to vga mode. |
||
413 | * Note that the master holds a refcount as well, and may request an |
||
414 | * explicit switch to vga mode when it releases its refcount to account |
||
415 | * for the situation of an X server vt switch to VGA with 3d resources |
||
416 | * active. |
||
417 | */ |
||
418 | void vmw_3d_resource_dec(struct vmw_private *dev_priv, |
||
419 | bool hide_svga) |
||
420 | { |
||
421 | int32_t n3d; |
||
422 | |||
423 | mutex_lock(&dev_priv->release_mutex); |
||
424 | if (unlikely(--dev_priv->num_3d_resources == 0)) |
||
425 | vmw_release_device(dev_priv); |
||
426 | else if (hide_svga) { |
||
427 | mutex_lock(&dev_priv->hw_mutex); |
||
428 | vmw_write(dev_priv, SVGA_REG_ENABLE, |
||
429 | vmw_read(dev_priv, SVGA_REG_ENABLE) | |
||
430 | SVGA_REG_ENABLE_HIDE); |
||
431 | mutex_unlock(&dev_priv->hw_mutex); |
||
432 | } |
||
433 | |||
434 | n3d = (int32_t) dev_priv->num_3d_resources; |
||
435 | mutex_unlock(&dev_priv->release_mutex); |
||
436 | |||
437 | BUG_ON(n3d < 0); |
||
438 | } |
||
439 | |||
440 | /** |
||
441 | * Sets the initial_[width|height] fields on the given vmw_private. |
||
442 | * |
||
443 | * It does so by reading SVGA_REG_[WIDTH|HEIGHT] regs and then |
||
444 | * clamping the value to fb_max_[width|height] fields and the |
||
445 | * VMW_MIN_INITIAL_[WIDTH|HEIGHT]. |
||
446 | * If the values appear to be invalid, set them to |
||
447 | * VMW_MIN_INITIAL_[WIDTH|HEIGHT]. |
||
448 | */ |
||
449 | static void vmw_get_initial_size(struct vmw_private *dev_priv) |
||
450 | { |
||
451 | uint32_t width; |
||
452 | uint32_t height; |
||
453 | |||
454 | width = vmw_read(dev_priv, SVGA_REG_WIDTH); |
||
455 | height = vmw_read(dev_priv, SVGA_REG_HEIGHT); |
||
456 | |||
457 | width = max_t(uint32_t, width, VMW_MIN_INITIAL_WIDTH); |
||
458 | height = max_t(uint32_t, height, VMW_MIN_INITIAL_HEIGHT); |
||
459 | |||
460 | if (width > dev_priv->fb_max_width || |
||
461 | height > dev_priv->fb_max_height) { |
||
462 | |||
463 | /* |
||
464 | * This is a host error and shouldn't occur. |
||
465 | */ |
||
466 | |||
467 | width = VMW_MIN_INITIAL_WIDTH; |
||
468 | height = VMW_MIN_INITIAL_HEIGHT; |
||
469 | } |
||
470 | |||
471 | dev_priv->initial_width = width; |
||
472 | dev_priv->initial_height = height; |
||
473 | } |
||
474 | |||
4569 | Serge | 475 | /** |
4570 | Serge | 476 | * vmw_dma_select_mode - Determine how DMA mappings should be set up for this |
477 | * system. |
||
478 | * |
||
479 | * @dev_priv: Pointer to a struct vmw_private |
||
480 | * |
||
481 | * This functions tries to determine the IOMMU setup and what actions |
||
482 | * need to be taken by the driver to make system pages visible to the |
||
483 | * device. |
||
484 | * If this function decides that DMA is not possible, it returns -EINVAL. |
||
485 | * The driver may then try to disable features of the device that require |
||
486 | * DMA. |
||
487 | */ |
||
488 | static int vmw_dma_select_mode(struct vmw_private *dev_priv) |
||
489 | { |
||
490 | static const char *names[vmw_dma_map_max] = { |
||
491 | [vmw_dma_phys] = "Using physical TTM page addresses.", |
||
492 | [vmw_dma_alloc_coherent] = "Using coherent TTM pages.", |
||
493 | [vmw_dma_map_populate] = "Keeping DMA mappings.", |
||
494 | [vmw_dma_map_bind] = "Giving up DMA mappings early."}; |
||
495 | |||
496 | dev_priv->map_mode = vmw_dma_phys; |
||
497 | DRM_INFO("DMA map mode: %s\n", names[dev_priv->map_mode]); |
||
498 | |||
499 | return 0; |
||
500 | } |
||
501 | |||
502 | /** |
||
4569 | Serge | 503 | * vmw_dma_masks - set required page- and dma masks |
504 | * |
||
505 | * @dev: Pointer to struct drm-device |
||
506 | * |
||
507 | * With 32-bit we can only handle 32 bit PFNs. Optionally set that |
||
508 | * restriction also for 64-bit systems. |
||
509 | */ |
||
510 | #ifdef CONFIG_INTEL_IOMMU |
||
511 | static int vmw_dma_masks(struct vmw_private *dev_priv) |
||
512 | { |
||
513 | struct drm_device *dev = dev_priv->dev; |
||
514 | |||
515 | if (intel_iommu_enabled && |
||
516 | (sizeof(unsigned long) == 4 || vmw_restrict_dma_mask)) { |
||
517 | DRM_INFO("Restricting DMA addresses to 44 bits.\n"); |
||
518 | return dma_set_mask(dev->dev, DMA_BIT_MASK(44)); |
||
519 | } |
||
520 | return 0; |
||
521 | } |
||
522 | #else |
||
523 | static int vmw_dma_masks(struct vmw_private *dev_priv) |
||
524 | { |
||
525 | return 0; |
||
526 | } |
||
527 | #endif |
||
528 | |||
4075 | Serge | 529 | static int vmw_driver_load(struct drm_device *dev, unsigned long chipset) |
530 | { |
||
531 | struct vmw_private *dev_priv; |
||
532 | int ret; |
||
533 | uint32_t svga_id; |
||
534 | enum vmw_res_type i; |
||
4569 | Serge | 535 | bool refuse_dma = false; |
4075 | Serge | 536 | |
537 | ENTER(); |
||
538 | |||
539 | dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL); |
||
540 | if (unlikely(dev_priv == NULL)) { |
||
541 | DRM_ERROR("Failed allocating a device private struct.\n"); |
||
542 | return -ENOMEM; |
||
543 | } |
||
544 | |||
545 | pci_set_master(dev->pdev); |
||
546 | |||
547 | dev_priv->dev = dev; |
||
548 | dev_priv->vmw_chipset = chipset; |
||
549 | dev_priv->last_read_seqno = (uint32_t) -100; |
||
550 | mutex_init(&dev_priv->hw_mutex); |
||
551 | mutex_init(&dev_priv->cmdbuf_mutex); |
||
552 | mutex_init(&dev_priv->release_mutex); |
||
4569 | Serge | 553 | mutex_init(&dev_priv->binding_mutex); |
4075 | Serge | 554 | rwlock_init(&dev_priv->resource_lock); |
555 | |||
556 | for (i = vmw_res_context; i < vmw_res_max; ++i) { |
||
557 | idr_init(&dev_priv->res_idr[i]); |
||
558 | INIT_LIST_HEAD(&dev_priv->res_lru[i]); |
||
559 | } |
||
560 | |||
561 | mutex_init(&dev_priv->init_mutex); |
||
562 | init_waitqueue_head(&dev_priv->fence_queue); |
||
563 | init_waitqueue_head(&dev_priv->fifo_queue); |
||
564 | dev_priv->fence_queue_waiters = 0; |
||
565 | atomic_set(&dev_priv->fifo_queue_waiters, 0); |
||
566 | |||
567 | dev_priv->used_memory_size = 0; |
||
568 | |||
569 | dev_priv->io_start = pci_resource_start(dev->pdev, 0); |
||
570 | dev_priv->vram_start = pci_resource_start(dev->pdev, 1); |
||
571 | dev_priv->mmio_start = pci_resource_start(dev->pdev, 2); |
||
572 | |||
573 | printk("io: %x vram: %x mmio: %x\n",dev_priv->io_start, |
||
574 | dev_priv->vram_start,dev_priv->mmio_start); |
||
575 | |||
576 | dev_priv->enable_fb = enable_fbdev; |
||
577 | |||
578 | mutex_lock(&dev_priv->hw_mutex); |
||
579 | |||
580 | vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2); |
||
581 | svga_id = vmw_read(dev_priv, SVGA_REG_ID); |
||
582 | if (svga_id != SVGA_ID_2) { |
||
583 | ret = -ENOSYS; |
||
584 | DRM_ERROR("Unsupported SVGA ID 0x%x\n", svga_id); |
||
585 | mutex_unlock(&dev_priv->hw_mutex); |
||
586 | goto out_err0; |
||
587 | } |
||
588 | |||
589 | dev_priv->capabilities = vmw_read(dev_priv, SVGA_REG_CAPABILITIES); |
||
4570 | Serge | 590 | ret = vmw_dma_select_mode(dev_priv); |
591 | if (unlikely(ret != 0)) { |
||
592 | DRM_INFO("Restricting capabilities due to IOMMU setup.\n"); |
||
593 | refuse_dma = true; |
||
594 | } |
||
4075 | Serge | 595 | |
596 | dev_priv->vram_size = vmw_read(dev_priv, SVGA_REG_VRAM_SIZE); |
||
597 | dev_priv->mmio_size = vmw_read(dev_priv, SVGA_REG_MEM_SIZE); |
||
598 | dev_priv->fb_max_width = vmw_read(dev_priv, SVGA_REG_MAX_WIDTH); |
||
599 | dev_priv->fb_max_height = vmw_read(dev_priv, SVGA_REG_MAX_HEIGHT); |
||
600 | |||
601 | vmw_get_initial_size(dev_priv); |
||
602 | |||
4569 | Serge | 603 | if (dev_priv->capabilities & SVGA_CAP_GMR2) { |
4075 | Serge | 604 | dev_priv->max_gmr_ids = |
605 | vmw_read(dev_priv, SVGA_REG_GMR_MAX_IDS); |
||
606 | dev_priv->max_gmr_pages = |
||
607 | vmw_read(dev_priv, SVGA_REG_GMRS_MAX_PAGES); |
||
608 | dev_priv->memory_size = |
||
609 | vmw_read(dev_priv, SVGA_REG_MEMORY_SIZE); |
||
610 | dev_priv->memory_size -= dev_priv->vram_size; |
||
611 | } else { |
||
612 | /* |
||
613 | * An arbitrary limit of 512MiB on surface |
||
614 | * memory. But all HWV8 hardware supports GMR2. |
||
615 | */ |
||
616 | dev_priv->memory_size = 512*1024*1024; |
||
617 | } |
||
4569 | Serge | 618 | dev_priv->max_mob_pages = 0; |
619 | if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) { |
||
620 | uint64_t mem_size = |
||
621 | vmw_read(dev_priv, |
||
622 | SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB); |
||
4075 | Serge | 623 | |
4569 | Serge | 624 | dev_priv->max_mob_pages = mem_size * 1024 / PAGE_SIZE; |
625 | dev_priv->prim_bb_mem = |
||
626 | vmw_read(dev_priv, |
||
627 | SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM); |
||
628 | } else |
||
629 | dev_priv->prim_bb_mem = dev_priv->vram_size; |
||
630 | |||
631 | ret = vmw_dma_masks(dev_priv); |
||
632 | if (unlikely(ret != 0)) { |
||
633 | mutex_unlock(&dev_priv->hw_mutex); |
||
634 | goto out_err0; |
||
635 | } |
||
636 | |||
637 | if (unlikely(dev_priv->prim_bb_mem < dev_priv->vram_size)) |
||
638 | dev_priv->prim_bb_mem = dev_priv->vram_size; |
||
639 | |||
4075 | Serge | 640 | mutex_unlock(&dev_priv->hw_mutex); |
641 | |||
642 | vmw_print_capabilities(dev_priv->capabilities); |
||
643 | |||
4569 | Serge | 644 | if (dev_priv->capabilities & SVGA_CAP_GMR2) { |
4075 | Serge | 645 | DRM_INFO("Max GMR ids is %u\n", |
646 | (unsigned)dev_priv->max_gmr_ids); |
||
647 | DRM_INFO("Max number of GMR pages is %u\n", |
||
648 | (unsigned)dev_priv->max_gmr_pages); |
||
649 | DRM_INFO("Max dedicated hypervisor surface memory is %u kiB\n", |
||
650 | (unsigned)dev_priv->memory_size / 1024); |
||
651 | } |
||
4569 | Serge | 652 | DRM_INFO("Maximum display memory size is %u kiB\n", |
653 | dev_priv->prim_bb_mem / 1024); |
||
4075 | Serge | 654 | DRM_INFO("VRAM at 0x%08x size is %u kiB\n", |
655 | dev_priv->vram_start, dev_priv->vram_size / 1024); |
||
656 | DRM_INFO("MMIO at 0x%08x size is %u kiB\n", |
||
657 | dev_priv->mmio_start, dev_priv->mmio_size / 1024); |
||
658 | |||
659 | ret = vmw_ttm_global_init(dev_priv); |
||
660 | if (unlikely(ret != 0)) |
||
661 | goto out_err0; |
||
662 | |||
663 | |||
4569 | Serge | 664 | vmw_master_init(&dev_priv->fbdev_master); |
665 | dev_priv->active_master = &dev_priv->fbdev_master; |
||
4075 | Serge | 666 | |
667 | |||
668 | ret = ttm_bo_device_init(&dev_priv->bdev, |
||
669 | dev_priv->bo_global_ref.ref.object, |
||
670 | &vmw_bo_driver, VMWGFX_FILE_PAGE_OFFSET, |
||
671 | false); |
||
672 | if (unlikely(ret != 0)) { |
||
673 | DRM_ERROR("Failed initializing TTM buffer object driver.\n"); |
||
674 | goto out_err1; |
||
675 | } |
||
676 | |||
677 | ret = ttm_bo_init_mm(&dev_priv->bdev, TTM_PL_VRAM, |
||
678 | (dev_priv->vram_size >> PAGE_SHIFT)); |
||
679 | if (unlikely(ret != 0)) { |
||
680 | DRM_ERROR("Failed initializing memory manager for VRAM.\n"); |
||
681 | goto out_err2; |
||
682 | } |
||
683 | |||
684 | dev_priv->has_gmr = true; |
||
4569 | Serge | 685 | if (((dev_priv->capabilities & (SVGA_CAP_GMR | SVGA_CAP_GMR2)) == 0) || |
686 | refuse_dma || ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_GMR, |
||
687 | VMW_PL_GMR) != 0) { |
||
4075 | Serge | 688 | DRM_INFO("No GMR memory available. " |
689 | "Graphics memory resources are very limited.\n"); |
||
690 | dev_priv->has_gmr = false; |
||
691 | } |
||
692 | |||
4569 | Serge | 693 | if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) { |
694 | dev_priv->has_mob = true; |
||
695 | if (ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_MOB, |
||
696 | VMW_PL_MOB) != 0) { |
||
697 | DRM_INFO("No MOB memory available. " |
||
698 | "3D will be disabled.\n"); |
||
699 | dev_priv->has_mob = false; |
||
700 | } |
||
701 | } |
||
4075 | Serge | 702 | dev_priv->mmio_virt = ioremap_wc(dev_priv->mmio_start, |
703 | dev_priv->mmio_size); |
||
704 | |||
705 | if (unlikely(dev_priv->mmio_virt == NULL)) { |
||
706 | ret = -ENOMEM; |
||
707 | DRM_ERROR("Failed mapping MMIO.\n"); |
||
708 | goto out_err3; |
||
709 | } |
||
710 | |||
711 | /* Need mmio memory to check for fifo pitchlock cap. */ |
||
712 | if (!(dev_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) && |
||
713 | !(dev_priv->capabilities & SVGA_CAP_PITCHLOCK) && |
||
714 | !vmw_fifo_have_pitchlock(dev_priv)) { |
||
715 | ret = -ENOSYS; |
||
716 | DRM_ERROR("Hardware has no pitchlock\n"); |
||
717 | goto out_err4; |
||
718 | } |
||
719 | |||
4569 | Serge | 720 | // dev_priv->tdev = ttm_object_device_init |
721 | // (dev_priv->mem_global_ref.object, 12, &vmw_prime_dmabuf_ops); |
||
4075 | Serge | 722 | |
4569 | Serge | 723 | // if (unlikely(dev_priv->tdev == NULL)) { |
724 | // DRM_ERROR("Unable to initialize TTM object management.\n"); |
||
725 | // ret = -ENOMEM; |
||
726 | // goto out_err4; |
||
727 | // } |
||
4075 | Serge | 728 | |
729 | dev->dev_private = dev_priv; |
||
730 | |||
731 | #if 0 |
||
732 | |||
733 | if (dev_priv->capabilities & SVGA_CAP_IRQMASK) { |
||
734 | ret = drm_irq_install(dev); |
||
735 | if (ret != 0) { |
||
736 | DRM_ERROR("Failed installing irq: %d\n", ret); |
||
737 | goto out_no_irq; |
||
738 | } |
||
739 | } |
||
740 | |||
741 | dev_priv->fman = vmw_fence_manager_init(dev_priv); |
||
4111 | Serge | 742 | if (unlikely(dev_priv->fman == NULL)) { |
743 | ret = -ENOMEM; |
||
4075 | Serge | 744 | goto out_no_fman; |
4111 | Serge | 745 | } |
4075 | Serge | 746 | |
747 | vmw_kms_save_vga(dev_priv); |
||
748 | #endif |
||
749 | |||
750 | /* Start kms and overlay systems, needs fifo. */ |
||
751 | ret = vmw_kms_init(dev_priv); |
||
752 | if (unlikely(ret != 0)) |
||
753 | goto out_no_kms; |
||
754 | |||
4080 | Serge | 755 | if (dev_priv->enable_fb) { |
4075 | Serge | 756 | ret = vmw_3d_resource_inc(dev_priv, true); |
757 | if (unlikely(ret != 0)) |
||
758 | goto out_no_fifo; |
||
759 | // vmw_fb_init(dev_priv); |
||
4080 | Serge | 760 | } |
4075 | Serge | 761 | |
4111 | Serge | 762 | main_device = dev; |
763 | |||
4080 | Serge | 764 | LEAVE(); |
4075 | Serge | 765 | return 0; |
766 | |||
767 | out_no_fifo: |
||
768 | // vmw_overlay_close(dev_priv); |
||
769 | // vmw_kms_close(dev_priv); |
||
770 | out_no_kms: |
||
771 | // vmw_kms_restore_vga(dev_priv); |
||
772 | // vmw_fence_manager_takedown(dev_priv->fman); |
||
773 | out_no_fman: |
||
774 | // if (dev_priv->capabilities & SVGA_CAP_IRQMASK) |
||
775 | // drm_irq_uninstall(dev_priv->dev); |
||
776 | out_no_irq: |
||
777 | // if (dev_priv->stealth) |
||
778 | // pci_release_region(dev->pdev, 2); |
||
779 | // else |
||
780 | // pci_release_regions(dev->pdev); |
||
781 | out_no_device: |
||
782 | // ttm_object_device_release(&dev_priv->tdev); |
||
783 | out_err4: |
||
784 | // iounmap(dev_priv->mmio_virt); |
||
785 | out_err3: |
||
786 | // arch_phys_wc_del(dev_priv->mmio_mtrr); |
||
787 | // if (dev_priv->has_gmr) |
||
788 | // (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR); |
||
789 | // (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM); |
||
790 | out_err2: |
||
791 | // (void)ttm_bo_device_release(&dev_priv->bdev); |
||
792 | out_err1: |
||
793 | // vmw_ttm_global_release(dev_priv); |
||
794 | out_err0: |
||
795 | // for (i = vmw_res_context; i < vmw_res_max; ++i) |
||
796 | // idr_destroy(&dev_priv->res_idr[i]); |
||
797 | |||
798 | kfree(dev_priv); |
||
799 | return ret; |
||
800 | } |
||
801 | |||
802 | #if 0 |
||
803 | static int vmw_driver_unload(struct drm_device *dev) |
||
804 | { |
||
805 | struct vmw_private *dev_priv = vmw_priv(dev); |
||
806 | enum vmw_res_type i; |
||
807 | |||
808 | unregister_pm_notifier(&dev_priv->pm_nb); |
||
809 | |||
810 | if (dev_priv->ctx.res_ht_initialized) |
||
811 | drm_ht_remove(&dev_priv->ctx.res_ht); |
||
812 | if (dev_priv->ctx.cmd_bounce) |
||
813 | vfree(dev_priv->ctx.cmd_bounce); |
||
814 | if (dev_priv->enable_fb) { |
||
815 | vmw_fb_close(dev_priv); |
||
816 | vmw_kms_restore_vga(dev_priv); |
||
817 | vmw_3d_resource_dec(dev_priv, false); |
||
818 | } |
||
819 | vmw_kms_close(dev_priv); |
||
820 | vmw_overlay_close(dev_priv); |
||
821 | vmw_fence_manager_takedown(dev_priv->fman); |
||
822 | if (dev_priv->capabilities & SVGA_CAP_IRQMASK) |
||
823 | drm_irq_uninstall(dev_priv->dev); |
||
824 | if (dev_priv->stealth) |
||
825 | pci_release_region(dev->pdev, 2); |
||
826 | else |
||
827 | pci_release_regions(dev->pdev); |
||
828 | |||
829 | ttm_object_device_release(&dev_priv->tdev); |
||
830 | iounmap(dev_priv->mmio_virt); |
||
831 | arch_phys_wc_del(dev_priv->mmio_mtrr); |
||
4569 | Serge | 832 | if (dev_priv->has_mob) |
833 | (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_MOB); |
||
4075 | Serge | 834 | if (dev_priv->has_gmr) |
835 | (void)ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR); |
||
836 | (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM); |
||
837 | (void)ttm_bo_device_release(&dev_priv->bdev); |
||
838 | vmw_ttm_global_release(dev_priv); |
||
839 | |||
840 | for (i = vmw_res_context; i < vmw_res_max; ++i) |
||
841 | idr_destroy(&dev_priv->res_idr[i]); |
||
842 | |||
843 | kfree(dev_priv); |
||
844 | |||
845 | return 0; |
||
846 | } |
||
847 | |||
848 | static void vmw_preclose(struct drm_device *dev, |
||
849 | struct drm_file *file_priv) |
||
850 | { |
||
851 | struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv); |
||
852 | struct vmw_private *dev_priv = vmw_priv(dev); |
||
853 | |||
854 | vmw_event_fence_fpriv_gone(dev_priv->fman, &vmw_fp->fence_events); |
||
855 | } |
||
856 | |||
857 | static void vmw_postclose(struct drm_device *dev, |
||
858 | struct drm_file *file_priv) |
||
859 | { |
||
860 | struct vmw_fpriv *vmw_fp; |
||
861 | |||
862 | vmw_fp = vmw_fpriv(file_priv); |
||
4569 | Serge | 863 | |
864 | if (vmw_fp->locked_master) { |
||
865 | struct vmw_master *vmaster = |
||
866 | vmw_master(vmw_fp->locked_master); |
||
867 | |||
868 | ttm_vt_unlock(&vmaster->lock); |
||
869 | drm_master_put(&vmw_fp->locked_master); |
||
870 | } |
||
871 | |||
4075 | Serge | 872 | ttm_object_file_release(&vmw_fp->tfile); |
873 | kfree(vmw_fp); |
||
874 | } |
||
875 | #endif |
||
876 | |||
877 | static int vmw_driver_open(struct drm_device *dev, struct drm_file *file_priv) |
||
878 | { |
||
879 | struct vmw_private *dev_priv = vmw_priv(dev); |
||
880 | struct vmw_fpriv *vmw_fp; |
||
881 | int ret = -ENOMEM; |
||
882 | |||
883 | vmw_fp = kzalloc(sizeof(*vmw_fp), GFP_KERNEL); |
||
884 | if (unlikely(vmw_fp == NULL)) |
||
885 | return ret; |
||
886 | |||
887 | INIT_LIST_HEAD(&vmw_fp->fence_events); |
||
888 | // vmw_fp->tfile = ttm_object_file_init(dev_priv->tdev, 10); |
||
889 | // if (unlikely(vmw_fp->tfile == NULL)) |
||
890 | // goto out_no_tfile; |
||
891 | |||
892 | file_priv->driver_priv = vmw_fp; |
||
893 | // dev_priv->bdev.dev_mapping = dev->dev_mapping; |
||
894 | |||
895 | return 0; |
||
896 | |||
897 | out_no_tfile: |
||
898 | kfree(vmw_fp); |
||
899 | return ret; |
||
900 | } |
||
901 | |||
902 | #if 0 |
||
903 | static long vmw_unlocked_ioctl(struct file *filp, unsigned int cmd, |
||
904 | unsigned long arg) |
||
905 | { |
||
906 | struct drm_file *file_priv = filp->private_data; |
||
907 | struct drm_device *dev = file_priv->minor->dev; |
||
908 | unsigned int nr = DRM_IOCTL_NR(cmd); |
||
909 | |||
910 | /* |
||
911 | * Do extra checking on driver private ioctls. |
||
912 | */ |
||
913 | |||
914 | if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END) |
||
915 | && (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls)) { |
||
4111 | Serge | 916 | const struct drm_ioctl_desc *ioctl = |
4075 | Serge | 917 | &vmw_ioctls[nr - DRM_COMMAND_BASE]; |
918 | |||
919 | if (unlikely(ioctl->cmd_drv != cmd)) { |
||
920 | DRM_ERROR("Invalid command format, ioctl %d\n", |
||
921 | nr - DRM_COMMAND_BASE); |
||
922 | return -EINVAL; |
||
923 | } |
||
924 | } |
||
925 | |||
926 | return drm_ioctl(filp, cmd, arg); |
||
927 | } |
||
928 | |||
929 | static void vmw_lastclose(struct drm_device *dev) |
||
930 | { |
||
931 | struct drm_crtc *crtc; |
||
932 | struct drm_mode_set set; |
||
933 | int ret; |
||
934 | |||
935 | set.x = 0; |
||
936 | set.y = 0; |
||
937 | set.fb = NULL; |
||
938 | set.mode = NULL; |
||
939 | set.connectors = NULL; |
||
940 | set.num_connectors = 0; |
||
941 | |||
942 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
||
943 | set.crtc = crtc; |
||
944 | ret = drm_mode_set_config_internal(&set); |
||
945 | WARN_ON(ret != 0); |
||
946 | } |
||
947 | |||
948 | } |
||
4569 | Serge | 949 | #endif |
4075 | Serge | 950 | |
951 | static void vmw_master_init(struct vmw_master *vmaster) |
||
952 | { |
||
4570 | Serge | 953 | ttm_lock_init(&vmaster->lock); |
4075 | Serge | 954 | INIT_LIST_HEAD(&vmaster->fb_surf); |
955 | mutex_init(&vmaster->fb_surf_mutex); |
||
956 | } |
||
957 | |||
958 | static int vmw_master_create(struct drm_device *dev, |
||
959 | struct drm_master *master) |
||
960 | { |
||
961 | struct vmw_master *vmaster; |
||
962 | |||
963 | vmaster = kzalloc(sizeof(*vmaster), GFP_KERNEL); |
||
964 | if (unlikely(vmaster == NULL)) |
||
965 | return -ENOMEM; |
||
966 | |||
967 | vmw_master_init(vmaster); |
||
4569 | Serge | 968 | // ttm_lock_set_kill(&vmaster->lock, true, SIGTERM); |
4075 | Serge | 969 | master->driver_priv = vmaster; |
970 | |||
971 | return 0; |
||
972 | } |
||
973 | |||
974 | static void vmw_master_destroy(struct drm_device *dev, |
||
975 | struct drm_master *master) |
||
976 | { |
||
977 | struct vmw_master *vmaster = vmw_master(master); |
||
978 | |||
979 | master->driver_priv = NULL; |
||
980 | kfree(vmaster); |
||
981 | } |
||
982 | |||
4569 | Serge | 983 | #if 0 |
4075 | Serge | 984 | static int vmw_master_set(struct drm_device *dev, |
985 | struct drm_file *file_priv, |
||
986 | bool from_open) |
||
987 | { |
||
988 | struct vmw_private *dev_priv = vmw_priv(dev); |
||
989 | struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv); |
||
990 | struct vmw_master *active = dev_priv->active_master; |
||
991 | struct vmw_master *vmaster = vmw_master(file_priv->master); |
||
992 | int ret = 0; |
||
993 | |||
994 | if (!dev_priv->enable_fb) { |
||
995 | ret = vmw_3d_resource_inc(dev_priv, true); |
||
996 | if (unlikely(ret != 0)) |
||
997 | return ret; |
||
998 | vmw_kms_save_vga(dev_priv); |
||
999 | mutex_lock(&dev_priv->hw_mutex); |
||
1000 | vmw_write(dev_priv, SVGA_REG_TRACES, 0); |
||
1001 | mutex_unlock(&dev_priv->hw_mutex); |
||
1002 | } |
||
1003 | |||
1004 | if (active) { |
||
1005 | BUG_ON(active != &dev_priv->fbdev_master); |
||
1006 | ret = ttm_vt_lock(&active->lock, false, vmw_fp->tfile); |
||
1007 | if (unlikely(ret != 0)) |
||
1008 | goto out_no_active_lock; |
||
1009 | |||
1010 | ttm_lock_set_kill(&active->lock, true, SIGTERM); |
||
1011 | ret = ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_VRAM); |
||
1012 | if (unlikely(ret != 0)) { |
||
1013 | DRM_ERROR("Unable to clean VRAM on " |
||
1014 | "master drop.\n"); |
||
1015 | } |
||
1016 | |||
1017 | dev_priv->active_master = NULL; |
||
1018 | } |
||
1019 | |||
1020 | ttm_lock_set_kill(&vmaster->lock, false, SIGTERM); |
||
1021 | if (!from_open) { |
||
1022 | ttm_vt_unlock(&vmaster->lock); |
||
1023 | BUG_ON(vmw_fp->locked_master != file_priv->master); |
||
1024 | drm_master_put(&vmw_fp->locked_master); |
||
1025 | } |
||
1026 | |||
1027 | dev_priv->active_master = vmaster; |
||
1028 | |||
1029 | return 0; |
||
1030 | |||
1031 | out_no_active_lock: |
||
1032 | if (!dev_priv->enable_fb) { |
||
1033 | vmw_kms_restore_vga(dev_priv); |
||
1034 | vmw_3d_resource_dec(dev_priv, true); |
||
1035 | mutex_lock(&dev_priv->hw_mutex); |
||
1036 | vmw_write(dev_priv, SVGA_REG_TRACES, 1); |
||
1037 | mutex_unlock(&dev_priv->hw_mutex); |
||
1038 | } |
||
1039 | return ret; |
||
1040 | } |
||
1041 | |||
1042 | static void vmw_master_drop(struct drm_device *dev, |
||
1043 | struct drm_file *file_priv, |
||
1044 | bool from_release) |
||
1045 | { |
||
1046 | struct vmw_private *dev_priv = vmw_priv(dev); |
||
1047 | struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv); |
||
1048 | struct vmw_master *vmaster = vmw_master(file_priv->master); |
||
1049 | int ret; |
||
1050 | |||
1051 | /** |
||
1052 | * Make sure the master doesn't disappear while we have |
||
1053 | * it locked. |
||
1054 | */ |
||
1055 | |||
1056 | vmw_fp->locked_master = drm_master_get(file_priv->master); |
||
1057 | ret = ttm_vt_lock(&vmaster->lock, false, vmw_fp->tfile); |
||
1058 | if (unlikely((ret != 0))) { |
||
1059 | DRM_ERROR("Unable to lock TTM at VT switch.\n"); |
||
1060 | drm_master_put(&vmw_fp->locked_master); |
||
1061 | } |
||
1062 | |||
4569 | Serge | 1063 | vmw_execbuf_release_pinned_bo(dev_priv); |
4075 | Serge | 1064 | |
1065 | if (!dev_priv->enable_fb) { |
||
1066 | ret = ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_VRAM); |
||
1067 | if (unlikely(ret != 0)) |
||
1068 | DRM_ERROR("Unable to clean VRAM on master drop.\n"); |
||
1069 | vmw_kms_restore_vga(dev_priv); |
||
1070 | vmw_3d_resource_dec(dev_priv, true); |
||
1071 | mutex_lock(&dev_priv->hw_mutex); |
||
1072 | vmw_write(dev_priv, SVGA_REG_TRACES, 1); |
||
1073 | mutex_unlock(&dev_priv->hw_mutex); |
||
1074 | } |
||
1075 | |||
1076 | dev_priv->active_master = &dev_priv->fbdev_master; |
||
1077 | ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM); |
||
1078 | ttm_vt_unlock(&dev_priv->fbdev_master.lock); |
||
1079 | |||
1080 | if (dev_priv->enable_fb) |
||
1081 | vmw_fb_on(dev_priv); |
||
1082 | } |
||
1083 | |||
4080 | Serge | 1084 | |
1085 | static void vmw_remove(struct pci_dev *pdev) |
||
1086 | { |
||
1087 | struct drm_device *dev = pci_get_drvdata(pdev); |
||
1088 | |||
1089 | drm_put_dev(dev); |
||
1090 | } |
||
1091 | |||
1092 | static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val, |
||
1093 | void *ptr) |
||
1094 | { |
||
1095 | struct vmw_private *dev_priv = |
||
1096 | container_of(nb, struct vmw_private, pm_nb); |
||
1097 | struct vmw_master *vmaster = dev_priv->active_master; |
||
1098 | |||
1099 | switch (val) { |
||
1100 | case PM_HIBERNATION_PREPARE: |
||
1101 | case PM_SUSPEND_PREPARE: |
||
1102 | ttm_suspend_lock(&vmaster->lock); |
||
1103 | |||
1104 | /** |
||
1105 | * This empties VRAM and unbinds all GMR bindings. |
||
1106 | * Buffer contents is moved to swappable memory. |
||
1107 | */ |
||
1108 | vmw_execbuf_release_pinned_bo(dev_priv); |
||
1109 | vmw_resource_evict_all(dev_priv); |
||
1110 | ttm_bo_swapout_all(&dev_priv->bdev); |
||
1111 | |||
1112 | break; |
||
1113 | case PM_POST_HIBERNATION: |
||
1114 | case PM_POST_SUSPEND: |
||
1115 | case PM_POST_RESTORE: |
||
1116 | ttm_suspend_unlock(&vmaster->lock); |
||
1117 | |||
1118 | break; |
||
1119 | case PM_RESTORE_PREPARE: |
||
1120 | break; |
||
1121 | default: |
||
1122 | break; |
||
1123 | } |
||
1124 | return 0; |
||
1125 | } |
||
1126 | |||
1127 | /** |
||
1128 | * These might not be needed with the virtual SVGA device. |
||
1129 | */ |
||
1130 | |||
1131 | static int vmw_pci_suspend(struct pci_dev *pdev, pm_message_t state) |
||
1132 | { |
||
1133 | struct drm_device *dev = pci_get_drvdata(pdev); |
||
1134 | struct vmw_private *dev_priv = vmw_priv(dev); |
||
1135 | |||
1136 | if (dev_priv->num_3d_resources != 0) { |
||
1137 | DRM_INFO("Can't suspend or hibernate " |
||
1138 | "while 3D resources are active.\n"); |
||
1139 | return -EBUSY; |
||
1140 | } |
||
1141 | |||
1142 | pci_save_state(pdev); |
||
1143 | pci_disable_device(pdev); |
||
1144 | pci_set_power_state(pdev, PCI_D3hot); |
||
1145 | return 0; |
||
1146 | } |
||
1147 | |||
1148 | static int vmw_pci_resume(struct pci_dev *pdev) |
||
1149 | { |
||
1150 | pci_set_power_state(pdev, PCI_D0); |
||
1151 | pci_restore_state(pdev); |
||
1152 | return pci_enable_device(pdev); |
||
1153 | } |
||
1154 | |||
1155 | static int vmw_pm_suspend(struct device *kdev) |
||
1156 | { |
||
1157 | struct pci_dev *pdev = to_pci_dev(kdev); |
||
1158 | struct pm_message dummy; |
||
1159 | |||
1160 | dummy.event = 0; |
||
1161 | |||
1162 | return vmw_pci_suspend(pdev, dummy); |
||
1163 | } |
||
1164 | |||
1165 | static int vmw_pm_resume(struct device *kdev) |
||
1166 | { |
||
1167 | struct pci_dev *pdev = to_pci_dev(kdev); |
||
1168 | |||
1169 | return vmw_pci_resume(pdev); |
||
1170 | } |
||
1171 | |||
1172 | static int vmw_pm_prepare(struct device *kdev) |
||
1173 | { |
||
1174 | struct pci_dev *pdev = to_pci_dev(kdev); |
||
1175 | struct drm_device *dev = pci_get_drvdata(pdev); |
||
1176 | struct vmw_private *dev_priv = vmw_priv(dev); |
||
1177 | |||
1178 | /** |
||
1179 | * Release 3d reference held by fbdev and potentially |
||
1180 | * stop fifo. |
||
1181 | */ |
||
1182 | dev_priv->suspended = true; |
||
1183 | if (dev_priv->enable_fb) |
||
1184 | vmw_3d_resource_dec(dev_priv, true); |
||
1185 | |||
1186 | if (dev_priv->num_3d_resources != 0) { |
||
1187 | |||
1188 | DRM_INFO("Can't suspend or hibernate " |
||
1189 | "while 3D resources are active.\n"); |
||
1190 | |||
1191 | if (dev_priv->enable_fb) |
||
1192 | vmw_3d_resource_inc(dev_priv, true); |
||
1193 | dev_priv->suspended = false; |
||
1194 | return -EBUSY; |
||
1195 | } |
||
1196 | |||
1197 | return 0; |
||
1198 | } |
||
1199 | |||
4075 | Serge | 1200 | #endif |
1201 | |||
1202 | static struct drm_driver driver = { |
||
1203 | .driver_features = DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | |
||
1204 | DRIVER_MODESET, |
||
4111 | Serge | 1205 | .load = vmw_driver_load, |
4570 | Serge | 1206 | // .unload = vmw_driver_unload, |
1207 | // .lastclose = vmw_lastclose, |
||
4075 | Serge | 1208 | .irq_preinstall = vmw_irq_preinstall, |
1209 | .irq_postinstall = vmw_irq_postinstall, |
||
1210 | // .irq_uninstall = vmw_irq_uninstall, |
||
1211 | .irq_handler = vmw_irq_handler, |
||
1212 | // .get_vblank_counter = vmw_get_vblank_counter, |
||
1213 | // .enable_vblank = vmw_enable_vblank, |
||
1214 | // .disable_vblank = vmw_disable_vblank, |
||
1215 | // .ioctls = vmw_ioctls, |
||
1216 | // .num_ioctls = DRM_ARRAY_SIZE(vmw_ioctls), |
||
1217 | .open = vmw_driver_open, |
||
1218 | // .preclose = vmw_preclose, |
||
1219 | // .postclose = vmw_postclose, |
||
1220 | |||
1221 | // .dumb_create = vmw_dumb_create, |
||
1222 | // .dumb_map_offset = vmw_dumb_map_offset, |
||
1223 | // .dumb_destroy = vmw_dumb_destroy, |
||
1224 | |||
4570 | Serge | 1225 | |
4075 | Serge | 1226 | }; |
1227 | |||
4111 | Serge | 1228 | #if 0 |
1229 | static struct pci_driver vmw_pci_driver = { |
||
1230 | .name = VMWGFX_DRIVER_NAME, |
||
1231 | .id_table = vmw_pci_id_list, |
||
1232 | .probe = vmw_probe, |
||
1233 | .remove = vmw_remove, |
||
1234 | .driver = { |
||
1235 | .pm = &vmw_pm_ops |
||
1236 | } |
||
1237 | }; |
||
4080 | Serge | 1238 | |
4111 | Serge | 1239 | static int vmw_probe(struct pci_dev *pdev, const struct pci_device_id *ent) |
1240 | { |
||
1241 | return drm_get_pci_dev(pdev, ent, &driver); |
||
1242 | } |
||
1243 | #endif |
||
1244 | |||
4080 | Serge | 1245 | int vmw_init(void) |
1246 | { |
||
1247 | static pci_dev_t device; |
||
1248 | const struct pci_device_id *ent; |
||
1249 | int err; |
||
1250 | |||
1251 | ENTER(); |
||
1252 | |||
1253 | ent = find_pci_device(&device, vmw_pci_id_list); |
||
1254 | if( unlikely(ent == NULL) ) |
||
1255 | { |
||
1256 | dbgprintf("device not found\n"); |
||
1257 | return -ENODEV; |
||
1258 | }; |
||
1259 | |||
4111 | Serge | 1260 | drm_core_init(); |
1261 | |||
4080 | Serge | 1262 | DRM_INFO("device %x:%x\n", device.pci_dev.vendor, |
1263 | device.pci_dev.device); |
||
1264 | |||
4111 | Serge | 1265 | err = drm_get_pci_dev(&device.pci_dev, ent, &driver); |
4080 | Serge | 1266 | LEAVE(); |
1267 | |||
1268 | return err; |
||
1269 | } |
||
1270 | |||
1271 | |||
1272 | MODULE_AUTHOR("VMware Inc. and others"); |
||
1273 | MODULE_DESCRIPTION("Standalone drm driver for the VMware SVGA device"); |
||
1274 | MODULE_LICENSE("GPL and additional rights"); |
||
4569 | Serge | 1275 | |
1276 | |||
1277 | void *kmemdup(const void *src, size_t len, gfp_t gfp) |
||
1278 | { |
||
1279 | void *p; |
||
1280 | |||
1281 | p = kmalloc(len, gfp); |
||
1282 | if (p) |
||
1283 | memcpy(p, src, len); |
||
1284 | return p; |
||
1285 | }>>>>>>> |
||
1286 |