Rev 5271 | Details | Compare with Previous | Last modification | View Log | RSS feed
| Rev | Author | Line No. | Line |
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| 5078 | serge | 1 | /* |
| 2 | * Copyright 2013 Advanced Micro Devices, Inc. |
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| 3 | * |
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| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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| 5 | * copy of this software and associated documentation files (the "Software"), |
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| 6 | * to deal in the Software without restriction, including without limitation |
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| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
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| 9 | * Software is furnished to do so, subject to the following conditions: |
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| 10 | * |
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| 11 | * The above copyright notice and this permission notice shall be included in |
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| 12 | * all copies or substantial portions of the Software. |
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| 13 | * |
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| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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| 20 | * OTHER DEALINGS IN THE SOFTWARE. |
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| 21 | * |
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| 22 | * Authors: Christian König |
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| 23 | */ |
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| 24 | |||
| 25 | #include |
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| 26 | #include |
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| 27 | #include "radeon.h" |
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| 28 | #include "radeon_asic.h" |
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| 29 | #include "rv770d.h" |
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| 30 | |||
| 31 | /** |
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| 32 | * uvd_v2_2_fence_emit - emit an fence & trap command |
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| 33 | * |
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| 34 | * @rdev: radeon_device pointer |
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| 35 | * @fence: fence to emit |
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| 36 | * |
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| 37 | * Write a fence and a trap command to the ring. |
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| 38 | */ |
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| 39 | void uvd_v2_2_fence_emit(struct radeon_device *rdev, |
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| 40 | struct radeon_fence *fence) |
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| 41 | { |
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| 42 | struct radeon_ring *ring = &rdev->ring[fence->ring]; |
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| 43 | uint64_t addr = rdev->fence_drv[fence->ring].gpu_addr; |
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| 44 | |||
| 45 | radeon_ring_write(ring, PACKET0(UVD_CONTEXT_ID, 0)); |
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| 46 | radeon_ring_write(ring, fence->seq); |
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| 47 | radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0)); |
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| 48 | radeon_ring_write(ring, lower_32_bits(addr)); |
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| 49 | radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0)); |
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| 50 | radeon_ring_write(ring, upper_32_bits(addr) & 0xff); |
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| 51 | radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_CMD, 0)); |
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| 52 | radeon_ring_write(ring, 0); |
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| 53 | |||
| 54 | radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0)); |
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| 55 | radeon_ring_write(ring, 0); |
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| 56 | radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0)); |
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| 57 | radeon_ring_write(ring, 0); |
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| 58 | radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_CMD, 0)); |
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| 59 | radeon_ring_write(ring, 2); |
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| 60 | } |
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| 61 | |||
| 62 | /** |
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| 6104 | serge | 63 | * uvd_v2_2_semaphore_emit - emit semaphore command |
| 64 | * |
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| 65 | * @rdev: radeon_device pointer |
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| 66 | * @ring: radeon_ring pointer |
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| 67 | * @semaphore: semaphore to emit commands for |
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| 68 | * @emit_wait: true if we should emit a wait command |
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| 69 | * |
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| 70 | * Emit a semaphore command (either wait or signal) to the UVD ring. |
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| 71 | */ |
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| 72 | bool uvd_v2_2_semaphore_emit(struct radeon_device *rdev, |
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| 73 | struct radeon_ring *ring, |
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| 74 | struct radeon_semaphore *semaphore, |
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| 75 | bool emit_wait) |
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| 76 | { |
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| 77 | uint64_t addr = semaphore->gpu_addr; |
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| 78 | |||
| 79 | radeon_ring_write(ring, PACKET0(UVD_SEMA_ADDR_LOW, 0)); |
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| 80 | radeon_ring_write(ring, (addr >> 3) & 0x000FFFFF); |
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| 81 | |||
| 82 | radeon_ring_write(ring, PACKET0(UVD_SEMA_ADDR_HIGH, 0)); |
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| 83 | radeon_ring_write(ring, (addr >> 23) & 0x000FFFFF); |
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| 84 | |||
| 85 | radeon_ring_write(ring, PACKET0(UVD_SEMA_CMD, 0)); |
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| 86 | radeon_ring_write(ring, emit_wait ? 1 : 0); |
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| 87 | |||
| 88 | return true; |
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| 89 | } |
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| 90 | |||
| 91 | /** |
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| 5078 | serge | 92 | * uvd_v2_2_resume - memory controller programming |
| 93 | * |
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| 94 | * @rdev: radeon_device pointer |
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| 95 | * |
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| 96 | * Let the UVD memory controller know it's offsets |
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| 97 | */ |
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| 98 | int uvd_v2_2_resume(struct radeon_device *rdev) |
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| 99 | { |
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| 100 | uint64_t addr; |
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| 101 | uint32_t chip_id, size; |
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| 102 | int r; |
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| 103 | |||
| 5271 | serge | 104 | /* RV770 uses V1.0 MC */ |
| 105 | if (rdev->family == CHIP_RV770) |
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| 106 | return uvd_v1_0_resume(rdev); |
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| 107 | |||
| 5078 | serge | 108 | r = radeon_uvd_resume(rdev); |
| 109 | if (r) |
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| 110 | return r; |
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| 111 | |||
| 112 | /* programm the VCPU memory controller bits 0-27 */ |
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| 113 | addr = rdev->uvd.gpu_addr >> 3; |
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| 114 | size = RADEON_GPU_PAGE_ALIGN(rdev->uvd_fw->size + 4) >> 3; |
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| 115 | WREG32(UVD_VCPU_CACHE_OFFSET0, addr); |
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| 116 | WREG32(UVD_VCPU_CACHE_SIZE0, size); |
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| 117 | |||
| 118 | addr += size; |
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| 119 | size = RADEON_UVD_STACK_SIZE >> 3; |
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| 120 | WREG32(UVD_VCPU_CACHE_OFFSET1, addr); |
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| 121 | WREG32(UVD_VCPU_CACHE_SIZE1, size); |
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| 122 | |||
| 123 | addr += size; |
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| 124 | size = RADEON_UVD_HEAP_SIZE >> 3; |
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| 125 | WREG32(UVD_VCPU_CACHE_OFFSET2, addr); |
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| 126 | WREG32(UVD_VCPU_CACHE_SIZE2, size); |
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| 127 | |||
| 128 | /* bits 28-31 */ |
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| 129 | addr = (rdev->uvd.gpu_addr >> 28) & 0xF; |
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| 130 | WREG32(UVD_LMI_ADDR_EXT, (addr << 12) | (addr << 0)); |
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| 131 | |||
| 132 | /* bits 32-39 */ |
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| 133 | addr = (rdev->uvd.gpu_addr >> 32) & 0xFF; |
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| 134 | WREG32(UVD_LMI_EXT40_ADDR, addr | (0x9 << 16) | (0x1 << 31)); |
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| 135 | |||
| 136 | /* tell firmware which hardware it is running on */ |
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| 137 | switch (rdev->family) { |
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| 138 | default: |
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| 139 | return -EINVAL; |
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| 140 | case CHIP_RV710: |
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| 141 | chip_id = 0x01000005; |
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| 142 | break; |
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| 143 | case CHIP_RV730: |
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| 144 | chip_id = 0x01000006; |
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| 145 | break; |
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| 146 | case CHIP_RV740: |
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| 147 | chip_id = 0x01000007; |
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| 148 | break; |
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| 149 | case CHIP_CYPRESS: |
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| 150 | case CHIP_HEMLOCK: |
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| 151 | chip_id = 0x01000008; |
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| 152 | break; |
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| 153 | case CHIP_JUNIPER: |
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| 154 | chip_id = 0x01000009; |
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| 155 | break; |
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| 156 | case CHIP_REDWOOD: |
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| 157 | chip_id = 0x0100000a; |
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| 158 | break; |
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| 159 | case CHIP_CEDAR: |
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| 160 | chip_id = 0x0100000b; |
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| 161 | break; |
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| 162 | case CHIP_SUMO: |
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| 163 | case CHIP_SUMO2: |
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| 164 | chip_id = 0x0100000c; |
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| 165 | break; |
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| 166 | case CHIP_PALM: |
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| 167 | chip_id = 0x0100000e; |
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| 168 | break; |
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| 169 | case CHIP_CAYMAN: |
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| 170 | chip_id = 0x0100000f; |
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| 171 | break; |
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| 172 | case CHIP_BARTS: |
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| 173 | chip_id = 0x01000010; |
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| 174 | break; |
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| 175 | case CHIP_TURKS: |
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| 176 | chip_id = 0x01000011; |
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| 177 | break; |
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| 178 | case CHIP_CAICOS: |
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| 179 | chip_id = 0x01000012; |
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| 180 | break; |
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| 181 | case CHIP_TAHITI: |
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| 182 | chip_id = 0x01000014; |
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| 183 | break; |
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| 184 | case CHIP_VERDE: |
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| 185 | chip_id = 0x01000015; |
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| 186 | break; |
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| 187 | case CHIP_PITCAIRN: |
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| 188 | case CHIP_OLAND: |
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| 189 | chip_id = 0x01000016; |
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| 190 | break; |
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| 191 | case CHIP_ARUBA: |
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| 192 | chip_id = 0x01000017; |
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| 193 | break; |
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| 194 | } |
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| 195 | WREG32(UVD_VCPU_CHIP_ID, chip_id); |
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| 196 | |||
| 197 | return 0; |
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| 198 | } |