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| Rev | Author | Line No. | Line |
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| 5078 | serge | 1 | /* |
| 2 | * Copyright 2012 Advanced Micro Devices, Inc. |
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| 3 | * |
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| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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| 5 | * copy of this software and associated documentation files (the "Software"), |
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| 6 | * to deal in the Software without restriction, including without limitation |
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| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
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| 9 | * Software is furnished to do so, subject to the following conditions: |
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| 10 | * |
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| 11 | * The above copyright notice and this permission notice shall be included in |
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| 12 | * all copies or substantial portions of the Software. |
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| 13 | * |
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| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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| 20 | * OTHER DEALINGS IN THE SOFTWARE. |
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| 21 | * |
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| 22 | * Authors: Alex Deucher |
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| 23 | */ |
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| 24 | #ifndef _TRINITYD_H_ |
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| 25 | #define _TRINITYD_H_ |
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| 26 | |||
| 27 | /* pm registers */ |
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| 28 | |||
| 29 | /* cg */ |
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| 30 | #define CG_CGTT_LOCAL_0 0x0 |
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| 31 | #define CG_CGTT_LOCAL_1 0x1 |
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| 32 | |||
| 33 | /* smc */ |
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| 34 | #define SMU_SCLK_DPM_STATE_0_CNTL_0 0x1f000 |
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| 35 | # define STATE_VALID(x) ((x) << 0) |
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| 36 | # define STATE_VALID_MASK (0xff << 0) |
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| 37 | # define STATE_VALID_SHIFT 0 |
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| 38 | # define CLK_DIVIDER(x) ((x) << 8) |
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| 39 | # define CLK_DIVIDER_MASK (0xff << 8) |
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| 40 | # define CLK_DIVIDER_SHIFT 8 |
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| 41 | # define VID(x) ((x) << 16) |
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| 42 | # define VID_MASK (0xff << 16) |
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| 43 | # define VID_SHIFT 16 |
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| 44 | # define LVRT(x) ((x) << 24) |
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| 45 | # define LVRT_MASK (0xff << 24) |
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| 46 | # define LVRT_SHIFT 24 |
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| 47 | #define SMU_SCLK_DPM_STATE_0_CNTL_1 0x1f004 |
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| 48 | # define DS_DIV(x) ((x) << 0) |
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| 49 | # define DS_DIV_MASK (0xff << 0) |
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| 50 | # define DS_DIV_SHIFT 0 |
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| 51 | # define DS_SH_DIV(x) ((x) << 8) |
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| 52 | # define DS_SH_DIV_MASK (0xff << 8) |
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| 53 | # define DS_SH_DIV_SHIFT 8 |
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| 54 | # define DISPLAY_WM(x) ((x) << 16) |
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| 55 | # define DISPLAY_WM_MASK (0xff << 16) |
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| 56 | # define DISPLAY_WM_SHIFT 16 |
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| 57 | # define VCE_WM(x) ((x) << 24) |
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| 58 | # define VCE_WM_MASK (0xff << 24) |
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| 59 | # define VCE_WM_SHIFT 24 |
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| 60 | |||
| 61 | #define SMU_SCLK_DPM_STATE_0_CNTL_3 0x1f00c |
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| 62 | # define GNB_SLOW(x) ((x) << 0) |
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| 63 | # define GNB_SLOW_MASK (0xff << 0) |
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| 64 | # define GNB_SLOW_SHIFT 0 |
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| 65 | # define FORCE_NBPS1(x) ((x) << 8) |
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| 66 | # define FORCE_NBPS1_MASK (0xff << 8) |
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| 67 | # define FORCE_NBPS1_SHIFT 8 |
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| 68 | #define SMU_SCLK_DPM_STATE_0_AT 0x1f010 |
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| 69 | # define AT(x) ((x) << 0) |
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| 70 | # define AT_MASK (0xff << 0) |
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| 71 | # define AT_SHIFT 0 |
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| 72 | |||
| 73 | #define SMU_SCLK_DPM_STATE_0_PG_CNTL 0x1f014 |
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| 74 | # define PD_SCLK_DIVIDER(x) ((x) << 16) |
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| 75 | # define PD_SCLK_DIVIDER_MASK (0xff << 16) |
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| 76 | # define PD_SCLK_DIVIDER_SHIFT 16 |
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| 77 | |||
| 78 | #define SMU_SCLK_DPM_STATE_1_CNTL_0 0x1f020 |
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| 79 | |||
| 80 | #define SMU_SCLK_DPM_CNTL 0x1f100 |
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| 81 | # define SCLK_DPM_EN(x) ((x) << 0) |
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| 82 | # define SCLK_DPM_EN_MASK (0xff << 0) |
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| 83 | # define SCLK_DPM_EN_SHIFT 0 |
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| 84 | # define SCLK_DPM_BOOT_STATE(x) ((x) << 16) |
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| 85 | # define SCLK_DPM_BOOT_STATE_MASK (0xff << 16) |
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| 86 | # define SCLK_DPM_BOOT_STATE_SHIFT 16 |
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| 87 | # define VOLTAGE_CHG_EN(x) ((x) << 24) |
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| 88 | # define VOLTAGE_CHG_EN_MASK (0xff << 24) |
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| 89 | # define VOLTAGE_CHG_EN_SHIFT 24 |
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| 90 | |||
| 91 | #define SMU_SCLK_DPM_TT_CNTL 0x1f108 |
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| 92 | # define SCLK_TT_EN(x) ((x) << 0) |
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| 93 | # define SCLK_TT_EN_MASK (0xff << 0) |
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| 94 | # define SCLK_TT_EN_SHIFT 0 |
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| 95 | #define SMU_SCLK_DPM_TTT 0x1f10c |
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| 96 | # define LT(x) ((x) << 0) |
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| 97 | # define LT_MASK (0xffff << 0) |
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| 98 | # define LT_SHIFT 0 |
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| 99 | # define HT(x) ((x) << 16) |
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| 100 | # define HT_MASK (0xffff << 16) |
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| 101 | # define HT_SHIFT 16 |
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| 102 | |||
| 103 | #define SMU_UVD_DPM_STATES 0x1f1a0 |
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| 104 | #define SMU_UVD_DPM_CNTL 0x1f1a4 |
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| 105 | |||
| 106 | #define SMU_S_PG_CNTL 0x1f118 |
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| 107 | # define DS_PG_EN(x) ((x) << 16) |
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| 108 | # define DS_PG_EN_MASK (0xff << 16) |
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| 109 | # define DS_PG_EN_SHIFT 16 |
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| 110 | |||
| 111 | #define GFX_POWER_GATING_CNTL 0x1f38c |
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| 112 | # define PDS_DIV(x) ((x) << 0) |
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| 113 | # define PDS_DIV_MASK (0xff << 0) |
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| 114 | # define PDS_DIV_SHIFT 0 |
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| 115 | # define SSSD(x) ((x) << 8) |
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| 116 | # define SSSD_MASK (0xff << 8) |
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| 117 | # define SSSD_SHIFT 8 |
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| 118 | |||
| 119 | #define PM_CONFIG 0x1f428 |
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| 120 | # define SVI_Mode (1 << 29) |
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| 121 | |||
| 122 | #define PM_I_CNTL_1 0x1f464 |
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| 123 | # define SCLK_DPM(x) ((x) << 0) |
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| 124 | # define SCLK_DPM_MASK (0xff << 0) |
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| 125 | # define SCLK_DPM_SHIFT 0 |
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| 126 | # define DS_PG_CNTL(x) ((x) << 16) |
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| 127 | # define DS_PG_CNTL_MASK (0xff << 16) |
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| 128 | # define DS_PG_CNTL_SHIFT 16 |
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| 129 | #define PM_TP 0x1f468 |
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| 130 | |||
| 131 | #define NB_PSTATE_CONFIG 0x1f5f8 |
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| 132 | # define Dpm0PgNbPsLo(x) ((x) << 0) |
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| 133 | # define Dpm0PgNbPsLo_MASK (3 << 0) |
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| 134 | # define Dpm0PgNbPsLo_SHIFT 0 |
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| 135 | # define Dpm0PgNbPsHi(x) ((x) << 2) |
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| 136 | # define Dpm0PgNbPsHi_MASK (3 << 2) |
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| 137 | # define Dpm0PgNbPsHi_SHIFT 2 |
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| 138 | # define DpmXNbPsLo(x) ((x) << 4) |
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| 139 | # define DpmXNbPsLo_MASK (3 << 4) |
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| 140 | # define DpmXNbPsLo_SHIFT 4 |
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| 141 | # define DpmXNbPsHi(x) ((x) << 6) |
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| 142 | # define DpmXNbPsHi_MASK (3 << 6) |
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| 143 | # define DpmXNbPsHi_SHIFT 6 |
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| 144 | |||
| 145 | #define DC_CAC_VALUE 0x1f908 |
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| 146 | |||
| 147 | #define GPU_CAC_AVRG_CNTL 0x1f920 |
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| 148 | # define WINDOW_SIZE(x) ((x) << 0) |
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| 149 | # define WINDOW_SIZE_MASK (0xff << 0) |
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| 150 | # define WINDOW_SIZE_SHIFT 0 |
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| 151 | |||
| 152 | #define CC_SMU_MISC_FUSES 0xe0001004 |
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| 153 | # define MinSClkDid(x) ((x) << 2) |
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| 154 | # define MinSClkDid_MASK (0x7f << 2) |
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| 155 | # define MinSClkDid_SHIFT 2 |
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| 156 | |||
| 157 | #define CC_SMU_TST_EFUSE1_MISC 0xe000101c |
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| 158 | # define RB_BACKEND_DISABLE(x) ((x) << 16) |
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| 159 | # define RB_BACKEND_DISABLE_MASK (3 << 16) |
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| 160 | # define RB_BACKEND_DISABLE_SHIFT 16 |
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| 161 | |||
| 162 | #define SMU_SCRATCH_A 0xe0003024 |
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| 163 | |||
| 164 | #define SMU_SCRATCH0 0xe0003040 |
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| 165 | |||
| 166 | /* mmio */ |
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| 167 | #define SMC_INT_REQ 0x220 |
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| 168 | |||
| 169 | #define SMC_MESSAGE_0 0x22c |
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| 170 | #define SMC_RESP_0 0x230 |
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| 171 | |||
| 172 | #define GENERAL_PWRMGT 0x670 |
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| 173 | # define GLOBAL_PWRMGT_EN (1 << 0) |
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| 174 | |||
| 175 | #define SCLK_PWRMGT_CNTL 0x678 |
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| 176 | # define DYN_PWR_DOWN_EN (1 << 2) |
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| 177 | # define RESET_BUSY_CNT (1 << 4) |
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| 178 | # define RESET_SCLK_CNT (1 << 5) |
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| 179 | # define DYN_GFX_CLK_OFF_EN (1 << 7) |
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| 180 | # define GFX_CLK_FORCE_ON (1 << 8) |
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| 181 | # define DYNAMIC_PM_EN (1 << 21) |
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| 182 | |||
| 183 | #define TARGET_AND_CURRENT_PROFILE_INDEX 0x684 |
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| 184 | # define TARGET_STATE(x) ((x) << 0) |
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| 185 | # define TARGET_STATE_MASK (0xf << 0) |
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| 186 | # define TARGET_STATE_SHIFT 0 |
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| 187 | # define CURRENT_STATE(x) ((x) << 4) |
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| 188 | # define CURRENT_STATE_MASK (0xf << 4) |
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| 189 | # define CURRENT_STATE_SHIFT 4 |
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| 190 | |||
| 191 | #define CG_GIPOTS 0x6d8 |
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| 192 | # define CG_GIPOT(x) ((x) << 16) |
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| 193 | # define CG_GIPOT_MASK (0xffff << 16) |
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| 194 | # define CG_GIPOT_SHIFT 16 |
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| 195 | |||
| 196 | #define CG_PG_CTRL 0x6e0 |
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| 197 | # define SP(x) ((x) << 0) |
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| 198 | # define SP_MASK (0xffff << 0) |
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| 199 | # define SP_SHIFT 0 |
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| 200 | # define SU(x) ((x) << 16) |
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| 201 | # define SU_MASK (0xffff << 16) |
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| 202 | # define SU_SHIFT 16 |
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| 203 | |||
| 204 | #define CG_MISC_REG 0x708 |
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| 205 | |||
| 206 | #define CG_THERMAL_INT_CTRL 0x738 |
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| 207 | # define DIG_THERM_INTH(x) ((x) << 0) |
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| 208 | # define DIG_THERM_INTH_MASK (0xff << 0) |
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| 209 | # define DIG_THERM_INTH_SHIFT 0 |
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| 210 | # define DIG_THERM_INTL(x) ((x) << 8) |
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| 211 | # define DIG_THERM_INTL_MASK (0xff << 8) |
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| 212 | # define DIG_THERM_INTL_SHIFT 8 |
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| 213 | # define THERM_INTH_MASK (1 << 24) |
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| 214 | # define THERM_INTL_MASK (1 << 25) |
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| 215 | |||
| 216 | #define CG_CG_VOLTAGE_CNTL 0x770 |
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| 217 | # define EN (1 << 9) |
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| 218 | |||
| 219 | #define HW_REV 0x5564 |
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| 220 | # define ATI_REV_ID_MASK (0xf << 28) |
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| 221 | # define ATI_REV_ID_SHIFT 28 |
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| 222 | /* 0 = A0, 1 = A1, 2 = B0, 3 = C0, etc. */ |
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| 223 | |||
| 224 | #define CGTS_SM_CTRL_REG 0x9150 |
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| 225 | |||
| 226 | #define GB_ADDR_CONFIG 0x98f8 |
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| 227 | |||
| 228 | #endif |