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Rev | Author | Line No. | Line |
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5078 | serge | 1 | /* |
2 | * Copyright 2012 Advanced Micro Devices, Inc. |
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3 | * |
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4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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5 | * copy of this software and associated documentation files (the "Software"), |
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6 | * to deal in the Software without restriction, including without limitation |
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7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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8 | * and/or sell copies of the Software, and to permit persons to whom the |
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9 | * Software is furnished to do so, subject to the following conditions: |
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10 | * |
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11 | * The above copyright notice and this permission notice shall be included in |
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12 | * all copies or substantial portions of the Software. |
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13 | * |
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14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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20 | * OTHER DEALINGS IN THE SOFTWARE. |
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21 | * |
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22 | */ |
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23 | |||
24 | #include "drmP.h" |
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25 | #include "radeon.h" |
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26 | #include "sumod.h" |
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27 | #include "sumo_dpm.h" |
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28 | #include "ppsmc.h" |
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29 | |||
30 | #define SUMO_SMU_SERVICE_ROUTINE_PG_INIT 1 |
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31 | #define SUMO_SMU_SERVICE_ROUTINE_ALTVDDNB_NOTIFY 27 |
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32 | #define SUMO_SMU_SERVICE_ROUTINE_GFX_SRV_ID_20 20 |
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33 | |||
34 | struct sumo_power_info *sumo_get_pi(struct radeon_device *rdev); |
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35 | |||
36 | static void sumo_send_msg_to_smu(struct radeon_device *rdev, u32 id) |
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37 | { |
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38 | u32 gfx_int_req; |
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39 | int i; |
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40 | |||
41 | for (i = 0; i < rdev->usec_timeout; i++) { |
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42 | if (RREG32(GFX_INT_STATUS) & INT_DONE) |
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43 | break; |
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44 | udelay(1); |
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45 | } |
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46 | |||
47 | gfx_int_req = SERV_INDEX(id) | INT_REQ; |
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48 | WREG32(GFX_INT_REQ, gfx_int_req); |
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49 | |||
50 | for (i = 0; i < rdev->usec_timeout; i++) { |
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51 | if (RREG32(GFX_INT_REQ) & INT_REQ) |
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52 | break; |
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53 | udelay(1); |
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54 | } |
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55 | |||
56 | for (i = 0; i < rdev->usec_timeout; i++) { |
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57 | if (RREG32(GFX_INT_STATUS) & INT_ACK) |
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58 | break; |
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59 | udelay(1); |
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60 | } |
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61 | |||
62 | for (i = 0; i < rdev->usec_timeout; i++) { |
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63 | if (RREG32(GFX_INT_STATUS) & INT_DONE) |
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64 | break; |
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65 | udelay(1); |
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66 | } |
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67 | |||
68 | gfx_int_req &= ~INT_REQ; |
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69 | WREG32(GFX_INT_REQ, gfx_int_req); |
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70 | } |
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71 | |||
72 | void sumo_initialize_m3_arb(struct radeon_device *rdev) |
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73 | { |
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74 | struct sumo_power_info *pi = sumo_get_pi(rdev); |
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75 | u32 i; |
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76 | |||
77 | if (!pi->enable_dynamic_m3_arbiter) |
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78 | return; |
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79 | |||
80 | for (i = 0; i < NUMBER_OF_M3ARB_PARAM_SETS; i++) |
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81 | WREG32_RCU(MCU_M3ARB_PARAMS + (i * 4), |
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82 | pi->sys_info.csr_m3_arb_cntl_default[i]); |
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83 | |||
84 | for (; i < NUMBER_OF_M3ARB_PARAM_SETS * 2; i++) |
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85 | WREG32_RCU(MCU_M3ARB_PARAMS + (i * 4), |
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86 | pi->sys_info.csr_m3_arb_cntl_uvd[i % NUMBER_OF_M3ARB_PARAM_SETS]); |
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87 | |||
88 | for (; i < NUMBER_OF_M3ARB_PARAM_SETS * 3; i++) |
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89 | WREG32_RCU(MCU_M3ARB_PARAMS + (i * 4), |
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90 | pi->sys_info.csr_m3_arb_cntl_fs3d[i % NUMBER_OF_M3ARB_PARAM_SETS]); |
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91 | } |
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92 | |||
93 | static bool sumo_is_alt_vddnb_supported(struct radeon_device *rdev) |
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94 | { |
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95 | struct sumo_power_info *pi = sumo_get_pi(rdev); |
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96 | bool return_code = false; |
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97 | |||
98 | if (!pi->enable_alt_vddnb) |
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99 | return return_code; |
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100 | |||
101 | if ((rdev->family == CHIP_SUMO) || (rdev->family == CHIP_SUMO2)) { |
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102 | if (pi->fw_version >= 0x00010C00) |
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103 | return_code = true; |
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104 | } |
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105 | |||
106 | return return_code; |
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107 | } |
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108 | |||
109 | void sumo_smu_notify_alt_vddnb_change(struct radeon_device *rdev, |
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110 | bool powersaving, bool force_nbps1) |
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111 | { |
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112 | u32 param = 0; |
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113 | |||
114 | if (!sumo_is_alt_vddnb_supported(rdev)) |
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115 | return; |
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116 | |||
117 | if (powersaving) |
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118 | param |= 1; |
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119 | |||
120 | if (force_nbps1) |
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121 | param |= 2; |
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122 | |||
123 | WREG32_RCU(RCU_ALTVDDNB_NOTIFY, param); |
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124 | |||
125 | sumo_send_msg_to_smu(rdev, SUMO_SMU_SERVICE_ROUTINE_ALTVDDNB_NOTIFY); |
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126 | } |
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127 | |||
128 | void sumo_smu_pg_init(struct radeon_device *rdev) |
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129 | { |
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130 | sumo_send_msg_to_smu(rdev, SUMO_SMU_SERVICE_ROUTINE_PG_INIT); |
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131 | } |
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132 | |||
133 | static u32 sumo_power_of_4(u32 unit) |
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134 | { |
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135 | u32 ret = 1; |
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136 | u32 i; |
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137 | |||
138 | for (i = 0; i < unit; i++) |
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139 | ret *= 4; |
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140 | |||
141 | return ret; |
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142 | } |
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143 | |||
144 | void sumo_enable_boost_timer(struct radeon_device *rdev) |
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145 | { |
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146 | struct sumo_power_info *pi = sumo_get_pi(rdev); |
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147 | u32 period, unit, timer_value; |
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148 | u32 xclk = radeon_get_xclk(rdev); |
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149 | |||
150 | unit = (RREG32_RCU(RCU_LCLK_SCALING_CNTL) & LCLK_SCALING_TIMER_PRESCALER_MASK) |
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151 | >> LCLK_SCALING_TIMER_PRESCALER_SHIFT; |
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152 | |||
153 | period = 100 * (xclk / 100 / sumo_power_of_4(unit)); |
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154 | |||
155 | timer_value = (period << 16) | (unit << 4); |
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156 | |||
157 | WREG32_RCU(RCU_GNB_PWR_REP_TIMER_CNTL, timer_value); |
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158 | WREG32_RCU(RCU_BOOST_MARGIN, pi->sys_info.sclk_dpm_boost_margin); |
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159 | WREG32_RCU(RCU_THROTTLE_MARGIN, pi->sys_info.sclk_dpm_throttle_margin); |
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160 | WREG32_RCU(GNB_TDP_LIMIT, pi->sys_info.gnb_tdp_limit); |
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161 | WREG32_RCU(RCU_SclkDpmTdpLimitPG, pi->sys_info.sclk_dpm_tdp_limit_pg); |
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162 | |||
163 | sumo_send_msg_to_smu(rdev, SUMO_SMU_SERVICE_ROUTINE_GFX_SRV_ID_20); |
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164 | } |
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165 | |||
166 | void sumo_set_tdp_limit(struct radeon_device *rdev, u32 index, u32 tdp_limit) |
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167 | { |
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168 | u32 regoffset = 0; |
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169 | u32 shift = 0; |
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170 | u32 mask = 0xFFF; |
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171 | u32 sclk_dpm_tdp_limit; |
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172 | |||
173 | switch (index) { |
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174 | case 0: |
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175 | regoffset = RCU_SclkDpmTdpLimit01; |
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176 | shift = 16; |
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177 | break; |
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178 | case 1: |
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179 | regoffset = RCU_SclkDpmTdpLimit01; |
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180 | shift = 0; |
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181 | break; |
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182 | case 2: |
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183 | regoffset = RCU_SclkDpmTdpLimit23; |
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184 | shift = 16; |
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185 | break; |
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186 | case 3: |
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187 | regoffset = RCU_SclkDpmTdpLimit23; |
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188 | shift = 0; |
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189 | break; |
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190 | case 4: |
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191 | regoffset = RCU_SclkDpmTdpLimit47; |
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192 | shift = 16; |
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193 | break; |
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194 | case 7: |
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195 | regoffset = RCU_SclkDpmTdpLimit47; |
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196 | shift = 0; |
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197 | break; |
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198 | default: |
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199 | break; |
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200 | } |
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201 | |||
202 | sclk_dpm_tdp_limit = RREG32_RCU(regoffset); |
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203 | sclk_dpm_tdp_limit &= ~(mask << shift); |
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204 | sclk_dpm_tdp_limit |= (tdp_limit << shift); |
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205 | WREG32_RCU(regoffset, sclk_dpm_tdp_limit); |
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206 | } |
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207 | |||
208 | void sumo_boost_state_enable(struct radeon_device *rdev, bool enable) |
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209 | { |
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210 | u32 boost_disable = RREG32_RCU(RCU_GPU_BOOST_DISABLE); |
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211 | |||
212 | boost_disable &= 0xFFFFFFFE; |
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213 | boost_disable |= (enable ? 0 : 1); |
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214 | WREG32_RCU(RCU_GPU_BOOST_DISABLE, boost_disable); |
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215 | } |
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216 | |||
217 | u32 sumo_get_running_fw_version(struct radeon_device *rdev) |
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218 | { |
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219 | return RREG32_RCU(RCU_FW_VERSION); |
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220 | }><>><>><>><>>>>>>>>> |
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221 |