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5078 | serge | 1 | /* |
2 | * Copyright 2013 Advanced Micro Devices, Inc. |
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3 | * |
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4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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5 | * copy of this software and associated documentation files (the "Software"), |
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6 | * to deal in the Software without restriction, including without limitation |
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7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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8 | * and/or sell copies of the Software, and to permit persons to whom the |
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9 | * Software is furnished to do so, subject to the following conditions: |
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10 | * |
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11 | * The above copyright notice and this permission notice shall be included in |
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12 | * all copies or substantial portions of the Software. |
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13 | * |
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14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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20 | * OTHER DEALINGS IN THE SOFTWARE. |
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21 | * |
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22 | */ |
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23 | |||
24 | #ifndef SMU7_FUSION_H |
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25 | #define SMU7_FUSION_H |
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26 | |||
27 | #include "smu7.h" |
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28 | |||
29 | #pragma pack(push, 1) |
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30 | |||
31 | #define SMU7_DTE_ITERATIONS 5 |
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32 | #define SMU7_DTE_SOURCES 5 |
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33 | #define SMU7_DTE_SINKS 3 |
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34 | #define SMU7_NUM_CPU_TES 2 |
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35 | #define SMU7_NUM_GPU_TES 1 |
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36 | #define SMU7_NUM_NON_TES 2 |
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37 | |||
38 | // All 'soft registers' should be uint32_t. |
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39 | struct SMU7_SoftRegisters |
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40 | { |
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41 | uint32_t RefClockFrequency; |
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42 | uint32_t PmTimerP; |
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43 | uint32_t FeatureEnables; |
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44 | uint32_t HandshakeDisables; |
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45 | |||
46 | uint8_t DisplayPhy1Config; |
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47 | uint8_t DisplayPhy2Config; |
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48 | uint8_t DisplayPhy3Config; |
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49 | uint8_t DisplayPhy4Config; |
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50 | |||
51 | uint8_t DisplayPhy5Config; |
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52 | uint8_t DisplayPhy6Config; |
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53 | uint8_t DisplayPhy7Config; |
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54 | uint8_t DisplayPhy8Config; |
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55 | |||
56 | uint32_t AverageGraphicsA; |
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57 | uint32_t AverageMemoryA; |
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58 | uint32_t AverageGioA; |
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59 | |||
60 | uint8_t SClkDpmEnabledLevels; |
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61 | uint8_t MClkDpmEnabledLevels; |
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62 | uint8_t LClkDpmEnabledLevels; |
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63 | uint8_t PCIeDpmEnabledLevels; |
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64 | |||
65 | uint8_t UVDDpmEnabledLevels; |
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66 | uint8_t SAMUDpmEnabledLevels; |
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67 | uint8_t ACPDpmEnabledLevels; |
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68 | uint8_t VCEDpmEnabledLevels; |
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69 | |||
70 | uint32_t DRAM_LOG_ADDR_H; |
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71 | uint32_t DRAM_LOG_ADDR_L; |
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72 | uint32_t DRAM_LOG_PHY_ADDR_H; |
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73 | uint32_t DRAM_LOG_PHY_ADDR_L; |
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74 | uint32_t DRAM_LOG_BUFF_SIZE; |
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75 | uint32_t UlvEnterC; |
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76 | uint32_t UlvTime; |
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77 | uint32_t Reserved[3]; |
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78 | |||
79 | }; |
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80 | |||
81 | typedef struct SMU7_SoftRegisters SMU7_SoftRegisters; |
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82 | |||
83 | struct SMU7_Fusion_GraphicsLevel |
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84 | { |
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85 | uint32_t MinVddNb; |
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86 | |||
87 | uint32_t SclkFrequency; |
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88 | |||
89 | uint8_t Vid; |
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90 | uint8_t VidOffset; |
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91 | uint16_t AT; |
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92 | |||
93 | uint8_t PowerThrottle; |
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94 | uint8_t GnbSlow; |
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95 | uint8_t ForceNbPs1; |
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96 | uint8_t SclkDid; |
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97 | |||
98 | uint8_t DisplayWatermark; |
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99 | uint8_t EnabledForActivity; |
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100 | uint8_t EnabledForThrottle; |
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101 | uint8_t UpH; |
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102 | |||
103 | uint8_t DownH; |
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104 | uint8_t VoltageDownH; |
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105 | uint8_t DeepSleepDivId; |
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106 | |||
107 | uint8_t ClkBypassCntl; |
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108 | |||
109 | uint32_t reserved; |
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110 | }; |
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111 | |||
112 | typedef struct SMU7_Fusion_GraphicsLevel SMU7_Fusion_GraphicsLevel; |
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113 | |||
114 | struct SMU7_Fusion_GIOLevel |
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115 | { |
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116 | uint8_t EnabledForActivity; |
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117 | uint8_t LclkDid; |
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118 | uint8_t Vid; |
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119 | uint8_t VoltageDownH; |
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120 | |||
121 | uint32_t MinVddNb; |
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122 | |||
123 | uint16_t ResidencyCounter; |
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124 | uint8_t UpH; |
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125 | uint8_t DownH; |
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126 | |||
127 | uint32_t LclkFrequency; |
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128 | |||
129 | uint8_t ActivityLevel; |
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130 | uint8_t EnabledForThrottle; |
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131 | |||
132 | uint8_t ClkBypassCntl; |
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133 | |||
134 | uint8_t padding; |
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135 | }; |
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136 | |||
137 | typedef struct SMU7_Fusion_GIOLevel SMU7_Fusion_GIOLevel; |
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138 | |||
139 | // UVD VCLK/DCLK state (level) definition. |
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140 | struct SMU7_Fusion_UvdLevel |
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141 | { |
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142 | uint32_t VclkFrequency; |
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143 | uint32_t DclkFrequency; |
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144 | uint16_t MinVddNb; |
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145 | uint8_t VclkDivider; |
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146 | uint8_t DclkDivider; |
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147 | |||
148 | uint8_t VClkBypassCntl; |
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149 | uint8_t DClkBypassCntl; |
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150 | |||
151 | uint8_t padding[2]; |
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152 | |||
153 | }; |
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154 | |||
155 | typedef struct SMU7_Fusion_UvdLevel SMU7_Fusion_UvdLevel; |
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156 | |||
157 | // Clocks for other external blocks (VCE, ACP, SAMU). |
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158 | struct SMU7_Fusion_ExtClkLevel |
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159 | { |
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160 | uint32_t Frequency; |
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161 | uint16_t MinVoltage; |
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162 | uint8_t Divider; |
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163 | uint8_t ClkBypassCntl; |
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164 | |||
165 | uint32_t Reserved; |
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166 | }; |
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167 | typedef struct SMU7_Fusion_ExtClkLevel SMU7_Fusion_ExtClkLevel; |
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168 | |||
169 | struct SMU7_Fusion_ACPILevel |
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170 | { |
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171 | uint32_t Flags; |
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172 | uint32_t MinVddNb; |
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173 | uint32_t SclkFrequency; |
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174 | uint8_t SclkDid; |
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175 | uint8_t GnbSlow; |
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176 | uint8_t ForceNbPs1; |
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177 | uint8_t DisplayWatermark; |
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178 | uint8_t DeepSleepDivId; |
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179 | uint8_t padding[3]; |
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180 | }; |
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181 | |||
182 | typedef struct SMU7_Fusion_ACPILevel SMU7_Fusion_ACPILevel; |
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183 | |||
184 | struct SMU7_Fusion_NbDpm |
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185 | { |
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186 | uint8_t DpmXNbPsHi; |
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187 | uint8_t DpmXNbPsLo; |
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188 | uint8_t Dpm0PgNbPsHi; |
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189 | uint8_t Dpm0PgNbPsLo; |
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190 | uint8_t EnablePsi1; |
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191 | uint8_t SkipDPM0; |
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192 | uint8_t SkipPG; |
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193 | uint8_t Hysteresis; |
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194 | uint8_t EnableDpmPstatePoll; |
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195 | uint8_t padding[3]; |
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196 | }; |
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197 | |||
198 | typedef struct SMU7_Fusion_NbDpm SMU7_Fusion_NbDpm; |
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199 | |||
200 | struct SMU7_Fusion_StateInfo |
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201 | { |
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202 | uint32_t SclkFrequency; |
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203 | uint32_t LclkFrequency; |
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204 | uint32_t VclkFrequency; |
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205 | uint32_t DclkFrequency; |
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206 | uint32_t SamclkFrequency; |
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207 | uint32_t AclkFrequency; |
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208 | uint32_t EclkFrequency; |
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209 | uint8_t DisplayWatermark; |
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210 | uint8_t McArbIndex; |
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211 | int8_t SclkIndex; |
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212 | int8_t MclkIndex; |
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213 | }; |
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214 | |||
215 | typedef struct SMU7_Fusion_StateInfo SMU7_Fusion_StateInfo; |
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216 | |||
217 | struct SMU7_Fusion_DpmTable |
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218 | { |
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219 | uint32_t SystemFlags; |
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220 | |||
221 | SMU7_PIDController GraphicsPIDController; |
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222 | SMU7_PIDController GioPIDController; |
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223 | |||
224 | uint8_t GraphicsDpmLevelCount; |
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225 | uint8_t GIOLevelCount; |
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226 | uint8_t UvdLevelCount; |
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227 | uint8_t VceLevelCount; |
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228 | |||
229 | uint8_t AcpLevelCount; |
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230 | uint8_t SamuLevelCount; |
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231 | uint16_t FpsHighT; |
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232 | |||
233 | SMU7_Fusion_GraphicsLevel GraphicsLevel [SMU__NUM_SCLK_DPM_STATE]; |
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234 | SMU7_Fusion_ACPILevel ACPILevel; |
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235 | SMU7_Fusion_UvdLevel UvdLevel [SMU7_MAX_LEVELS_UVD]; |
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236 | SMU7_Fusion_ExtClkLevel VceLevel [SMU7_MAX_LEVELS_VCE]; |
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237 | SMU7_Fusion_ExtClkLevel AcpLevel [SMU7_MAX_LEVELS_ACP]; |
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238 | SMU7_Fusion_ExtClkLevel SamuLevel [SMU7_MAX_LEVELS_SAMU]; |
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239 | |||
240 | uint8_t UvdBootLevel; |
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241 | uint8_t VceBootLevel; |
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242 | uint8_t AcpBootLevel; |
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243 | uint8_t SamuBootLevel; |
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244 | uint8_t UVDInterval; |
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245 | uint8_t VCEInterval; |
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246 | uint8_t ACPInterval; |
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247 | uint8_t SAMUInterval; |
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248 | |||
249 | uint8_t GraphicsBootLevel; |
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250 | uint8_t GraphicsInterval; |
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251 | uint8_t GraphicsThermThrottleEnable; |
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252 | uint8_t GraphicsVoltageChangeEnable; |
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253 | |||
254 | uint8_t GraphicsClkSlowEnable; |
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255 | uint8_t GraphicsClkSlowDivider; |
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256 | uint16_t FpsLowT; |
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257 | |||
258 | uint32_t DisplayCac; |
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259 | uint32_t LowSclkInterruptT; |
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260 | |||
261 | uint32_t DRAM_LOG_ADDR_H; |
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262 | uint32_t DRAM_LOG_ADDR_L; |
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263 | uint32_t DRAM_LOG_PHY_ADDR_H; |
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264 | uint32_t DRAM_LOG_PHY_ADDR_L; |
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265 | uint32_t DRAM_LOG_BUFF_SIZE; |
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266 | |||
267 | }; |
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268 | |||
269 | struct SMU7_Fusion_GIODpmTable |
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270 | { |
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271 | |||
272 | SMU7_Fusion_GIOLevel GIOLevel [SMU7_MAX_LEVELS_GIO]; |
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273 | |||
274 | SMU7_PIDController GioPIDController; |
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275 | |||
276 | uint32_t GIOLevelCount; |
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277 | |||
278 | uint8_t Enable; |
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279 | uint8_t GIOVoltageChangeEnable; |
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280 | uint8_t GIOBootLevel; |
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281 | uint8_t padding; |
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282 | uint8_t padding1[2]; |
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283 | uint8_t TargetState; |
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284 | uint8_t CurrenttState; |
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285 | uint8_t ThrottleOnHtc; |
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286 | uint8_t ThermThrottleStatus; |
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287 | uint8_t ThermThrottleTempSelect; |
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288 | uint8_t ThermThrottleEnable; |
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289 | uint16_t TemperatureLimitHigh; |
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290 | uint16_t TemperatureLimitLow; |
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291 | |||
292 | }; |
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293 | |||
294 | typedef struct SMU7_Fusion_DpmTable SMU7_Fusion_DpmTable; |
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295 | typedef struct SMU7_Fusion_GIODpmTable SMU7_Fusion_GIODpmTable; |
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296 | |||
297 | #pragma pack(pop) |
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298 | |||
299 | #endif |
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300 |