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5078 | serge | 1 | /* |
2 | * Copyright 2013 Advanced Micro Devices, Inc. |
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3 | * |
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4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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5 | * copy of this software and associated documentation files (the "Software"), |
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6 | * to deal in the Software without restriction, including without limitation |
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7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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8 | * and/or sell copies of the Software, and to permit persons to whom the |
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9 | * Software is furnished to do so, subject to the following conditions: |
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10 | * |
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11 | * The above copyright notice and this permission notice shall be included in |
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12 | * all copies or substantial portions of the Software. |
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13 | * |
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14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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20 | * OTHER DEALINGS IN THE SOFTWARE. |
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21 | * |
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22 | */ |
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23 | #ifndef PP_SISLANDS_SMC_H |
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24 | #define PP_SISLANDS_SMC_H |
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25 | |||
26 | #include "ppsmc.h" |
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27 | |||
28 | #pragma pack(push, 1) |
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29 | |||
30 | #define SISLANDS_MAX_SMC_PERFORMANCE_LEVELS_PER_SWSTATE 16 |
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31 | |||
32 | struct PP_SIslands_Dpm2PerfLevel |
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33 | { |
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34 | uint8_t MaxPS; |
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35 | uint8_t TgtAct; |
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36 | uint8_t MaxPS_StepInc; |
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37 | uint8_t MaxPS_StepDec; |
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38 | uint8_t PSSamplingTime; |
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39 | uint8_t NearTDPDec; |
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40 | uint8_t AboveSafeInc; |
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41 | uint8_t BelowSafeInc; |
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42 | uint8_t PSDeltaLimit; |
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43 | uint8_t PSDeltaWin; |
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44 | uint16_t PwrEfficiencyRatio; |
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45 | uint8_t Reserved[4]; |
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46 | }; |
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47 | |||
48 | typedef struct PP_SIslands_Dpm2PerfLevel PP_SIslands_Dpm2PerfLevel; |
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49 | |||
50 | struct PP_SIslands_DPM2Status |
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51 | { |
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52 | uint32_t dpm2Flags; |
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53 | uint8_t CurrPSkip; |
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54 | uint8_t CurrPSkipPowerShift; |
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55 | uint8_t CurrPSkipTDP; |
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56 | uint8_t CurrPSkipOCP; |
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57 | uint8_t MaxSPLLIndex; |
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58 | uint8_t MinSPLLIndex; |
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59 | uint8_t CurrSPLLIndex; |
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60 | uint8_t InfSweepMode; |
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61 | uint8_t InfSweepDir; |
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62 | uint8_t TDPexceeded; |
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63 | uint8_t reserved; |
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64 | uint8_t SwitchDownThreshold; |
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65 | uint32_t SwitchDownCounter; |
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66 | uint32_t SysScalingFactor; |
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67 | }; |
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68 | |||
69 | typedef struct PP_SIslands_DPM2Status PP_SIslands_DPM2Status; |
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70 | |||
71 | struct PP_SIslands_DPM2Parameters |
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72 | { |
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73 | uint32_t TDPLimit; |
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74 | uint32_t NearTDPLimit; |
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75 | uint32_t SafePowerLimit; |
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76 | uint32_t PowerBoostLimit; |
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77 | uint32_t MinLimitDelta; |
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78 | }; |
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79 | typedef struct PP_SIslands_DPM2Parameters PP_SIslands_DPM2Parameters; |
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80 | |||
81 | struct PP_SIslands_PAPMStatus |
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82 | { |
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83 | uint32_t EstimatedDGPU_T; |
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84 | uint32_t EstimatedDGPU_P; |
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85 | uint32_t EstimatedAPU_T; |
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86 | uint32_t EstimatedAPU_P; |
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87 | uint8_t dGPU_T_Limit_Exceeded; |
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88 | uint8_t reserved[3]; |
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89 | }; |
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90 | typedef struct PP_SIslands_PAPMStatus PP_SIslands_PAPMStatus; |
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91 | |||
92 | struct PP_SIslands_PAPMParameters |
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93 | { |
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94 | uint32_t NearTDPLimitTherm; |
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95 | uint32_t NearTDPLimitPAPM; |
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96 | uint32_t PlatformPowerLimit; |
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97 | uint32_t dGPU_T_Limit; |
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98 | uint32_t dGPU_T_Warning; |
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99 | uint32_t dGPU_T_Hysteresis; |
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100 | }; |
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101 | typedef struct PP_SIslands_PAPMParameters PP_SIslands_PAPMParameters; |
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102 | |||
103 | struct SISLANDS_SMC_SCLK_VALUE |
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104 | { |
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105 | uint32_t vCG_SPLL_FUNC_CNTL; |
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106 | uint32_t vCG_SPLL_FUNC_CNTL_2; |
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107 | uint32_t vCG_SPLL_FUNC_CNTL_3; |
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108 | uint32_t vCG_SPLL_FUNC_CNTL_4; |
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109 | uint32_t vCG_SPLL_SPREAD_SPECTRUM; |
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110 | uint32_t vCG_SPLL_SPREAD_SPECTRUM_2; |
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111 | uint32_t sclk_value; |
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112 | }; |
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113 | |||
114 | typedef struct SISLANDS_SMC_SCLK_VALUE SISLANDS_SMC_SCLK_VALUE; |
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115 | |||
116 | struct SISLANDS_SMC_MCLK_VALUE |
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117 | { |
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118 | uint32_t vMPLL_FUNC_CNTL; |
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119 | uint32_t vMPLL_FUNC_CNTL_1; |
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120 | uint32_t vMPLL_FUNC_CNTL_2; |
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121 | uint32_t vMPLL_AD_FUNC_CNTL; |
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122 | uint32_t vMPLL_DQ_FUNC_CNTL; |
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123 | uint32_t vMCLK_PWRMGT_CNTL; |
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124 | uint32_t vDLL_CNTL; |
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125 | uint32_t vMPLL_SS; |
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126 | uint32_t vMPLL_SS2; |
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127 | uint32_t mclk_value; |
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128 | }; |
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129 | |||
130 | typedef struct SISLANDS_SMC_MCLK_VALUE SISLANDS_SMC_MCLK_VALUE; |
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131 | |||
132 | struct SISLANDS_SMC_VOLTAGE_VALUE |
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133 | { |
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134 | uint16_t value; |
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135 | uint8_t index; |
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136 | uint8_t phase_settings; |
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137 | }; |
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138 | |||
139 | typedef struct SISLANDS_SMC_VOLTAGE_VALUE SISLANDS_SMC_VOLTAGE_VALUE; |
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140 | |||
141 | struct SISLANDS_SMC_HW_PERFORMANCE_LEVEL |
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142 | { |
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143 | uint8_t ACIndex; |
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144 | uint8_t displayWatermark; |
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145 | uint8_t gen2PCIE; |
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146 | uint8_t UVDWatermark; |
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147 | uint8_t VCEWatermark; |
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148 | uint8_t strobeMode; |
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149 | uint8_t mcFlags; |
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150 | uint8_t padding; |
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151 | uint32_t aT; |
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152 | uint32_t bSP; |
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153 | SISLANDS_SMC_SCLK_VALUE sclk; |
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154 | SISLANDS_SMC_MCLK_VALUE mclk; |
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155 | SISLANDS_SMC_VOLTAGE_VALUE vddc; |
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156 | SISLANDS_SMC_VOLTAGE_VALUE mvdd; |
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157 | SISLANDS_SMC_VOLTAGE_VALUE vddci; |
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158 | SISLANDS_SMC_VOLTAGE_VALUE std_vddc; |
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159 | uint8_t hysteresisUp; |
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160 | uint8_t hysteresisDown; |
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161 | uint8_t stateFlags; |
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162 | uint8_t arbRefreshState; |
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163 | uint32_t SQPowerThrottle; |
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164 | uint32_t SQPowerThrottle_2; |
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165 | uint32_t MaxPoweredUpCU; |
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166 | SISLANDS_SMC_VOLTAGE_VALUE high_temp_vddc; |
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167 | SISLANDS_SMC_VOLTAGE_VALUE low_temp_vddc; |
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168 | uint32_t reserved[2]; |
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169 | PP_SIslands_Dpm2PerfLevel dpm2; |
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170 | }; |
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171 | |||
172 | #define SISLANDS_SMC_STROBE_RATIO 0x0F |
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173 | #define SISLANDS_SMC_STROBE_ENABLE 0x10 |
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174 | |||
175 | #define SISLANDS_SMC_MC_EDC_RD_FLAG 0x01 |
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176 | #define SISLANDS_SMC_MC_EDC_WR_FLAG 0x02 |
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177 | #define SISLANDS_SMC_MC_RTT_ENABLE 0x04 |
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178 | #define SISLANDS_SMC_MC_STUTTER_EN 0x08 |
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179 | #define SISLANDS_SMC_MC_PG_EN 0x10 |
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180 | |||
181 | typedef struct SISLANDS_SMC_HW_PERFORMANCE_LEVEL SISLANDS_SMC_HW_PERFORMANCE_LEVEL; |
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182 | |||
183 | struct SISLANDS_SMC_SWSTATE |
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184 | { |
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185 | uint8_t flags; |
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186 | uint8_t levelCount; |
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187 | uint8_t padding2; |
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188 | uint8_t padding3; |
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189 | SISLANDS_SMC_HW_PERFORMANCE_LEVEL levels[1]; |
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190 | }; |
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191 | |||
192 | typedef struct SISLANDS_SMC_SWSTATE SISLANDS_SMC_SWSTATE; |
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193 | |||
194 | #define SISLANDS_SMC_VOLTAGEMASK_VDDC 0 |
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195 | #define SISLANDS_SMC_VOLTAGEMASK_MVDD 1 |
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196 | #define SISLANDS_SMC_VOLTAGEMASK_VDDCI 2 |
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197 | #define SISLANDS_SMC_VOLTAGEMASK_MAX 4 |
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198 | |||
199 | struct SISLANDS_SMC_VOLTAGEMASKTABLE |
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200 | { |
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201 | uint32_t lowMask[SISLANDS_SMC_VOLTAGEMASK_MAX]; |
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202 | }; |
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203 | |||
204 | typedef struct SISLANDS_SMC_VOLTAGEMASKTABLE SISLANDS_SMC_VOLTAGEMASKTABLE; |
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205 | |||
206 | #define SISLANDS_MAX_NO_VREG_STEPS 32 |
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207 | |||
208 | struct SISLANDS_SMC_STATETABLE |
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209 | { |
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210 | uint8_t thermalProtectType; |
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211 | uint8_t systemFlags; |
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212 | uint8_t maxVDDCIndexInPPTable; |
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213 | uint8_t extraFlags; |
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214 | uint32_t lowSMIO[SISLANDS_MAX_NO_VREG_STEPS]; |
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215 | SISLANDS_SMC_VOLTAGEMASKTABLE voltageMaskTable; |
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216 | SISLANDS_SMC_VOLTAGEMASKTABLE phaseMaskTable; |
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217 | PP_SIslands_DPM2Parameters dpm2Params; |
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218 | SISLANDS_SMC_SWSTATE initialState; |
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219 | SISLANDS_SMC_SWSTATE ACPIState; |
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220 | SISLANDS_SMC_SWSTATE ULVState; |
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221 | SISLANDS_SMC_SWSTATE driverState; |
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222 | SISLANDS_SMC_HW_PERFORMANCE_LEVEL dpmLevels[SISLANDS_MAX_SMC_PERFORMANCE_LEVELS_PER_SWSTATE - 1]; |
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223 | }; |
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224 | |||
225 | typedef struct SISLANDS_SMC_STATETABLE SISLANDS_SMC_STATETABLE; |
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226 | |||
227 | #define SI_SMC_SOFT_REGISTER_mclk_chg_timeout 0x0 |
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228 | #define SI_SMC_SOFT_REGISTER_delay_vreg 0xC |
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229 | #define SI_SMC_SOFT_REGISTER_delay_acpi 0x28 |
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230 | #define SI_SMC_SOFT_REGISTER_seq_index 0x5C |
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231 | #define SI_SMC_SOFT_REGISTER_mvdd_chg_time 0x60 |
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232 | #define SI_SMC_SOFT_REGISTER_mclk_switch_lim 0x70 |
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233 | #define SI_SMC_SOFT_REGISTER_watermark_threshold 0x78 |
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234 | #define SI_SMC_SOFT_REGISTER_phase_shedding_delay 0x88 |
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235 | #define SI_SMC_SOFT_REGISTER_ulv_volt_change_delay 0x8C |
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236 | #define SI_SMC_SOFT_REGISTER_mc_block_delay 0x98 |
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237 | #define SI_SMC_SOFT_REGISTER_ticks_per_us 0xA8 |
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238 | #define SI_SMC_SOFT_REGISTER_crtc_index 0xC4 |
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239 | #define SI_SMC_SOFT_REGISTER_mclk_change_block_cp_min 0xC8 |
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240 | #define SI_SMC_SOFT_REGISTER_mclk_change_block_cp_max 0xCC |
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241 | #define SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width 0xF4 |
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242 | #define SI_SMC_SOFT_REGISTER_tdr_is_about_to_happen 0xFC |
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243 | #define SI_SMC_SOFT_REGISTER_vr_hot_gpio 0x100 |
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244 | #define SI_SMC_SOFT_REGISTER_svi_rework_plat_type 0x118 |
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245 | #define SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svd 0x11c |
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246 | #define SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svc 0x120 |
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247 | |||
248 | #define SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES 16 |
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249 | #define SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES 32 |
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250 | |||
251 | #define SMC_SISLANDS_SCALE_I 7 |
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252 | #define SMC_SISLANDS_SCALE_R 12 |
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253 | |||
254 | struct PP_SIslands_CacConfig |
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255 | { |
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256 | uint16_t cac_lkge_lut[SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES]; |
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257 | uint32_t lkge_lut_V0; |
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258 | uint32_t lkge_lut_Vstep; |
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259 | uint32_t WinTime; |
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260 | uint32_t R_LL; |
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261 | uint32_t calculation_repeats; |
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262 | uint32_t l2numWin_TDP; |
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263 | uint32_t dc_cac; |
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264 | uint8_t lts_truncate_n; |
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265 | uint8_t SHIFT_N; |
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266 | uint8_t log2_PG_LKG_SCALE; |
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267 | uint8_t cac_temp; |
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268 | uint32_t lkge_lut_T0; |
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269 | uint32_t lkge_lut_Tstep; |
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270 | }; |
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271 | |||
272 | typedef struct PP_SIslands_CacConfig PP_SIslands_CacConfig; |
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273 | |||
274 | #define SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE 16 |
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275 | #define SMC_SISLANDS_MC_REGISTER_ARRAY_SET_COUNT 20 |
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276 | |||
277 | struct SMC_SIslands_MCRegisterAddress |
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278 | { |
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279 | uint16_t s0; |
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280 | uint16_t s1; |
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281 | }; |
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282 | |||
283 | typedef struct SMC_SIslands_MCRegisterAddress SMC_SIslands_MCRegisterAddress; |
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284 | |||
285 | struct SMC_SIslands_MCRegisterSet |
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286 | { |
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287 | uint32_t value[SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE]; |
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288 | }; |
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289 | |||
290 | typedef struct SMC_SIslands_MCRegisterSet SMC_SIslands_MCRegisterSet; |
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291 | |||
292 | struct SMC_SIslands_MCRegisters |
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293 | { |
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294 | uint8_t last; |
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295 | uint8_t reserved[3]; |
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296 | SMC_SIslands_MCRegisterAddress address[SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE]; |
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297 | SMC_SIslands_MCRegisterSet data[SMC_SISLANDS_MC_REGISTER_ARRAY_SET_COUNT]; |
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298 | }; |
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299 | |||
300 | typedef struct SMC_SIslands_MCRegisters SMC_SIslands_MCRegisters; |
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301 | |||
302 | struct SMC_SIslands_MCArbDramTimingRegisterSet |
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303 | { |
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304 | uint32_t mc_arb_dram_timing; |
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305 | uint32_t mc_arb_dram_timing2; |
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306 | uint8_t mc_arb_rfsh_rate; |
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307 | uint8_t mc_arb_burst_time; |
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308 | uint8_t padding[2]; |
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309 | }; |
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310 | |||
311 | typedef struct SMC_SIslands_MCArbDramTimingRegisterSet SMC_SIslands_MCArbDramTimingRegisterSet; |
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312 | |||
313 | struct SMC_SIslands_MCArbDramTimingRegisters |
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314 | { |
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315 | uint8_t arb_current; |
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316 | uint8_t reserved[3]; |
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317 | SMC_SIslands_MCArbDramTimingRegisterSet data[16]; |
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318 | }; |
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319 | |||
320 | typedef struct SMC_SIslands_MCArbDramTimingRegisters SMC_SIslands_MCArbDramTimingRegisters; |
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321 | |||
322 | struct SMC_SISLANDS_SPLL_DIV_TABLE |
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323 | { |
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324 | uint32_t freq[256]; |
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325 | uint32_t ss[256]; |
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326 | }; |
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327 | |||
328 | #define SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK 0x01ffffff |
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329 | #define SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT 0 |
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330 | #define SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK 0xfe000000 |
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331 | #define SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT 25 |
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332 | #define SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK 0x000fffff |
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333 | #define SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT 0 |
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334 | #define SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK 0xfff00000 |
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335 | #define SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT 20 |
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336 | |||
337 | typedef struct SMC_SISLANDS_SPLL_DIV_TABLE SMC_SISLANDS_SPLL_DIV_TABLE; |
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338 | |||
339 | #define SMC_SISLANDS_DTE_MAX_FILTER_STAGES 5 |
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340 | |||
341 | #define SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE 16 |
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342 | |||
343 | struct Smc_SIslands_DTE_Configuration |
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344 | { |
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345 | uint32_t tau[SMC_SISLANDS_DTE_MAX_FILTER_STAGES]; |
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346 | uint32_t R[SMC_SISLANDS_DTE_MAX_FILTER_STAGES]; |
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347 | uint32_t K; |
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348 | uint32_t T0; |
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349 | uint32_t MaxT; |
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350 | uint8_t WindowSize; |
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351 | uint8_t Tdep_count; |
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352 | uint8_t temp_select; |
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353 | uint8_t DTE_mode; |
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354 | uint8_t T_limits[SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE]; |
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355 | uint32_t Tdep_tau[SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE]; |
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356 | uint32_t Tdep_R[SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE]; |
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357 | uint32_t Tthreshold; |
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358 | }; |
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359 | |||
360 | typedef struct Smc_SIslands_DTE_Configuration Smc_SIslands_DTE_Configuration; |
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361 | |||
362 | #define SMC_SISLANDS_DTE_STATUS_FLAG_DTE_ON 1 |
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363 | |||
364 | #define SISLANDS_SMC_FIRMWARE_HEADER_LOCATION 0x10000 |
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365 | |||
366 | #define SISLANDS_SMC_FIRMWARE_HEADER_version 0x0 |
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367 | #define SISLANDS_SMC_FIRMWARE_HEADER_flags 0x4 |
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368 | #define SISLANDS_SMC_FIRMWARE_HEADER_softRegisters 0xC |
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369 | #define SISLANDS_SMC_FIRMWARE_HEADER_stateTable 0x10 |
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370 | #define SISLANDS_SMC_FIRMWARE_HEADER_fanTable 0x14 |
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371 | #define SISLANDS_SMC_FIRMWARE_HEADER_CacConfigTable 0x18 |
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372 | #define SISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable 0x24 |
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373 | #define SISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable 0x30 |
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374 | #define SISLANDS_SMC_FIRMWARE_HEADER_spllTable 0x38 |
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375 | #define SISLANDS_SMC_FIRMWARE_HEADER_DteConfiguration 0x40 |
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376 | #define SISLANDS_SMC_FIRMWARE_HEADER_PAPMParameters 0x48 |
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377 | |||
378 | #pragma pack(pop) |
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379 | |||
380 | int si_copy_bytes_to_smc(struct radeon_device *rdev, |
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381 | u32 smc_start_address, |
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382 | const u8 *src, u32 byte_count, u32 limit); |
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383 | void si_start_smc(struct radeon_device *rdev); |
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384 | void si_reset_smc(struct radeon_device *rdev); |
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385 | int si_program_jump_on_start(struct radeon_device *rdev); |
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386 | void si_stop_smc_clock(struct radeon_device *rdev); |
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387 | void si_start_smc_clock(struct radeon_device *rdev); |
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388 | bool si_is_smc_running(struct radeon_device *rdev); |
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389 | PPSMC_Result si_send_msg_to_smc(struct radeon_device *rdev, PPSMC_Msg msg); |
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390 | PPSMC_Result si_wait_for_smc_inactive(struct radeon_device *rdev); |
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391 | int si_load_smc_ucode(struct radeon_device *rdev, u32 limit); |
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392 | int si_read_smc_sram_dword(struct radeon_device *rdev, u32 smc_address, |
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393 | u32 *value, u32 limit); |
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394 | int si_write_smc_sram_dword(struct radeon_device *rdev, u32 smc_address, |
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395 | u32 value, u32 limit); |
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396 | |||
397 | #endif |
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398 |