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5078 serge 1 
/*
2 
 * Copyright 2013 Advanced Micro Devices, Inc.
3 
 *
4 
 * Permission is hereby granted, free of charge, to any person obtaining a
5 
 * copy of this software and associated documentation files (the "Software"),
6 
 * to deal in the Software without restriction, including without limitation
7 
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 
 * and/or sell copies of the Software, and to permit persons to whom the
9 
 * Software is furnished to do so, subject to the following conditions:
10 
 *
11 
 * The above copyright notice and this permission notice shall be included in
12 
 * all copies or substantial portions of the Software.
13 
 *
14 
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17 
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 
 * OTHER DEALINGS IN THE SOFTWARE.
21 
 *
22 
 */
23 
 
24 
#include "drmP.h"
25 
#include "radeon.h"
26 
#include "sid.h"
27 
#include "r600_dpm.h"
28 
#include "si_dpm.h"
29 
#include "atom.h"
30 
#include
31 
#include
32 
 
33 
#define MC_CG_ARB_FREQ_F0           0x0a
34 
#define MC_CG_ARB_FREQ_F1           0x0b
35 
#define MC_CG_ARB_FREQ_F2           0x0c
36 
#define MC_CG_ARB_FREQ_F3           0x0d
37 
 
38 
#define SMC_RAM_END                 0x20000
39 
 
40 
#define SCLK_MIN_DEEPSLEEP_FREQ     1350
41 
 
42 
static const struct si_cac_config_reg cac_weights_tahiti[] =
43 
{
44 
	{ 0x0, 0x0000ffff, 0, 0xc, SISLANDS_CACCONFIG_CGIND },
45 
	{ 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
46 
	{ 0x1, 0x0000ffff, 0, 0x101, SISLANDS_CACCONFIG_CGIND },
47 
	{ 0x1, 0xffff0000, 16, 0xc, SISLANDS_CACCONFIG_CGIND },
48 
	{ 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
49 
	{ 0x3, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
50 
	{ 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
51 
	{ 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
52 
	{ 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
53 
	{ 0x5, 0x0000ffff, 0, 0x8fc, SISLANDS_CACCONFIG_CGIND },
54 
	{ 0x5, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
55 
	{ 0x6, 0x0000ffff, 0, 0x95, SISLANDS_CACCONFIG_CGIND },
56 
	{ 0x6, 0xffff0000, 16, 0x34e, SISLANDS_CACCONFIG_CGIND },
57 
	{ 0x18f, 0x0000ffff, 0, 0x1a1, SISLANDS_CACCONFIG_CGIND },
58 
	{ 0x7, 0x0000ffff, 0, 0xda, SISLANDS_CACCONFIG_CGIND },
59 
	{ 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
60 
	{ 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
61 
	{ 0x8, 0xffff0000, 16, 0x46, SISLANDS_CACCONFIG_CGIND },
62 
	{ 0x9, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
63 
	{ 0xa, 0x0000ffff, 0, 0x208, SISLANDS_CACCONFIG_CGIND },
64 
	{ 0xb, 0x0000ffff, 0, 0xe7, SISLANDS_CACCONFIG_CGIND },
65 
	{ 0xb, 0xffff0000, 16, 0x948, SISLANDS_CACCONFIG_CGIND },
66 
	{ 0xc, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
67 
	{ 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
68 
	{ 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
69 
	{ 0xe, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
70 
	{ 0xf, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
71 
	{ 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
72 
	{ 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
73 
	{ 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
74 
	{ 0x11, 0x0000ffff, 0, 0x167, SISLANDS_CACCONFIG_CGIND },
75 
	{ 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
76 
	{ 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
77 
	{ 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
78 
	{ 0x13, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
79 
	{ 0x14, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
80 
	{ 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
81 
	{ 0x15, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
82 
	{ 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
83 
	{ 0x16, 0x0000ffff, 0, 0x31, SISLANDS_CACCONFIG_CGIND },
84 
	{ 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
85 
	{ 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
86 
	{ 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
87 
	{ 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
88 
	{ 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
89 
	{ 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
90 
	{ 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
91 
	{ 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
92 
	{ 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
93 
	{ 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
94 
	{ 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
95 
	{ 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
96 
	{ 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
97 
	{ 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
98 
	{ 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
99 
	{ 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
100 
	{ 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
101 
	{ 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
102 
	{ 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
103 
	{ 0x6d, 0x0000ffff, 0, 0x18e, SISLANDS_CACCONFIG_CGIND },
104 
	{ 0xFFFFFFFF }
105 
};
106 
 
107 
static const struct si_cac_config_reg lcac_tahiti[] =
108 
{
109 
	{ 0x143, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
110 
	{ 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
111 
	{ 0x146, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
112 
	{ 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
113 
	{ 0x149, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
114 
	{ 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
115 
	{ 0x14c, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
116 
	{ 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
117 
	{ 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
118 
	{ 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
119 
	{ 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
120 
	{ 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
121 
	{ 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
122 
	{ 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
123 
	{ 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
124 
	{ 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
125 
	{ 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
126 
	{ 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
127 
	{ 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
128 
	{ 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
129 
	{ 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
130 
	{ 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
131 
	{ 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
132 
	{ 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
133 
	{ 0x8c, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
134 
	{ 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
135 
	{ 0x8f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
136 
	{ 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
137 
	{ 0x92, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
138 
	{ 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
139 
	{ 0x95, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
140 
	{ 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
141 
	{ 0x14f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
142 
	{ 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
143 
	{ 0x152, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
144 
	{ 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
145 
	{ 0x155, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
146 
	{ 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
147 
	{ 0x158, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
148 
	{ 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
149 
	{ 0x110, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
150 
	{ 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
151 
	{ 0x113, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
152 
	{ 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
153 
	{ 0x116, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
154 
	{ 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
155 
	{ 0x119, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
156 
	{ 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
157 
	{ 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
158 
	{ 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
159 
	{ 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
160 
	{ 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
161 
	{ 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
162 
	{ 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
163 
	{ 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
164 
	{ 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
165 
	{ 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
166 
	{ 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
167 
	{ 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
168 
	{ 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
169 
	{ 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
170 
	{ 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
171 
	{ 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
172 
	{ 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
173 
	{ 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
174 
	{ 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
175 
	{ 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
176 
	{ 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
177 
	{ 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
178 
	{ 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
179 
	{ 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
180 
	{ 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
181 
	{ 0x16d, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
182 
	{ 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
183 
	{ 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
184 
	{ 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
185 
	{ 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
186 
	{ 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
187 
	{ 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
188 
	{ 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
189 
	{ 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
190 
	{ 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
191 
	{ 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
192 
	{ 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
193 
	{ 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
194 
	{ 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
195 
	{ 0xFFFFFFFF }
196 
 
197 
};
198 
 
199 
static const struct si_cac_config_reg cac_override_tahiti[] =
200 
{
201 
	{ 0xFFFFFFFF }
202 
};
203 
 
204 
static const struct si_powertune_data powertune_data_tahiti =
205 
{
206 
	((1 << 16) | 27027),
207 
	6,
208 
	0,
209 
	4,
210 
	95,
211 
	{
212 
		0UL,
213 
		0UL,
214 
		4521550UL,
215 
		309631529UL,
216 
		-1270850L,
217 
		4513710L,
218 
		40
219 
	},
220 
	595000000UL,
221 
	12,
222 
	{
223 
		0,
224 
		0,
225 
		0,
226 
		0,
227 
		0,
228 
		0,
229 
		0,
230 
 
231 
	},
232 
	true
233 
};
234 
 
235 
static const struct si_dte_data dte_data_tahiti =
236 
{
237 
	{ 1159409, 0, 0, 0, 0 },
238 
	{ 777, 0, 0, 0, 0 },
239 
	2,
240 
	54000,
241 
	127000,
242 
	25,
243 
	2,
244 
	10,
245 
	13,
246 
	{ 27, 31, 35, 39, 43, 47, 54, 61, 67, 74, 81, 88, 95, 0, 0, 0 },
247 
	{ 240888759, 221057860, 235370597, 162287531, 158510299, 131423027, 116673180, 103067515, 87941937, 76209048, 68209175, 64090048, 58301890, 0, 0, 0 },
248 
	{ 12024, 11189, 11451, 8411, 7939, 6666, 5681, 4905, 4241, 3720, 3354, 3122, 2890, 0, 0, 0 },
249 
	85,
250 
	false
251 
};
252 
 
253 
static const struct si_dte_data dte_data_tahiti_le =
254 
{
255 
	{ 0x1E8480, 0x7A1200, 0x2160EC0, 0x3938700, 0 },
256 
	{ 0x7D, 0x7D, 0x4E4, 0xB00, 0 },
257 
	0x5,
258 
	0xAFC8,
259 
	0x64,
260 
	0x32,
261 
	1,
262 
	0,
263 
	0x10,
264 
	{ 0x78, 0x7C, 0x82, 0x88, 0x8E, 0x94, 0x9A, 0xA0, 0xA6, 0xAC, 0xB0, 0xB4, 0xB8, 0xBC, 0xC0, 0xC4 },
265 
	{ 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700 },
266 
	{ 0x2AF8, 0x2AF8, 0x29BB, 0x27F9, 0x2637, 0x2475, 0x22B3, 0x20F1, 0x1F2F, 0x1D6D, 0x1734, 0x1414, 0x10F4, 0xDD4, 0xAB4, 0x794 },
267 
	85,
268 
	true
269 
};
270 
 
271 
static const struct si_dte_data dte_data_tahiti_pro =
272 
{
273 
	{ 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
274 
	{ 0x0, 0x0, 0x0, 0x0, 0x0 },
275 
	5,
276 
	45000,
277 
	100,
278 
	0xA,
279 
	1,
280 
	0,
281 
	0x10,
282 
	{ 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
283 
	{ 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
284 
	{ 0x7D0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
285 
	90,
286 
	true
287 
};
288 
 
289 
static const struct si_dte_data dte_data_new_zealand =
290 
{
291 
	{ 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0 },
292 
	{ 0x29B, 0x3E9, 0x537, 0x7D2, 0 },
293 
	0x5,
294 
	0xAFC8,
295 
	0x69,
296 
	0x32,
297 
	1,
298 
	0,
299 
	0x10,
300 
	{ 0x82, 0xA0, 0xB4, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE },
301 
	{ 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
302 
	{ 0xDAC, 0x1388, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685 },
303 
	85,
304 
	true
305 
};
306 
 
307 
static const struct si_dte_data dte_data_aruba_pro =
308 
{
309 
	{ 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
310 
	{ 0x0, 0x0, 0x0, 0x0, 0x0 },
311 
	5,
312 
	45000,
313 
	100,
314 
	0xA,
315 
	1,
316 
	0,
317 
	0x10,
318 
	{ 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
319 
	{ 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
320 
	{ 0x1000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
321 
	90,
322 
	true
323 
};
324 
 
325 
static const struct si_dte_data dte_data_malta =
326 
{
327 
	{ 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
328 
	{ 0x0, 0x0, 0x0, 0x0, 0x0 },
329 
	5,
330 
	45000,
331 
	100,
332 
	0xA,
333 
	1,
334 
	0,
335 
	0x10,
336 
	{ 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
337 
	{ 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
338 
	{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
339 
	90,
340 
	true
341 
};
342 
 
343 
struct si_cac_config_reg cac_weights_pitcairn[] =
344 
{
345 
	{ 0x0, 0x0000ffff, 0, 0x8a, SISLANDS_CACCONFIG_CGIND },
346 
	{ 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
347 
	{ 0x1, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
348 
	{ 0x1, 0xffff0000, 16, 0x24d, SISLANDS_CACCONFIG_CGIND },
349 
	{ 0x2, 0x0000ffff, 0, 0x19, SISLANDS_CACCONFIG_CGIND },
350 
	{ 0x3, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
351 
	{ 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
352 
	{ 0x4, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
353 
	{ 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
354 
	{ 0x5, 0x0000ffff, 0, 0xc11, SISLANDS_CACCONFIG_CGIND },
355 
	{ 0x5, 0xffff0000, 16, 0x7f3, SISLANDS_CACCONFIG_CGIND },
356 
	{ 0x6, 0x0000ffff, 0, 0x403, SISLANDS_CACCONFIG_CGIND },
357 
	{ 0x6, 0xffff0000, 16, 0x367, SISLANDS_CACCONFIG_CGIND },
358 
	{ 0x18f, 0x0000ffff, 0, 0x4c9, SISLANDS_CACCONFIG_CGIND },
359 
	{ 0x7, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
360 
	{ 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
361 
	{ 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
362 
	{ 0x8, 0xffff0000, 16, 0x45d, SISLANDS_CACCONFIG_CGIND },
363 
	{ 0x9, 0x0000ffff, 0, 0x36d, SISLANDS_CACCONFIG_CGIND },
364 
	{ 0xa, 0x0000ffff, 0, 0x534, SISLANDS_CACCONFIG_CGIND },
365 
	{ 0xb, 0x0000ffff, 0, 0x5da, SISLANDS_CACCONFIG_CGIND },
366 
	{ 0xb, 0xffff0000, 16, 0x880, SISLANDS_CACCONFIG_CGIND },
367 
	{ 0xc, 0x0000ffff, 0, 0x201, SISLANDS_CACCONFIG_CGIND },
368 
	{ 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
369 
	{ 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
370 
	{ 0xe, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND },
371 
	{ 0xf, 0x0000ffff, 0, 0x1f, SISLANDS_CACCONFIG_CGIND },
372 
	{ 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
373 
	{ 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
374 
	{ 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
375 
	{ 0x11, 0x0000ffff, 0, 0x5de, SISLANDS_CACCONFIG_CGIND },
376 
	{ 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
377 
	{ 0x12, 0x0000ffff, 0, 0x7b, SISLANDS_CACCONFIG_CGIND },
378 
	{ 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
379 
	{ 0x13, 0xffff0000, 16, 0x13, SISLANDS_CACCONFIG_CGIND },
380 
	{ 0x14, 0x0000ffff, 0, 0xf9, SISLANDS_CACCONFIG_CGIND },
381 
	{ 0x15, 0x0000ffff, 0, 0x66, SISLANDS_CACCONFIG_CGIND },
382 
	{ 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
383 
	{ 0x4e, 0x0000ffff, 0, 0x13, SISLANDS_CACCONFIG_CGIND },
384 
	{ 0x16, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
385 
	{ 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
386 
	{ 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
387 
	{ 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
388 
	{ 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
389 
	{ 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
390 
	{ 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
391 
	{ 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
392 
	{ 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
393 
	{ 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
394 
	{ 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
395 
	{ 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
396 
	{ 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
397 
	{ 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
398 
	{ 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
399 
	{ 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
400 
	{ 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
401 
	{ 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
402 
	{ 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
403 
	{ 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
404 
	{ 0x6d, 0x0000ffff, 0, 0x186, SISLANDS_CACCONFIG_CGIND },
405 
	{ 0xFFFFFFFF }
406 
};
407 
 
408 
static const struct si_cac_config_reg lcac_pitcairn[] =
409 
{
410 
	{ 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
411 
	{ 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
412 
	{ 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
413 
	{ 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
414 
	{ 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
415 
	{ 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
416 
	{ 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
417 
	{ 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
418 
	{ 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
419 
	{ 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
420 
	{ 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
421 
	{ 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
422 
	{ 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
423 
	{ 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
424 
	{ 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
425 
	{ 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
426 
	{ 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
427 
	{ 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
428 
	{ 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
429 
	{ 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
430 
	{ 0x8f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
431 
	{ 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
432 
	{ 0x146, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
433 
	{ 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
434 
	{ 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
435 
	{ 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
436 
	{ 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
437 
	{ 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
438 
	{ 0x116, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
439 
	{ 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
440 
	{ 0x155, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
441 
	{ 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
442 
	{ 0x92, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
443 
	{ 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
444 
	{ 0x149, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
445 
	{ 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
446 
	{ 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
447 
	{ 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
448 
	{ 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
449 
	{ 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
450 
	{ 0x119, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
451 
	{ 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
452 
	{ 0x158, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
453 
	{ 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
454 
	{ 0x95, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
455 
	{ 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
456 
	{ 0x14c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
457 
	{ 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
458 
	{ 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
459 
	{ 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
460 
	{ 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
461 
	{ 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
462 
	{ 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
463 
	{ 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
464 
	{ 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
465 
	{ 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
466 
	{ 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
467 
	{ 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
468 
	{ 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
469 
	{ 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
470 
	{ 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
471 
	{ 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
472 
	{ 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
473 
	{ 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
474 
	{ 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
475 
	{ 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
476 
	{ 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
477 
	{ 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
478 
	{ 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
479 
	{ 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
480 
	{ 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
481 
	{ 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
482 
	{ 0x16d, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
483 
	{ 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
484 
	{ 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
485 
	{ 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
486 
	{ 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
487 
	{ 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
488 
	{ 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
489 
	{ 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
490 
	{ 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
491 
	{ 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
492 
	{ 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
493 
	{ 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
494 
	{ 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
495 
	{ 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
496 
	{ 0xFFFFFFFF }
497 
};
498 
 
499 
static const struct si_cac_config_reg cac_override_pitcairn[] =
500 
{
501 
    { 0xFFFFFFFF }
502 
};
503 
 
504 
static const struct si_powertune_data powertune_data_pitcairn =
505 
{
506 
	((1 << 16) | 27027),
507 
	5,
508 
	0,
509 
	6,
510 
	100,
511 
	{
512 
		51600000UL,
513 
		1800000UL,
514 
		7194395UL,
515 
		309631529UL,
516 
		-1270850L,
517 
		4513710L,
518 
		100
519 
	},
520 
	117830498UL,
521 
	12,
522 
	{
523 
		0,
524 
		0,
525 
		0,
526 
		0,
527 
		0,
528 
		0,
529 
		0,
530 
 
531 
	},
532 
	true
533 
};
534 
 
535 
static const struct si_dte_data dte_data_pitcairn =
536 
{
537 
	{ 0, 0, 0, 0, 0 },
538 
	{ 0, 0, 0, 0, 0 },
539 
	0,
540 
	0,
541 
	0,
542 
	0,
543 
	0,
544 
	0,
545 
	0,
546 
	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
547 
	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
548 
	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
549 
	0,
550 
	false
551 
};
552 
 
553 
static const struct si_dte_data dte_data_curacao_xt =
554 
{
555 
	{ 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
556 
	{ 0x0, 0x0, 0x0, 0x0, 0x0 },
557 
	5,
558 
	45000,
559 
	100,
560 
	0xA,
561 
	1,
562 
	0,
563 
	0x10,
564 
	{ 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
565 
	{ 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
566 
	{ 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
567 
	90,
568 
	true
569 
};
570 
 
571 
static const struct si_dte_data dte_data_curacao_pro =
572 
{
573 
	{ 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
574 
	{ 0x0, 0x0, 0x0, 0x0, 0x0 },
575 
	5,
576 
	45000,
577 
	100,
578 
	0xA,
579 
	1,
580 
	0,
581 
	0x10,
582 
	{ 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
583 
	{ 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
584 
	{ 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
585 
	90,
586 
	true
587 
};
588 
 
589 
static const struct si_dte_data dte_data_neptune_xt =
590 
{
591 
	{ 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
592 
	{ 0x0, 0x0, 0x0, 0x0, 0x0 },
593 
	5,
594 
	45000,
595 
	100,
596 
	0xA,
597 
	1,
598 
	0,
599 
	0x10,
600 
	{ 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
601 
	{ 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
602 
	{ 0x3A2F, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
603 
	90,
604 
	true
605 
};
606 
 
607 
static const struct si_cac_config_reg cac_weights_chelsea_pro[] =
608 
{
609 
	{ 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
610 
	{ 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
611 
	{ 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
612 
	{ 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
613 
	{ 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
614 
	{ 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
615 
	{ 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
616 
	{ 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
617 
	{ 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
618 
	{ 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
619 
	{ 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
620 
	{ 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
621 
	{ 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
622 
	{ 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
623 
	{ 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
624 
	{ 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
625 
	{ 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
626 
	{ 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
627 
	{ 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
628 
	{ 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
629 
	{ 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
630 
	{ 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
631 
	{ 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
632 
	{ 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
633 
	{ 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
634 
	{ 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
635 
	{ 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
636 
	{ 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
637 
	{ 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
638 
	{ 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
639 
	{ 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
640 
	{ 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
641 
	{ 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
642 
	{ 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
643 
	{ 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
644 
	{ 0x14, 0x0000ffff, 0, 0x2BD, SISLANDS_CACCONFIG_CGIND },
645 
	{ 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
646 
	{ 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
647 
	{ 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
648 
	{ 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
649 
	{ 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
650 
	{ 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
651 
	{ 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
652 
	{ 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
653 
	{ 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
654 
	{ 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
655 
	{ 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
656 
	{ 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
657 
	{ 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
658 
	{ 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
659 
	{ 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
660 
	{ 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
661 
	{ 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
662 
	{ 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
663 
	{ 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
664 
	{ 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
665 
	{ 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
666 
	{ 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
667 
	{ 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
668 
	{ 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
669 
	{ 0xFFFFFFFF }
670 
};
671 
 
672 
static const struct si_cac_config_reg cac_weights_chelsea_xt[] =
673 
{
674 
	{ 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
675 
	{ 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
676 
	{ 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
677 
	{ 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
678 
	{ 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
679 
	{ 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
680 
	{ 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
681 
	{ 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
682 
	{ 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
683 
	{ 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
684 
	{ 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
685 
	{ 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
686 
	{ 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
687 
	{ 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
688 
	{ 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
689 
	{ 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
690 
	{ 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
691 
	{ 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
692 
	{ 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
693 
	{ 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
694 
	{ 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
695 
	{ 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
696 
	{ 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
697 
	{ 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
698 
	{ 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
699 
	{ 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
700 
	{ 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
701 
	{ 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
702 
	{ 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
703 
	{ 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
704 
	{ 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
705 
	{ 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
706 
	{ 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
707 
	{ 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
708 
	{ 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
709 
	{ 0x14, 0x0000ffff, 0, 0x30A, SISLANDS_CACCONFIG_CGIND },
710 
	{ 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
711 
	{ 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
712 
	{ 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
713 
	{ 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
714 
	{ 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
715 
	{ 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
716 
	{ 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
717 
	{ 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
718 
	{ 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
719 
	{ 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
720 
	{ 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
721 
	{ 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
722 
	{ 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
723 
	{ 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
724 
	{ 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
725 
	{ 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
726 
	{ 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
727 
	{ 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
728 
	{ 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
729 
	{ 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
730 
	{ 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
731 
	{ 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
732 
	{ 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
733 
	{ 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
734 
	{ 0xFFFFFFFF }
735 
};
736 
 
737 
static const struct si_cac_config_reg cac_weights_heathrow[] =
738 
{
739 
	{ 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
740 
	{ 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
741 
	{ 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
742 
	{ 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
743 
	{ 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
744 
	{ 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
745 
	{ 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
746 
	{ 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
747 
	{ 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
748 
	{ 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
749 
	{ 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
750 
	{ 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
751 
	{ 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
752 
	{ 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
753 
	{ 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
754 
	{ 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
755 
	{ 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
756 
	{ 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
757 
	{ 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
758 
	{ 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
759 
	{ 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
760 
	{ 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
761 
	{ 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
762 
	{ 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
763 
	{ 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
764 
	{ 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
765 
	{ 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
766 
	{ 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
767 
	{ 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
768 
	{ 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
769 
	{ 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
770 
	{ 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
771 
	{ 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
772 
	{ 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
773 
	{ 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
774 
	{ 0x14, 0x0000ffff, 0, 0x362, SISLANDS_CACCONFIG_CGIND },
775 
	{ 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
776 
	{ 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
777 
	{ 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
778 
	{ 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
779 
	{ 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
780 
	{ 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
781 
	{ 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
782 
	{ 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
783 
	{ 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
784 
	{ 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
785 
	{ 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
786 
	{ 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
787 
	{ 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
788 
	{ 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
789 
	{ 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
790 
	{ 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
791 
	{ 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
792 
	{ 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
793 
	{ 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
794 
	{ 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
795 
	{ 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
796 
	{ 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
797 
	{ 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
798 
	{ 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
799 
	{ 0xFFFFFFFF }
800 
};
801 
 
802 
static const struct si_cac_config_reg cac_weights_cape_verde_pro[] =
803 
{
804 
	{ 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
805 
	{ 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
806 
	{ 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
807 
	{ 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
808 
	{ 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
809 
	{ 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
810 
	{ 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
811 
	{ 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
812 
	{ 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
813 
	{ 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
814 
	{ 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
815 
	{ 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
816 
	{ 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
817 
	{ 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
818 
	{ 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
819 
	{ 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
820 
	{ 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
821 
	{ 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
822 
	{ 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
823 
	{ 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
824 
	{ 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
825 
	{ 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
826 
	{ 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
827 
	{ 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
828 
	{ 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
829 
	{ 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
830 
	{ 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
831 
	{ 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
832 
	{ 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
833 
	{ 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
834 
	{ 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
835 
	{ 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
836 
	{ 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
837 
	{ 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
838 
	{ 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
839 
	{ 0x14, 0x0000ffff, 0, 0x315, SISLANDS_CACCONFIG_CGIND },
840 
	{ 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
841 
	{ 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
842 
	{ 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
843 
	{ 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
844 
	{ 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
845 
	{ 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
846 
	{ 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
847 
	{ 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
848 
	{ 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
849 
	{ 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
850 
	{ 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
851 
	{ 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
852 
	{ 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
853 
	{ 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
854 
	{ 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
855 
	{ 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
856 
	{ 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
857 
	{ 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
858 
	{ 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
859 
	{ 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
860 
	{ 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
861 
	{ 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
862 
	{ 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
863 
	{ 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
864 
	{ 0xFFFFFFFF }
865 
};
866 
 
867 
static const struct si_cac_config_reg cac_weights_cape_verde[] =
868 
{
869 
	{ 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
870 
	{ 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
871 
	{ 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
872 
	{ 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
873 
	{ 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
874 
	{ 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
875 
	{ 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
876 
	{ 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
877 
	{ 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
878 
	{ 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
879 
	{ 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
880 
	{ 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
881 
	{ 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
882 
	{ 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
883 
	{ 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
884 
	{ 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
885 
	{ 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
886 
	{ 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
887 
	{ 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
888 
	{ 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
889 
	{ 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
890 
	{ 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
891 
	{ 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
892 
	{ 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
893 
	{ 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
894 
	{ 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
895 
	{ 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
896 
	{ 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
897 
	{ 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
898 
	{ 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
899 
	{ 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
900 
	{ 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
901 
	{ 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
902 
	{ 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
903 
	{ 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
904 
	{ 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND },
905 
	{ 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
906 
	{ 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
907 
	{ 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
908 
	{ 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
909 
	{ 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
910 
	{ 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
911 
	{ 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
912 
	{ 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
913 
	{ 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
914 
	{ 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
915 
	{ 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
916 
	{ 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
917 
	{ 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
918 
	{ 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
919 
	{ 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
920 
	{ 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
921 
	{ 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
922 
	{ 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
923 
	{ 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
924 
	{ 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
925 
	{ 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
926 
	{ 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
927 
	{ 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
928 
	{ 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
929 
	{ 0xFFFFFFFF }
930 
};
931 
 
932 
static const struct si_cac_config_reg lcac_cape_verde[] =
933 
{
934 
	{ 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
935 
	{ 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
936 
	{ 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
937 
	{ 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
938 
	{ 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
939 
	{ 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
940 
	{ 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
941 
	{ 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
942 
	{ 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
943 
	{ 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
944 
	{ 0x143, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
945 
	{ 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
946 
	{ 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
947 
	{ 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
948 
	{ 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
949 
	{ 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
950 
	{ 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
951 
	{ 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
952 
	{ 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
953 
	{ 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
954 
	{ 0x8f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
955 
	{ 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
956 
	{ 0x146, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
957 
	{ 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
958 
	{ 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
959 
	{ 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
960 
	{ 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
961 
	{ 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
962 
	{ 0x164, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
963 
	{ 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
964 
	{ 0x167, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
965 
	{ 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
966 
	{ 0x16a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
967 
	{ 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
968 
	{ 0x15e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
969 
	{ 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
970 
	{ 0x161, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
971 
	{ 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
972 
	{ 0x15b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
973 
	{ 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
974 
	{ 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
975 
	{ 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
976 
	{ 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
977 
	{ 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
978 
	{ 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
979 
	{ 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
980 
	{ 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
981 
	{ 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
982 
	{ 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
983 
	{ 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
984 
	{ 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
985 
	{ 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
986 
	{ 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
987 
	{ 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
988 
	{ 0xFFFFFFFF }
989 
};
990 
 
991 
static const struct si_cac_config_reg cac_override_cape_verde[] =
992 
{
993 
    { 0xFFFFFFFF }
994 
};
995 
 
996 
static const struct si_powertune_data powertune_data_cape_verde =
997 
{
998 
	((1 << 16) | 0x6993),
999 
	5,
1000 
	0,
1001 
	7,
1002 
	105,
1003 
	{
1004 
		0UL,
1005 
		0UL,
1006 
		7194395UL,
1007 
		309631529UL,
1008 
		-1270850L,
1009 
		4513710L,
1010 
		100
1011 
	},
1012 
	117830498UL,
1013 
	12,
1014 
	{
1015 
		0,
1016 
		0,
1017 
		0,
1018 
		0,
1019 
		0,
1020 
		0,
1021 
		0,
1022 
 
1023 
	},
1024 
	true
1025 
};
1026 
 
1027 
static const struct si_dte_data dte_data_cape_verde =
1028 
{
1029 
	{ 0, 0, 0, 0, 0 },
1030 
	{ 0, 0, 0, 0, 0 },
1031 
	0,
1032 
	0,
1033 
	0,
1034 
	0,
1035 
	0,
1036 
	0,
1037 
	0,
1038 
	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1039 
	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1040 
	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1041 
	0,
1042 
	false
1043 
};
1044 
 
1045 
static const struct si_dte_data dte_data_venus_xtx =
1046 
{
1047 
	{ 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1048 
	{ 0x71C, 0xAAB, 0xE39, 0x11C7, 0x0 },
1049 
	5,
1050 
	55000,
1051 
	0x69,
1052 
	0xA,
1053 
	1,
1054 
	0,
1055 
	0x3,
1056 
	{ 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1057 
	{ 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1058 
	{ 0xD6D8, 0x88B8, 0x1555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1059 
	90,
1060 
	true
1061 
};
1062 
 
1063 
static const struct si_dte_data dte_data_venus_xt =
1064 
{
1065 
	{ 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1066 
	{ 0xBDA, 0x11C7, 0x17B4, 0x1DA1, 0x0 },
1067 
	5,
1068 
	55000,
1069 
	0x69,
1070 
	0xA,
1071 
	1,
1072 
	0,
1073 
	0x3,
1074 
	{ 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1075 
	{ 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1076 
	{ 0xAFC8, 0x88B8, 0x238E, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1077 
	90,
1078 
	true
1079 
};
1080 
 
1081 
static const struct si_dte_data dte_data_venus_pro =
1082 
{
1083 
	{  0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1084 
	{ 0x11C7, 0x1AAB, 0x238E, 0x2C72, 0x0 },
1085 
	5,
1086 
	55000,
1087 
	0x69,
1088 
	0xA,
1089 
	1,
1090 
	0,
1091 
	0x3,
1092 
	{ 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1093 
	{ 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1094 
	{ 0x88B8, 0x88B8, 0x3555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1095 
	90,
1096 
	true
1097 
};
1098 
 
1099 
struct si_cac_config_reg cac_weights_oland[] =
1100 
{
1101 
	{ 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
1102 
	{ 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
1103 
	{ 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
1104 
	{ 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
1105 
	{ 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1106 
	{ 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
1107 
	{ 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
1108 
	{ 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
1109 
	{ 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
1110 
	{ 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
1111 
	{ 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
1112 
	{ 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
1113 
	{ 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
1114 
	{ 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1115 
	{ 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
1116 
	{ 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
1117 
	{ 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
1118 
	{ 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
1119 
	{ 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
1120 
	{ 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
1121 
	{ 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
1122 
	{ 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
1123 
	{ 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
1124 
	{ 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
1125 
	{ 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
1126 
	{ 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1127 
	{ 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1128 
	{ 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1129 
	{ 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1130 
	{ 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
1131 
	{ 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1132 
	{ 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
1133 
	{ 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
1134 
	{ 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
1135 
	{ 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1136 
	{ 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND },
1137 
	{ 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1138 
	{ 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1139 
	{ 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1140 
	{ 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1141 
	{ 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
1142 
	{ 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1143 
	{ 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1144 
	{ 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1145 
	{ 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1146 
	{ 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1147 
	{ 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1148 
	{ 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1149 
	{ 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1150 
	{ 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1151 
	{ 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1152 
	{ 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1153 
	{ 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1154 
	{ 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1155 
	{ 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1156 
	{ 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1157 
	{ 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1158 
	{ 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1159 
	{ 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1160 
	{ 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
1161 
	{ 0xFFFFFFFF }
1162 
};
1163 
 
1164 
static const struct si_cac_config_reg cac_weights_mars_pro[] =
1165 
{
1166 
	{ 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1167 
	{ 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1168 
	{ 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1169 
	{ 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1170 
	{ 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1171 
	{ 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1172 
	{ 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1173 
	{ 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1174 
	{ 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1175 
	{ 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1176 
	{ 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1177 
	{ 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1178 
	{ 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1179 
	{ 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1180 
	{ 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1181 
	{ 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1182 
	{ 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1183 
	{ 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1184 
	{ 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1185 
	{ 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1186 
	{ 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1187 
	{ 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1188 
	{ 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1189 
	{ 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1190 
	{ 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1191 
	{ 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1192 
	{ 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1193 
	{ 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1194 
	{ 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1195 
	{ 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1196 
	{ 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1197 
	{ 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1198 
	{ 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1199 
	{ 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1200 
	{ 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1201 
	{ 0x14, 0x0000ffff, 0, 0x2, SISLANDS_CACCONFIG_CGIND },
1202 
	{ 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1203 
	{ 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1204 
	{ 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1205 
	{ 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1206 
	{ 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1207 
	{ 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1208 
	{ 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1209 
	{ 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1210 
	{ 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1211 
	{ 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1212 
	{ 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1213 
	{ 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1214 
	{ 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1215 
	{ 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1216 
	{ 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1217 
	{ 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1218 
	{ 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1219 
	{ 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1220 
	{ 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1221 
	{ 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1222 
	{ 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1223 
	{ 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1224 
	{ 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1225 
	{ 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1226 
	{ 0xFFFFFFFF }
1227 
};
1228 
 
1229 
static const struct si_cac_config_reg cac_weights_mars_xt[] =
1230 
{
1231 
	{ 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1232 
	{ 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1233 
	{ 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1234 
	{ 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1235 
	{ 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1236 
	{ 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1237 
	{ 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1238 
	{ 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1239 
	{ 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1240 
	{ 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1241 
	{ 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1242 
	{ 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1243 
	{ 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1244 
	{ 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1245 
	{ 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1246 
	{ 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1247 
	{ 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1248 
	{ 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1249 
	{ 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1250 
	{ 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1251 
	{ 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1252 
	{ 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1253 
	{ 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1254 
	{ 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1255 
	{ 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1256 
	{ 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1257 
	{ 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1258 
	{ 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1259 
	{ 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1260 
	{ 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1261 
	{ 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1262 
	{ 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1263 
	{ 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1264 
	{ 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1265 
	{ 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1266 
	{ 0x14, 0x0000ffff, 0, 0x60, SISLANDS_CACCONFIG_CGIND },
1267 
	{ 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1268 
	{ 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1269 
	{ 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1270 
	{ 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1271 
	{ 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1272 
	{ 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1273 
	{ 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1274 
	{ 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1275 
	{ 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1276 
	{ 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1277 
	{ 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1278 
	{ 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1279 
	{ 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1280 
	{ 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1281 
	{ 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1282 
	{ 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1283 
	{ 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1284 
	{ 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1285 
	{ 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1286 
	{ 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1287 
	{ 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1288 
	{ 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1289 
	{ 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1290 
	{ 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1291 
	{ 0xFFFFFFFF }
1292 
};
1293 
 
1294 
static const struct si_cac_config_reg cac_weights_oland_pro[] =
1295 
{
1296 
	{ 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1297 
	{ 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1298 
	{ 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1299 
	{ 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1300 
	{ 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1301 
	{ 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1302 
	{ 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1303 
	{ 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1304 
	{ 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1305 
	{ 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1306 
	{ 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1307 
	{ 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1308 
	{ 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1309 
	{ 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1310 
	{ 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1311 
	{ 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1312 
	{ 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1313 
	{ 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1314 
	{ 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1315 
	{ 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1316 
	{ 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1317 
	{ 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1318 
	{ 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1319 
	{ 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1320 
	{ 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1321 
	{ 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1322 
	{ 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1323 
	{ 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1324 
	{ 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1325 
	{ 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1326 
	{ 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1327 
	{ 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1328 
	{ 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1329 
	{ 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1330 
	{ 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1331 
	{ 0x14, 0x0000ffff, 0, 0x90, SISLANDS_CACCONFIG_CGIND },
1332 
	{ 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1333 
	{ 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1334 
	{ 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1335 
	{ 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1336 
	{ 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1337 
	{ 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1338 
	{ 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1339 
	{ 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1340 
	{ 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1341 
	{ 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1342 
	{ 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1343 
	{ 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1344 
	{ 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1345 
	{ 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1346 
	{ 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1347 
	{ 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1348 
	{ 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1349 
	{ 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1350 
	{ 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1351 
	{ 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1352 
	{ 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1353 
	{ 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1354 
	{ 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1355 
	{ 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1356 
	{ 0xFFFFFFFF }
1357 
};
1358 
 
1359 
static const struct si_cac_config_reg cac_weights_oland_xt[] =
1360 
{
1361 
	{ 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1362 
	{ 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1363 
	{ 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1364 
	{ 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1365 
	{ 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1366 
	{ 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1367 
	{ 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1368 
	{ 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1369 
	{ 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1370 
	{ 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1371 
	{ 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1372 
	{ 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1373 
	{ 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1374 
	{ 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1375 
	{ 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1376 
	{ 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1377 
	{ 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1378 
	{ 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1379 
	{ 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1380 
	{ 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1381 
	{ 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1382 
	{ 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1383 
	{ 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1384 
	{ 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1385 
	{ 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1386 
	{ 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1387 
	{ 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1388 
	{ 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1389 
	{ 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1390 
	{ 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1391 
	{ 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1392 
	{ 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1393 
	{ 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1394 
	{ 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1395 
	{ 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1396 
	{ 0x14, 0x0000ffff, 0, 0x120, SISLANDS_CACCONFIG_CGIND },
1397 
	{ 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1398 
	{ 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1399 
	{ 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1400 
	{ 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1401 
	{ 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1402 
	{ 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1403 
	{ 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1404 
	{ 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1405 
	{ 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1406 
	{ 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1407 
	{ 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1408 
	{ 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1409 
	{ 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1410 
	{ 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1411 
	{ 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1412 
	{ 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1413 
	{ 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1414 
	{ 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1415 
	{ 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1416 
	{ 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1417 
	{ 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1418 
	{ 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1419 
	{ 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1420 
	{ 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1421 
	{ 0xFFFFFFFF }
1422 
};
1423 
 
1424 
static const struct si_cac_config_reg lcac_oland[] =
1425 
{
1426 
	{ 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1427 
	{ 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1428 
	{ 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1429 
	{ 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1430 
	{ 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1431 
	{ 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1432 
	{ 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1433 
	{ 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1434 
	{ 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1435 
	{ 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1436 
	{ 0x143, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
1437 
	{ 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1438 
	{ 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1439 
	{ 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1440 
	{ 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1441 
	{ 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1442 
	{ 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1443 
	{ 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1444 
	{ 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1445 
	{ 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1446 
	{ 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1447 
	{ 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1448 
	{ 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1449 
	{ 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1450 
	{ 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1451 
	{ 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1452 
	{ 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1453 
	{ 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1454 
	{ 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1455 
	{ 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1456 
	{ 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1457 
	{ 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1458 
	{ 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1459 
	{ 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1460 
	{ 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1461 
	{ 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1462 
	{ 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1463 
	{ 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1464 
	{ 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1465 
	{ 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1466 
	{ 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1467 
	{ 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1468 
	{ 0xFFFFFFFF }
1469 
};
1470 
 
1471 
static const struct si_cac_config_reg lcac_mars_pro[] =
1472 
{
1473 
	{ 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1474 
	{ 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1475 
	{ 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1476 
	{ 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1477 
	{ 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1478 
	{ 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1479 
	{ 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1480 
	{ 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1481 
	{ 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1482 
	{ 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1483 
	{ 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1484 
	{ 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1485 
	{ 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1486 
	{ 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1487 
	{ 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1488 
	{ 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1489 
	{ 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1490 
	{ 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1491 
	{ 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1492 
	{ 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1493 
	{ 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1494 
	{ 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1495 
	{ 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1496 
	{ 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1497 
	{ 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1498 
	{ 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1499 
	{ 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1500 
	{ 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1501 
	{ 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1502 
	{ 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1503 
	{ 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1504 
	{ 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1505 
	{ 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1506 
	{ 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1507 
	{ 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1508 
	{ 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1509 
	{ 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1510 
	{ 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1511 
	{ 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1512 
	{ 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1513 
	{ 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1514 
	{ 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1515 
	{ 0xFFFFFFFF }
1516 
};
1517 
 
1518 
static const struct si_cac_config_reg cac_override_oland[] =
1519 
{
1520 
	{ 0xFFFFFFFF }
1521 
};
1522 
 
1523 
static const struct si_powertune_data powertune_data_oland =
1524 
{
1525 
	((1 << 16) | 0x6993),
1526 
	5,
1527 
	0,
1528 
	7,
1529 
	105,
1530 
	{
1531 
		0UL,
1532 
		0UL,
1533 
		7194395UL,
1534 
		309631529UL,
1535 
		-1270850L,
1536 
		4513710L,
1537 
		100
1538 
	},
1539 
	117830498UL,
1540 
	12,
1541 
	{
1542 
		0,
1543 
		0,
1544 
		0,
1545 
		0,
1546 
		0,
1547 
		0,
1548 
		0,
1549 
 
1550 
	},
1551 
	true
1552 
};
1553 
 
1554 
static const struct si_powertune_data powertune_data_mars_pro =
1555 
{
1556 
	((1 << 16) | 0x6993),
1557 
	5,
1558 
	0,
1559 
	7,
1560 
	105,
1561 
	{
1562 
		0UL,
1563 
		0UL,
1564 
		7194395UL,
1565 
		309631529UL,
1566 
		-1270850L,
1567 
		4513710L,
1568 
		100
1569 
	},
1570 
	117830498UL,
1571 
	12,
1572 
	{
1573 
		0,
1574 
		0,
1575 
		0,
1576 
		0,
1577 
		0,
1578 
		0,
1579 
		0,
1580 
 
1581 
	},
1582 
	true
1583 
};
1584 
 
1585 
static const struct si_dte_data dte_data_oland =
1586 
{
1587 
	{ 0, 0, 0, 0, 0 },
1588 
	{ 0, 0, 0, 0, 0 },
1589 
	0,
1590 
	0,
1591 
	0,
1592 
	0,
1593 
	0,
1594 
	0,
1595 
	0,
1596 
	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1597 
	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1598 
	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1599 
	0,
1600 
	false
1601 
};
1602 
 
1603 
static const struct si_dte_data dte_data_mars_pro =
1604 
{
1605 
	{ 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1606 
	{ 0x0, 0x0, 0x0, 0x0, 0x0 },
1607 
	5,
1608 
	55000,
1609 
	105,
1610 
	0xA,
1611 
	1,
1612 
	0,
1613 
	0x10,
1614 
	{ 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
1615 
	{ 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
1616 
	{ 0xF627, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1617 
	90,
1618 
	true
1619 
};
1620 
 
1621 
static const struct si_dte_data dte_data_sun_xt =
1622 
{
1623 
	{ 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1624 
	{ 0x0, 0x0, 0x0, 0x0, 0x0 },
1625 
	5,
1626 
	55000,
1627 
	105,
1628 
	0xA,
1629 
	1,
1630 
	0,
1631 
	0x10,
1632 
	{ 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
1633 
	{ 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
1634 
	{ 0xD555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1635 
	90,
1636 
	true
1637 
};
1638 
 
1639 
 
1640 
static const struct si_cac_config_reg cac_weights_hainan[] =
1641 
{
1642 
	{ 0x0, 0x0000ffff, 0, 0x2d9, SISLANDS_CACCONFIG_CGIND },
1643 
	{ 0x0, 0xffff0000, 16, 0x22b, SISLANDS_CACCONFIG_CGIND },
1644 
	{ 0x1, 0x0000ffff, 0, 0x21c, SISLANDS_CACCONFIG_CGIND },
1645 
	{ 0x1, 0xffff0000, 16, 0x1dc, SISLANDS_CACCONFIG_CGIND },
1646 
	{ 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1647 
	{ 0x3, 0x0000ffff, 0, 0x24e, SISLANDS_CACCONFIG_CGIND },
1648 
	{ 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1649 
	{ 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1650 
	{ 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1651 
	{ 0x5, 0x0000ffff, 0, 0x35e, SISLANDS_CACCONFIG_CGIND },
1652 
	{ 0x5, 0xffff0000, 16, 0x1143, SISLANDS_CACCONFIG_CGIND },
1653 
	{ 0x6, 0x0000ffff, 0, 0xe17, SISLANDS_CACCONFIG_CGIND },
1654 
	{ 0x6, 0xffff0000, 16, 0x441, SISLANDS_CACCONFIG_CGIND },
1655 
	{ 0x18f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1656 
	{ 0x7, 0x0000ffff, 0, 0x28b, SISLANDS_CACCONFIG_CGIND },
1657 
	{ 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1658 
	{ 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1659 
	{ 0x8, 0xffff0000, 16, 0xabe, SISLANDS_CACCONFIG_CGIND },
1660 
	{ 0x9, 0x0000ffff, 0, 0xf11, SISLANDS_CACCONFIG_CGIND },
1661 
	{ 0xa, 0x0000ffff, 0, 0x907, SISLANDS_CACCONFIG_CGIND },
1662 
	{ 0xb, 0x0000ffff, 0, 0xb45, SISLANDS_CACCONFIG_CGIND },
1663 
	{ 0xb, 0xffff0000, 16, 0xd1e, SISLANDS_CACCONFIG_CGIND },
1664 
	{ 0xc, 0x0000ffff, 0, 0xa2c, SISLANDS_CACCONFIG_CGIND },
1665 
	{ 0xd, 0x0000ffff, 0, 0x62, SISLANDS_CACCONFIG_CGIND },
1666 
	{ 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1667 
	{ 0xe, 0x0000ffff, 0, 0x1f3, SISLANDS_CACCONFIG_CGIND },
1668 
	{ 0xf, 0x0000ffff, 0, 0x42, SISLANDS_CACCONFIG_CGIND },
1669 
	{ 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1670 
	{ 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1671 
	{ 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1672 
	{ 0x11, 0x0000ffff, 0, 0x709, SISLANDS_CACCONFIG_CGIND },
1673 
	{ 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1674 
	{ 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1675 
	{ 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1676 
	{ 0x13, 0xffff0000, 16, 0x3a, SISLANDS_CACCONFIG_CGIND },
1677 
	{ 0x14, 0x0000ffff, 0, 0x357, SISLANDS_CACCONFIG_CGIND },
1678 
	{ 0x15, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND },
1679 
	{ 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1680 
	{ 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1681 
	{ 0x16, 0x0000ffff, 0, 0x314, SISLANDS_CACCONFIG_CGIND },
1682 
	{ 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1683 
	{ 0x17, 0x0000ffff, 0, 0x6d, SISLANDS_CACCONFIG_CGIND },
1684 
	{ 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1685 
	{ 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1686 
	{ 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1687 
	{ 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1688 
	{ 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1689 
	{ 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1690 
	{ 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1691 
	{ 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1692 
	{ 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1693 
	{ 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1694 
	{ 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1695 
	{ 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1696 
	{ 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1697 
	{ 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1698 
	{ 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1699 
	{ 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1700 
	{ 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1701 
	{ 0x6d, 0x0000ffff, 0, 0x1b9, SISLANDS_CACCONFIG_CGIND },
1702 
	{ 0xFFFFFFFF }
1703 
};
1704 
 
1705 
static const struct si_powertune_data powertune_data_hainan =
1706 
{
1707 
	((1 << 16) | 0x6993),
1708 
	5,
1709 
	0,
1710 
	9,
1711 
	105,
1712 
	{
1713 
		0UL,
1714 
		0UL,
1715 
		7194395UL,
1716 
		309631529UL,
1717 
		-1270850L,
1718 
		4513710L,
1719 
		100
1720 
	},
1721 
	117830498UL,
1722 
	12,
1723 
	{
1724 
		0,
1725 
		0,
1726 
		0,
1727 
		0,
1728 
		0,
1729 
		0,
1730 
		0,
1731 
 
1732 
	},
1733 
	true
1734 
};
1735 
 
1736 
struct rv7xx_power_info *rv770_get_pi(struct radeon_device *rdev);
1737 
struct evergreen_power_info *evergreen_get_pi(struct radeon_device *rdev);
1738 
struct ni_power_info *ni_get_pi(struct radeon_device *rdev);
1739 
struct ni_ps *ni_get_ps(struct radeon_ps *rps);
1740 
 
1741 
extern int si_mc_load_microcode(struct radeon_device *rdev);
1742 
 
1743 
static int si_populate_voltage_value(struct radeon_device *rdev,
1744 
				     const struct atom_voltage_table *table,
1745 
				     u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage);
1746 
static int si_get_std_voltage_value(struct radeon_device *rdev,
1747 
				    SISLANDS_SMC_VOLTAGE_VALUE *voltage,
1748 
				    u16 *std_voltage);
1749 
static int si_write_smc_soft_register(struct radeon_device *rdev,
1750 
				      u16 reg_offset, u32 value);
1751 
static int si_convert_power_level_to_smc(struct radeon_device *rdev,
1752 
					 struct rv7xx_pl *pl,
1753 
					 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level);
1754 
static int si_calculate_sclk_params(struct radeon_device *rdev,
1755 
				    u32 engine_clock,
1756 
				    SISLANDS_SMC_SCLK_VALUE *sclk);
1757 
 
1758 
static struct si_power_info *si_get_pi(struct radeon_device *rdev)
1759 
{
1760 
        struct si_power_info *pi = rdev->pm.dpm.priv;
1761 
 
1762 
        return pi;
1763 
}
1764 
 
1765 
static void si_calculate_leakage_for_v_and_t_formula(const struct ni_leakage_coeffients *coeff,
1766 
						     u16 v, s32 t, u32 ileakage, u32 *leakage)
1767 
{
1768 
	s64 kt, kv, leakage_w, i_leakage, vddc;
1769 
	s64 temperature, t_slope, t_intercept, av, bv, t_ref;
1770 
	s64 tmp;
1771 
 
1772 
	i_leakage = div64_s64(drm_int2fixp(ileakage), 100);
1773 
	vddc = div64_s64(drm_int2fixp(v), 1000);
1774 
	temperature = div64_s64(drm_int2fixp(t), 1000);
1775 
 
1776 
	t_slope = div64_s64(drm_int2fixp(coeff->t_slope), 100000000);
1777 
	t_intercept = div64_s64(drm_int2fixp(coeff->t_intercept), 100000000);
1778 
	av = div64_s64(drm_int2fixp(coeff->av), 100000000);
1779 
	bv = div64_s64(drm_int2fixp(coeff->bv), 100000000);
1780 
	t_ref = drm_int2fixp(coeff->t_ref);
1781 
 
1782 
	tmp = drm_fixp_mul(t_slope, vddc) + t_intercept;
1783 
	kt = drm_fixp_exp(drm_fixp_mul(tmp, temperature));
1784 
	kt = drm_fixp_div(kt, drm_fixp_exp(drm_fixp_mul(tmp, t_ref)));
1785 
	kv = drm_fixp_mul(av, drm_fixp_exp(drm_fixp_mul(bv, vddc)));
1786 
 
1787 
	leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
1788 
 
1789 
	*leakage = drm_fixp2int(leakage_w * 1000);
1790 
}
1791 
 
1792 
static void si_calculate_leakage_for_v_and_t(struct radeon_device *rdev,
1793 
					     const struct ni_leakage_coeffients *coeff,
1794 
					     u16 v,
1795 
					     s32 t,
1796 
					     u32 i_leakage,
1797 
					     u32 *leakage)
1798 
{
1799 
	si_calculate_leakage_for_v_and_t_formula(coeff, v, t, i_leakage, leakage);
1800 
}
1801 
 
1802 
static void si_calculate_leakage_for_v_formula(const struct ni_leakage_coeffients *coeff,
1803 
					       const u32 fixed_kt, u16 v,
1804 
					       u32 ileakage, u32 *leakage)
1805 
{
1806 
	s64 kt, kv, leakage_w, i_leakage, vddc;
1807 
 
1808 
	i_leakage = div64_s64(drm_int2fixp(ileakage), 100);
1809 
	vddc = div64_s64(drm_int2fixp(v), 1000);
1810 
 
1811 
	kt = div64_s64(drm_int2fixp(fixed_kt), 100000000);
1812 
	kv = drm_fixp_mul(div64_s64(drm_int2fixp(coeff->av), 100000000),
1813 
			  drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bv), 100000000), vddc)));
1814 
 
1815 
	leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
1816 
 
1817 
	*leakage = drm_fixp2int(leakage_w * 1000);
1818 
}
1819 
 
1820 
static void si_calculate_leakage_for_v(struct radeon_device *rdev,
1821 
				       const struct ni_leakage_coeffients *coeff,
1822 
				       const u32 fixed_kt,
1823 
				       u16 v,
1824 
				       u32 i_leakage,
1825 
				       u32 *leakage)
1826 
{
1827 
	si_calculate_leakage_for_v_formula(coeff, fixed_kt, v, i_leakage, leakage);
1828 
}
1829 
 
1830 
 
1831 
static void si_update_dte_from_pl2(struct radeon_device *rdev,
1832 
				   struct si_dte_data *dte_data)
1833 
{
1834 
	u32 p_limit1 = rdev->pm.dpm.tdp_limit;
1835 
	u32 p_limit2 = rdev->pm.dpm.near_tdp_limit;
1836 
	u32 k = dte_data->k;
1837 
	u32 t_max = dte_data->max_t;
1838 
	u32 t_split[5] = { 10, 15, 20, 25, 30 };
1839 
	u32 t_0 = dte_data->t0;
1840 
	u32 i;
1841 
 
1842 
	if (p_limit2 != 0 && p_limit2 <= p_limit1) {
1843 
		dte_data->tdep_count = 3;
1844 
 
1845 
		for (i = 0; i < k; i++) {
1846 
			dte_data->r[i] =
1847 
				(t_split[i] * (t_max - t_0/(u32)1000) * (1 << 14)) /
1848 
				(p_limit2  * (u32)100);
1849 
		}
1850 
 
1851 
		dte_data->tdep_r[1] = dte_data->r[4] * 2;
1852 
 
1853 
		for (i = 2; i < SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; i++) {
1854 
			dte_data->tdep_r[i] = dte_data->r[4];
1855 
		}
1856 
	} else {
1857 
		DRM_ERROR("Invalid PL2! DTE will not be updated.\n");
1858 
	}
1859 
}
1860 
 
1861 
static void si_initialize_powertune_defaults(struct radeon_device *rdev)
1862 
{
1863 
	struct ni_power_info *ni_pi = ni_get_pi(rdev);
1864 
	struct si_power_info *si_pi = si_get_pi(rdev);
1865 
	bool update_dte_from_pl2 = false;
1866 
 
1867 
	if (rdev->family == CHIP_TAHITI) {
1868 
		si_pi->cac_weights = cac_weights_tahiti;
1869 
		si_pi->lcac_config = lcac_tahiti;
1870 
		si_pi->cac_override = cac_override_tahiti;
1871 
		si_pi->powertune_data = &powertune_data_tahiti;
1872 
		si_pi->dte_data = dte_data_tahiti;
1873 
 
1874 
		switch (rdev->pdev->device) {
1875 
		case 0x6798:
1876 
			si_pi->dte_data.enable_dte_by_default = true;
1877 
			break;
1878 
		case 0x6799:
1879 
			si_pi->dte_data = dte_data_new_zealand;
1880 
			break;
1881 
		case 0x6790:
1882 
		case 0x6791:
1883 
		case 0x6792:
1884 
		case 0x679E:
1885 
			si_pi->dte_data = dte_data_aruba_pro;
1886 
			update_dte_from_pl2 = true;
1887 
			break;
1888 
		case 0x679B:
1889 
			si_pi->dte_data = dte_data_malta;
1890 
			update_dte_from_pl2 = true;
1891 
			break;
1892 
		case 0x679A:
1893 
			si_pi->dte_data = dte_data_tahiti_pro;
1894 
			update_dte_from_pl2 = true;
1895 
			break;
1896 
		default:
1897 
			if (si_pi->dte_data.enable_dte_by_default == true)
1898 
				DRM_ERROR("DTE is not enabled!\n");
1899 
			break;
1900 
		}
1901 
	} else if (rdev->family == CHIP_PITCAIRN) {
1902 
		switch (rdev->pdev->device) {
1903 
		case 0x6810:
1904 
		case 0x6818:
1905 
			si_pi->cac_weights = cac_weights_pitcairn;
1906 
			si_pi->lcac_config = lcac_pitcairn;
1907 
			si_pi->cac_override = cac_override_pitcairn;
1908 
			si_pi->powertune_data = &powertune_data_pitcairn;
1909 
			si_pi->dte_data = dte_data_curacao_xt;
1910 
			update_dte_from_pl2 = true;
1911 
			break;
1912 
		case 0x6819:
1913 
		case 0x6811:
1914 
			si_pi->cac_weights = cac_weights_pitcairn;
1915 
			si_pi->lcac_config = lcac_pitcairn;
1916 
			si_pi->cac_override = cac_override_pitcairn;
1917 
			si_pi->powertune_data = &powertune_data_pitcairn;
1918 
			si_pi->dte_data = dte_data_curacao_pro;
1919 
			update_dte_from_pl2 = true;
1920 
			break;
1921 
		case 0x6800:
1922 
		case 0x6806:
1923 
			si_pi->cac_weights = cac_weights_pitcairn;
1924 
			si_pi->lcac_config = lcac_pitcairn;
1925 
			si_pi->cac_override = cac_override_pitcairn;
1926 
			si_pi->powertune_data = &powertune_data_pitcairn;
1927 
			si_pi->dte_data = dte_data_neptune_xt;
1928 
			update_dte_from_pl2 = true;
1929 
			break;
1930 
		default:
1931 
			si_pi->cac_weights = cac_weights_pitcairn;
1932 
			si_pi->lcac_config = lcac_pitcairn;
1933 
			si_pi->cac_override = cac_override_pitcairn;
1934 
			si_pi->powertune_data = &powertune_data_pitcairn;
1935 
			si_pi->dte_data = dte_data_pitcairn;
1936 
			break;
1937 
		}
1938 
	} else if (rdev->family == CHIP_VERDE) {
1939 
		si_pi->lcac_config = lcac_cape_verde;
1940 
		si_pi->cac_override = cac_override_cape_verde;
1941 
		si_pi->powertune_data = &powertune_data_cape_verde;
1942 
 
1943 
		switch (rdev->pdev->device) {
1944 
		case 0x683B:
1945 
		case 0x683F:
1946 
		case 0x6829:
1947 
		case 0x6835:
1948 
			si_pi->cac_weights = cac_weights_cape_verde_pro;
1949 
			si_pi->dte_data = dte_data_cape_verde;
1950 
			break;
1951 
		case 0x682C:
1952 
			si_pi->cac_weights = cac_weights_cape_verde_pro;
1953 
			si_pi->dte_data = dte_data_sun_xt;
1954 
			break;
1955 
		case 0x6825:
1956 
		case 0x6827:
1957 
			si_pi->cac_weights = cac_weights_heathrow;
1958 
			si_pi->dte_data = dte_data_cape_verde;
1959 
			break;
1960 
		case 0x6824:
1961 
		case 0x682D:
1962 
			si_pi->cac_weights = cac_weights_chelsea_xt;
1963 
			si_pi->dte_data = dte_data_cape_verde;
1964 
			break;
1965 
		case 0x682F:
1966 
			si_pi->cac_weights = cac_weights_chelsea_pro;
1967 
			si_pi->dte_data = dte_data_cape_verde;
1968 
			break;
1969 
		case 0x6820:
1970 
			si_pi->cac_weights = cac_weights_heathrow;
1971 
			si_pi->dte_data = dte_data_venus_xtx;
1972 
			break;
1973 
		case 0x6821:
1974 
			si_pi->cac_weights = cac_weights_heathrow;
1975 
			si_pi->dte_data = dte_data_venus_xt;
1976 
			break;
1977 
		case 0x6823:
1978 
		case 0x682B:
1979 
		case 0x6822:
1980 
		case 0x682A:
1981 
			si_pi->cac_weights = cac_weights_chelsea_pro;
1982 
			si_pi->dte_data = dte_data_venus_pro;
1983 
			break;
1984 
		default:
1985 
			si_pi->cac_weights = cac_weights_cape_verde;
1986 
			si_pi->dte_data = dte_data_cape_verde;
1987 
			break;
1988 
		}
1989 
	} else if (rdev->family == CHIP_OLAND) {
1990 
		switch (rdev->pdev->device) {
1991 
		case 0x6601:
1992 
		case 0x6621:
1993 
		case 0x6603:
1994 
		case 0x6605:
1995 
			si_pi->cac_weights = cac_weights_mars_pro;
1996 
			si_pi->lcac_config = lcac_mars_pro;
1997 
			si_pi->cac_override = cac_override_oland;
1998 
			si_pi->powertune_data = &powertune_data_mars_pro;
1999 
			si_pi->dte_data = dte_data_mars_pro;
2000 
			update_dte_from_pl2 = true;
2001 
			break;
2002 
		case 0x6600:
2003 
		case 0x6606:
2004 
		case 0x6620:
2005 
		case 0x6604:
2006 
			si_pi->cac_weights = cac_weights_mars_xt;
2007 
			si_pi->lcac_config = lcac_mars_pro;
2008 
			si_pi->cac_override = cac_override_oland;
2009 
			si_pi->powertune_data = &powertune_data_mars_pro;
2010 
			si_pi->dte_data = dte_data_mars_pro;
2011 
			update_dte_from_pl2 = true;
2012 
			break;
2013 
		case 0x6611:
2014 
		case 0x6613:
2015 
		case 0x6608:
2016 
			si_pi->cac_weights = cac_weights_oland_pro;
2017 
			si_pi->lcac_config = lcac_mars_pro;
2018 
			si_pi->cac_override = cac_override_oland;
2019 
			si_pi->powertune_data = &powertune_data_mars_pro;
2020 
			si_pi->dte_data = dte_data_mars_pro;
2021 
			update_dte_from_pl2 = true;
2022 
			break;
2023 
		case 0x6610:
2024 
			si_pi->cac_weights = cac_weights_oland_xt;
2025 
			si_pi->lcac_config = lcac_mars_pro;
2026 
			si_pi->cac_override = cac_override_oland;
2027 
			si_pi->powertune_data = &powertune_data_mars_pro;
2028 
			si_pi->dte_data = dte_data_mars_pro;
2029 
			update_dte_from_pl2 = true;
2030 
			break;
2031 
		default:
2032 
			si_pi->cac_weights = cac_weights_oland;
2033 
			si_pi->lcac_config = lcac_oland;
2034 
			si_pi->cac_override = cac_override_oland;
2035 
			si_pi->powertune_data = &powertune_data_oland;
2036 
			si_pi->dte_data = dte_data_oland;
2037 
			break;
2038 
		}
2039 
	} else if (rdev->family == CHIP_HAINAN) {
2040 
		si_pi->cac_weights = cac_weights_hainan;
2041 
		si_pi->lcac_config = lcac_oland;
2042 
		si_pi->cac_override = cac_override_oland;
2043 
		si_pi->powertune_data = &powertune_data_hainan;
2044 
		si_pi->dte_data = dte_data_sun_xt;
2045 
		update_dte_from_pl2 = true;
2046 
	} else {
2047 
		DRM_ERROR("Unknown SI asic revision, failed to initialize PowerTune!\n");
2048 
		return;
2049 
	}
2050 
 
2051 
	ni_pi->enable_power_containment = false;
2052 
	ni_pi->enable_cac = false;
2053 
	ni_pi->enable_sq_ramping = false;
2054 
	si_pi->enable_dte = false;
2055 
 
2056 
	if (si_pi->powertune_data->enable_powertune_by_default) {
2057 
		ni_pi->enable_power_containment= true;
2058 
		ni_pi->enable_cac = true;
2059 
		if (si_pi->dte_data.enable_dte_by_default) {
2060 
			si_pi->enable_dte = true;
2061 
			if (update_dte_from_pl2)
2062 
				si_update_dte_from_pl2(rdev, &si_pi->dte_data);
2063 
 
2064 
		}
2065 
		ni_pi->enable_sq_ramping = true;
2066 
	}
2067 
 
2068 
	ni_pi->driver_calculate_cac_leakage = true;
2069 
	ni_pi->cac_configuration_required = true;
2070 
 
2071 
	if (ni_pi->cac_configuration_required) {
2072 
		ni_pi->support_cac_long_term_average = true;
2073 
		si_pi->dyn_powertune_data.l2_lta_window_size =
2074 
			si_pi->powertune_data->l2_lta_window_size_default;
2075 
		si_pi->dyn_powertune_data.lts_truncate =
2076 
			si_pi->powertune_data->lts_truncate_default;
2077 
	} else {
2078 
		ni_pi->support_cac_long_term_average = false;
2079 
		si_pi->dyn_powertune_data.l2_lta_window_size = 0;
2080 
		si_pi->dyn_powertune_data.lts_truncate = 0;
2081 
	}
2082 
 
2083 
	si_pi->dyn_powertune_data.disable_uvd_powertune = false;
2084 
}
2085 
 
2086 
static u32 si_get_smc_power_scaling_factor(struct radeon_device *rdev)
2087 
{
2088 
	return 1;
2089 
}
2090 
 
2091 
static u32 si_calculate_cac_wintime(struct radeon_device *rdev)
2092 
{
2093 
	u32 xclk;
2094 
	u32 wintime;
2095 
	u32 cac_window;
2096 
	u32 cac_window_size;
2097 
 
2098 
	xclk = radeon_get_xclk(rdev);
2099 
 
2100 
	if (xclk == 0)
2101 
		return 0;
2102 
 
2103 
	cac_window = RREG32(CG_CAC_CTRL) & CAC_WINDOW_MASK;
2104 
	cac_window_size = ((cac_window & 0xFFFF0000) >> 16) * (cac_window & 0x0000FFFF);
2105 
 
2106 
	wintime = (cac_window_size * 100) / xclk;
2107 
 
2108 
	return wintime;
2109 
}
2110 
 
2111 
static u32 si_scale_power_for_smc(u32 power_in_watts, u32 scaling_factor)
2112 
{
2113 
	return power_in_watts;
2114 
}
2115 
 
2116 
static int si_calculate_adjusted_tdp_limits(struct radeon_device *rdev,
2117 
					    bool adjust_polarity,
2118 
					    u32 tdp_adjustment,
2119 
					    u32 *tdp_limit,
2120 
					    u32 *near_tdp_limit)
2121 
{
2122 
	u32 adjustment_delta, max_tdp_limit;
2123 
 
2124 
	if (tdp_adjustment > (u32)rdev->pm.dpm.tdp_od_limit)
2125 
		return -EINVAL;
2126 
 
2127 
	max_tdp_limit = ((100 + 100) * rdev->pm.dpm.tdp_limit) / 100;
2128 
 
2129 
	if (adjust_polarity) {
2130 
		*tdp_limit = ((100 + tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100;
2131 
		*near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted + (*tdp_limit - rdev->pm.dpm.tdp_limit);
2132 
	} else {
2133 
		*tdp_limit = ((100 - tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100;
2134 
		adjustment_delta  = rdev->pm.dpm.tdp_limit - *tdp_limit;
2135 
		if (adjustment_delta < rdev->pm.dpm.near_tdp_limit_adjusted)
2136 
			*near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted - adjustment_delta;
2137 
		else
2138 
			*near_tdp_limit = 0;
2139 
	}
2140 
 
2141 
	if ((*tdp_limit <= 0) || (*tdp_limit > max_tdp_limit))
2142 
		return -EINVAL;
2143 
	if ((*near_tdp_limit <= 0) || (*near_tdp_limit > *tdp_limit))
2144 
		return -EINVAL;
2145 
 
2146 
	return 0;
2147 
}
2148 
 
2149 
static int si_populate_smc_tdp_limits(struct radeon_device *rdev,
2150 
				      struct radeon_ps *radeon_state)
2151 
{
2152 
	struct ni_power_info *ni_pi = ni_get_pi(rdev);
2153 
	struct si_power_info *si_pi = si_get_pi(rdev);
2154 
 
2155 
	if (ni_pi->enable_power_containment) {
2156 
		SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable;
2157 
		PP_SIslands_PAPMParameters *papm_parm;
2158 
		struct radeon_ppm_table *ppm = rdev->pm.dpm.dyn_state.ppm_table;
2159 
		u32 scaling_factor = si_get_smc_power_scaling_factor(rdev);
2160 
		u32 tdp_limit;
2161 
		u32 near_tdp_limit;
2162 
		int ret;
2163 
 
2164 
		if (scaling_factor == 0)
2165 
			return -EINVAL;
2166 
 
2167 
		memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE));
2168 
 
2169 
		ret = si_calculate_adjusted_tdp_limits(rdev,
2170 
						       false, /* ??? */
2171 
						       rdev->pm.dpm.tdp_adjustment,
2172 
						       &tdp_limit,
2173 
						       &near_tdp_limit);
2174 
		if (ret)
2175 
			return ret;
2176 
 
2177 
		smc_table->dpm2Params.TDPLimit =
2178 
			cpu_to_be32(si_scale_power_for_smc(tdp_limit, scaling_factor) * 1000);
2179 
		smc_table->dpm2Params.NearTDPLimit =
2180 
			cpu_to_be32(si_scale_power_for_smc(near_tdp_limit, scaling_factor) * 1000);
2181 
		smc_table->dpm2Params.SafePowerLimit =
2182 
			cpu_to_be32(si_scale_power_for_smc((near_tdp_limit * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000);
2183 
 
2184 
		ret = si_copy_bytes_to_smc(rdev,
2185 
					   (si_pi->state_table_start + offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +
2186 
						 offsetof(PP_SIslands_DPM2Parameters, TDPLimit)),
2187 
					   (u8 *)(&(smc_table->dpm2Params.TDPLimit)),
2188 
					   sizeof(u32) * 3,
2189 
					   si_pi->sram_end);
2190 
		if (ret)
2191 
			return ret;
2192 
 
2193 
		if (si_pi->enable_ppm) {
2194 
			papm_parm = &si_pi->papm_parm;
2195 
			memset(papm_parm, 0, sizeof(PP_SIslands_PAPMParameters));
2196 
			papm_parm->NearTDPLimitTherm = cpu_to_be32(ppm->dgpu_tdp);
2197 
			papm_parm->dGPU_T_Limit = cpu_to_be32(ppm->tj_max);
2198 
			papm_parm->dGPU_T_Warning = cpu_to_be32(95);
2199 
			papm_parm->dGPU_T_Hysteresis = cpu_to_be32(5);
2200 
			papm_parm->PlatformPowerLimit = 0xffffffff;
2201 
			papm_parm->NearTDPLimitPAPM = 0xffffffff;
2202 
 
2203 
			ret = si_copy_bytes_to_smc(rdev, si_pi->papm_cfg_table_start,
2204 
						   (u8 *)papm_parm,
2205 
						   sizeof(PP_SIslands_PAPMParameters),
2206 
						   si_pi->sram_end);
2207 
			if (ret)
2208 
				return ret;
2209 
		}
2210 
	}
2211 
	return 0;
2212 
}
2213 
 
2214 
static int si_populate_smc_tdp_limits_2(struct radeon_device *rdev,
2215 
					struct radeon_ps *radeon_state)
2216 
{
2217 
	struct ni_power_info *ni_pi = ni_get_pi(rdev);
2218 
	struct si_power_info *si_pi = si_get_pi(rdev);
2219 
 
2220 
	if (ni_pi->enable_power_containment) {
2221 
		SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable;
2222 
		u32 scaling_factor = si_get_smc_power_scaling_factor(rdev);
2223 
		int ret;
2224 
 
2225 
		memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE));
2226 
 
2227 
		smc_table->dpm2Params.NearTDPLimit =
2228 
			cpu_to_be32(si_scale_power_for_smc(rdev->pm.dpm.near_tdp_limit_adjusted, scaling_factor) * 1000);
2229 
		smc_table->dpm2Params.SafePowerLimit =
2230 
			cpu_to_be32(si_scale_power_for_smc((rdev->pm.dpm.near_tdp_limit_adjusted * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000);
2231 
 
2232 
		ret = si_copy_bytes_to_smc(rdev,
2233 
					   (si_pi->state_table_start +
2234 
					    offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +
2235 
					    offsetof(PP_SIslands_DPM2Parameters, NearTDPLimit)),
2236 
					   (u8 *)(&(smc_table->dpm2Params.NearTDPLimit)),
2237 
					   sizeof(u32) * 2,
2238 
					   si_pi->sram_end);
2239 
		if (ret)
2240 
			return ret;
2241 
	}
2242 
 
2243 
	return 0;
2244 
}
2245 
 
2246 
static u16 si_calculate_power_efficiency_ratio(struct radeon_device *rdev,
2247 
					       const u16 prev_std_vddc,
2248 
					       const u16 curr_std_vddc)
2249 
{
2250 
	u64 margin = (u64)SISLANDS_DPM2_PWREFFICIENCYRATIO_MARGIN;
2251 
	u64 prev_vddc = (u64)prev_std_vddc;
2252 
	u64 curr_vddc = (u64)curr_std_vddc;
2253 
	u64 pwr_efficiency_ratio, n, d;
2254 
 
2255 
	if ((prev_vddc == 0) || (curr_vddc == 0))
2256 
		return 0;
2257 
 
2258 
	n = div64_u64((u64)1024 * curr_vddc * curr_vddc * ((u64)1000 + margin), (u64)1000);
2259 
	d = prev_vddc * prev_vddc;
2260 
	pwr_efficiency_ratio = div64_u64(n, d);
2261 
 
2262 
	if (pwr_efficiency_ratio > (u64)0xFFFF)
2263 
		return 0;
2264 
 
2265 
	return (u16)pwr_efficiency_ratio;
2266 
}
2267 
 
2268 
static bool si_should_disable_uvd_powertune(struct radeon_device *rdev,
2269 
					    struct radeon_ps *radeon_state)
2270 
{
2271 
	struct si_power_info *si_pi = si_get_pi(rdev);
2272 
 
2273 
	if (si_pi->dyn_powertune_data.disable_uvd_powertune &&
2274 
	    radeon_state->vclk && radeon_state->dclk)
2275 
		return true;
2276 
 
2277 
	return false;
2278 
}
2279 
 
2280 
static int si_populate_power_containment_values(struct radeon_device *rdev,
2281 
						struct radeon_ps *radeon_state,
2282 
						SISLANDS_SMC_SWSTATE *smc_state)
2283 
{
2284 
	struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
2285 
	struct ni_power_info *ni_pi = ni_get_pi(rdev);
2286 
	struct ni_ps *state = ni_get_ps(radeon_state);
2287 
	SISLANDS_SMC_VOLTAGE_VALUE vddc;
2288 
	u32 prev_sclk;
2289 
	u32 max_sclk;
2290 
	u32 min_sclk;
2291 
	u16 prev_std_vddc;
2292 
	u16 curr_std_vddc;
2293 
	int i;
2294 
	u16 pwr_efficiency_ratio;
2295 
	u8 max_ps_percent;
2296 
	bool disable_uvd_power_tune;
2297 
	int ret;
2298 
 
2299 
	if (ni_pi->enable_power_containment == false)
2300 
		return 0;
2301 
 
2302 
	if (state->performance_level_count == 0)
2303 
		return -EINVAL;
2304 
 
2305 
	if (smc_state->levelCount != state->performance_level_count)
2306 
		return -EINVAL;
2307 
 
2308 
	disable_uvd_power_tune = si_should_disable_uvd_powertune(rdev, radeon_state);
2309 
 
2310 
	smc_state->levels[0].dpm2.MaxPS = 0;
2311 
	smc_state->levels[0].dpm2.NearTDPDec = 0;
2312 
	smc_state->levels[0].dpm2.AboveSafeInc = 0;
2313 
	smc_state->levels[0].dpm2.BelowSafeInc = 0;
2314 
	smc_state->levels[0].dpm2.PwrEfficiencyRatio = 0;
2315 
 
2316 
	for (i = 1; i < state->performance_level_count; i++) {
2317 
		prev_sclk = state->performance_levels[i-1].sclk;
2318 
		max_sclk  = state->performance_levels[i].sclk;
2319 
		if (i == 1)
2320 
			max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_M;
2321 
		else
2322 
			max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_H;
2323 
 
2324 
		if (prev_sclk > max_sclk)
2325 
			return -EINVAL;
2326 
 
2327 
		if ((max_ps_percent == 0) ||
2328 
		    (prev_sclk == max_sclk) ||
2329 
		    disable_uvd_power_tune) {
2330 
			min_sclk = max_sclk;
2331 
		} else if (i == 1) {
2332 
			min_sclk = prev_sclk;
2333 
		} else {
2334 
			min_sclk = (prev_sclk * (u32)max_ps_percent) / 100;
2335 
		}
2336 
 
2337 
		if (min_sclk < state->performance_levels[0].sclk)
2338 
			min_sclk = state->performance_levels[0].sclk;
2339 
 
2340 
		if (min_sclk == 0)
2341 
			return -EINVAL;
2342 
 
2343 
		ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
2344 
						state->performance_levels[i-1].vddc, &vddc);
2345 
		if (ret)
2346 
			return ret;
2347 
 
2348 
		ret = si_get_std_voltage_value(rdev, &vddc, &prev_std_vddc);
2349 
		if (ret)
2350 
			return ret;
2351 
 
2352 
		ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
2353 
						state->performance_levels[i].vddc, &vddc);
2354 
		if (ret)
2355 
			return ret;
2356 
 
2357 
		ret = si_get_std_voltage_value(rdev, &vddc, &curr_std_vddc);
2358 
		if (ret)
2359 
			return ret;
2360 
 
2361 
		pwr_efficiency_ratio = si_calculate_power_efficiency_ratio(rdev,
2362 
									   prev_std_vddc, curr_std_vddc);
2363 
 
2364 
		smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / max_sclk);
2365 
		smc_state->levels[i].dpm2.NearTDPDec = SISLANDS_DPM2_NEAR_TDP_DEC;
2366 
		smc_state->levels[i].dpm2.AboveSafeInc = SISLANDS_DPM2_ABOVE_SAFE_INC;
2367 
		smc_state->levels[i].dpm2.BelowSafeInc = SISLANDS_DPM2_BELOW_SAFE_INC;
2368 
		smc_state->levels[i].dpm2.PwrEfficiencyRatio = cpu_to_be16(pwr_efficiency_ratio);
2369 
	}
2370 
 
2371 
	return 0;
2372 
}
2373 
 
2374 
static int si_populate_sq_ramping_values(struct radeon_device *rdev,
2375 
					 struct radeon_ps *radeon_state,
2376 
					 SISLANDS_SMC_SWSTATE *smc_state)
2377 
{
2378 
	struct ni_power_info *ni_pi = ni_get_pi(rdev);
2379 
	struct ni_ps *state = ni_get_ps(radeon_state);
2380 
	u32 sq_power_throttle, sq_power_throttle2;
2381 
	bool enable_sq_ramping = ni_pi->enable_sq_ramping;
2382 
	int i;
2383 
 
2384 
	if (state->performance_level_count == 0)
2385 
		return -EINVAL;
2386 
 
2387 
	if (smc_state->levelCount != state->performance_level_count)
2388 
		return -EINVAL;
2389 
 
2390 
	if (rdev->pm.dpm.sq_ramping_threshold == 0)
2391 
		return -EINVAL;
2392 
 
2393 
	if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER > (MAX_POWER_MASK >> MAX_POWER_SHIFT))
2394 
		enable_sq_ramping = false;
2395 
 
2396 
	if (SISLANDS_DPM2_SQ_RAMP_MIN_POWER > (MIN_POWER_MASK >> MIN_POWER_SHIFT))
2397 
		enable_sq_ramping = false;
2398 
 
2399 
	if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA > (MAX_POWER_DELTA_MASK >> MAX_POWER_DELTA_SHIFT))
2400 
		enable_sq_ramping = false;
2401 
 
2402 
	if (SISLANDS_DPM2_SQ_RAMP_STI_SIZE > (STI_SIZE_MASK >> STI_SIZE_SHIFT))
2403 
		enable_sq_ramping = false;
2404 
 
2405 
	if (SISLANDS_DPM2_SQ_RAMP_LTI_RATIO > (LTI_RATIO_MASK >> LTI_RATIO_SHIFT))
2406 
		enable_sq_ramping = false;
2407 
 
2408 
	for (i = 0; i < state->performance_level_count; i++) {
2409 
		sq_power_throttle = 0;
2410 
		sq_power_throttle2 = 0;
2411 
 
2412 
		if ((state->performance_levels[i].sclk >= rdev->pm.dpm.sq_ramping_threshold) &&
2413 
		    enable_sq_ramping) {
2414 
			sq_power_throttle |= MAX_POWER(SISLANDS_DPM2_SQ_RAMP_MAX_POWER);
2415 
			sq_power_throttle |= MIN_POWER(SISLANDS_DPM2_SQ_RAMP_MIN_POWER);
2416 
			sq_power_throttle2 |= MAX_POWER_DELTA(SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA);
2417 
			sq_power_throttle2 |= STI_SIZE(SISLANDS_DPM2_SQ_RAMP_STI_SIZE);
2418 
			sq_power_throttle2 |= LTI_RATIO(SISLANDS_DPM2_SQ_RAMP_LTI_RATIO);
2419 
		} else {
2420 
			sq_power_throttle |= MAX_POWER_MASK | MIN_POWER_MASK;
2421 
			sq_power_throttle2 |= MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
2422 
		}
2423 
 
2424 
		smc_state->levels[i].SQPowerThrottle = cpu_to_be32(sq_power_throttle);
2425 
		smc_state->levels[i].SQPowerThrottle_2 = cpu_to_be32(sq_power_throttle2);
2426 
	}
2427 
 
2428 
	return 0;
2429 
}
2430 
 
2431 
static int si_enable_power_containment(struct radeon_device *rdev,
2432 
				       struct radeon_ps *radeon_new_state,
2433 
				       bool enable)
2434 
{
2435 
	struct ni_power_info *ni_pi = ni_get_pi(rdev);
2436 
	PPSMC_Result smc_result;
2437 
	int ret = 0;
2438 
 
2439 
	if (ni_pi->enable_power_containment) {
2440 
		if (enable) {
2441 
			if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) {
2442 
				smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingActive);
2443 
				if (smc_result != PPSMC_Result_OK) {
2444 
					ret = -EINVAL;
2445 
					ni_pi->pc_enabled = false;
2446 
				} else {
2447 
					ni_pi->pc_enabled = true;
2448 
				}
2449 
			}
2450 
		} else {
2451 
			smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingInactive);
2452 
			if (smc_result != PPSMC_Result_OK)
2453 
				ret = -EINVAL;
2454 
			ni_pi->pc_enabled = false;
2455 
		}
2456 
	}
2457 
 
2458 
	return ret;
2459 
}
2460 
 
2461 
static int si_initialize_smc_dte_tables(struct radeon_device *rdev)
2462 
{
2463 
	struct si_power_info *si_pi = si_get_pi(rdev);
2464 
	int ret = 0;
2465 
	struct si_dte_data *dte_data = &si_pi->dte_data;
2466 
	Smc_SIslands_DTE_Configuration *dte_tables = NULL;
2467 
	u32 table_size;
2468 
	u8 tdep_count;
2469 
	u32 i;
2470 
 
2471 
	if (dte_data == NULL)
2472 
		si_pi->enable_dte = false;
2473 
 
2474 
	if (si_pi->enable_dte == false)
2475 
		return 0;
2476 
 
2477 
	if (dte_data->k <= 0)
2478 
		return -EINVAL;
2479 
 
2480 
	dte_tables = kzalloc(sizeof(Smc_SIslands_DTE_Configuration), GFP_KERNEL);
2481 
	if (dte_tables == NULL) {
2482 
		si_pi->enable_dte = false;
2483 
		return -ENOMEM;
2484 
	}
2485 
 
2486 
	table_size = dte_data->k;
2487 
 
2488 
	if (table_size > SMC_SISLANDS_DTE_MAX_FILTER_STAGES)
2489 
		table_size = SMC_SISLANDS_DTE_MAX_FILTER_STAGES;
2490 
 
2491 
	tdep_count = dte_data->tdep_count;
2492 
	if (tdep_count > SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE)
2493 
		tdep_count = SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE;
2494 
 
2495 
	dte_tables->K = cpu_to_be32(table_size);
2496 
	dte_tables->T0 = cpu_to_be32(dte_data->t0);
2497 
	dte_tables->MaxT = cpu_to_be32(dte_data->max_t);
2498 
	dte_tables->WindowSize = dte_data->window_size;
2499 
	dte_tables->temp_select = dte_data->temp_select;
2500 
	dte_tables->DTE_mode = dte_data->dte_mode;
2501 
	dte_tables->Tthreshold = cpu_to_be32(dte_data->t_threshold);
2502 
 
2503 
	if (tdep_count > 0)
2504 
		table_size--;
2505 
 
2506 
	for (i = 0; i < table_size; i++) {
2507 
		dte_tables->tau[i] = cpu_to_be32(dte_data->tau[i]);
2508 
		dte_tables->R[i]   = cpu_to_be32(dte_data->r[i]);
2509 
	}
2510 
 
2511 
	dte_tables->Tdep_count = tdep_count;
2512 
 
2513 
	for (i = 0; i < (u32)tdep_count; i++) {
2514 
		dte_tables->T_limits[i] = dte_data->t_limits[i];
2515 
		dte_tables->Tdep_tau[i] = cpu_to_be32(dte_data->tdep_tau[i]);
2516 
		dte_tables->Tdep_R[i] = cpu_to_be32(dte_data->tdep_r[i]);
2517 
	}
2518 
 
2519 
	ret = si_copy_bytes_to_smc(rdev, si_pi->dte_table_start, (u8 *)dte_tables,
2520 
				   sizeof(Smc_SIslands_DTE_Configuration), si_pi->sram_end);
2521 
	kfree(dte_tables);
2522 
 
2523 
	return ret;
2524 
}
2525 
 
2526 
static int si_get_cac_std_voltage_max_min(struct radeon_device *rdev,
2527 
					  u16 *max, u16 *min)
2528 
{
2529 
	struct si_power_info *si_pi = si_get_pi(rdev);
2530 
	struct radeon_cac_leakage_table *table =
2531 
		&rdev->pm.dpm.dyn_state.cac_leakage_table;
2532 
	u32 i;
2533 
	u32 v0_loadline;
2534 
 
2535 
 
2536 
	if (table == NULL)
2537 
		return -EINVAL;
2538 
 
2539 
	*max = 0;
2540 
	*min = 0xFFFF;
2541 
 
2542 
	for (i = 0; i < table->count; i++) {
2543 
		if (table->entries[i].vddc > *max)
2544 
			*max = table->entries[i].vddc;
2545 
		if (table->entries[i].vddc < *min)
2546 
			*min = table->entries[i].vddc;
2547 
	}
2548 
 
2549 
	if (si_pi->powertune_data->lkge_lut_v0_percent > 100)
2550 
		return -EINVAL;
2551 
 
2552 
	v0_loadline = (*min) * (100 - si_pi->powertune_data->lkge_lut_v0_percent) / 100;
2553 
 
2554 
	if (v0_loadline > 0xFFFFUL)
2555 
		return -EINVAL;
2556 
 
2557 
	*min = (u16)v0_loadline;
2558 
 
2559 
	if ((*min > *max) || (*max == 0) || (*min == 0))
2560 
		return -EINVAL;
2561 
 
2562 
	return 0;
2563 
}
2564 
 
2565 
static u16 si_get_cac_std_voltage_step(u16 max, u16 min)
2566 
{
2567 
	return ((max - min) + (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)) /
2568 
		SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES;
2569 
}
2570 
 
2571 
static int si_init_dte_leakage_table(struct radeon_device *rdev,
2572 
				     PP_SIslands_CacConfig *cac_tables,
2573 
				     u16 vddc_max, u16 vddc_min, u16 vddc_step,
2574 
				     u16 t0, u16 t_step)
2575 
{
2576 
	struct si_power_info *si_pi = si_get_pi(rdev);
2577 
	u32 leakage;
2578 
	unsigned int i, j;
2579 
	s32 t;
2580 
	u32 smc_leakage;
2581 
	u32 scaling_factor;
2582 
	u16 voltage;
2583 
 
2584 
	scaling_factor = si_get_smc_power_scaling_factor(rdev);
2585 
 
2586 
	for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) {
2587 
		t = (1000 * (i * t_step + t0));
2588 
 
2589 
		for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) {
2590 
			voltage = vddc_max - (vddc_step * j);
2591 
 
2592 
			si_calculate_leakage_for_v_and_t(rdev,
2593 
							 &si_pi->powertune_data->leakage_coefficients,
2594 
							 voltage,
2595 
							 t,
2596 
							 si_pi->dyn_powertune_data.cac_leakage,
2597 
							 &leakage);
2598 
 
2599 
			smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4;
2600 
 
2601 
			if (smc_leakage > 0xFFFF)
2602 
				smc_leakage = 0xFFFF;
2603 
 
2604 
			cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] =
2605 
				cpu_to_be16((u16)smc_leakage);
2606 
		}
2607 
	}
2608 
	return 0;
2609 
}
2610 
 
2611 
static int si_init_simplified_leakage_table(struct radeon_device *rdev,
2612 
					    PP_SIslands_CacConfig *cac_tables,
2613 
					    u16 vddc_max, u16 vddc_min, u16 vddc_step)
2614 
{
2615 
	struct si_power_info *si_pi = si_get_pi(rdev);
2616 
	u32 leakage;
2617 
	unsigned int i, j;
2618 
	u32 smc_leakage;
2619 
	u32 scaling_factor;
2620 
	u16 voltage;
2621 
 
2622 
	scaling_factor = si_get_smc_power_scaling_factor(rdev);
2623 
 
2624 
	for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) {
2625 
		voltage = vddc_max - (vddc_step * j);
2626 
 
2627 
		si_calculate_leakage_for_v(rdev,
2628 
					   &si_pi->powertune_data->leakage_coefficients,
2629 
					   si_pi->powertune_data->fixed_kt,
2630 
					   voltage,
2631 
					   si_pi->dyn_powertune_data.cac_leakage,
2632 
					   &leakage);
2633 
 
2634 
		smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4;
2635 
 
2636 
		if (smc_leakage > 0xFFFF)
2637 
			smc_leakage = 0xFFFF;
2638 
 
2639 
		for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++)
2640 
			cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] =
2641 
				cpu_to_be16((u16)smc_leakage);
2642 
	}
2643 
	return 0;
2644 
}
2645 
 
2646 
static int si_initialize_smc_cac_tables(struct radeon_device *rdev)
2647 
{
2648 
	struct ni_power_info *ni_pi = ni_get_pi(rdev);
2649 
	struct si_power_info *si_pi = si_get_pi(rdev);
2650 
	PP_SIslands_CacConfig *cac_tables = NULL;
2651 
	u16 vddc_max, vddc_min, vddc_step;
2652 
	u16 t0, t_step;
2653 
	u32 load_line_slope, reg;
2654 
	int ret = 0;
2655 
	u32 ticks_per_us = radeon_get_xclk(rdev) / 100;
2656 
 
2657 
	if (ni_pi->enable_cac == false)
2658 
		return 0;
2659 
 
2660 
	cac_tables = kzalloc(sizeof(PP_SIslands_CacConfig), GFP_KERNEL);
2661 
	if (!cac_tables)
2662 
		return -ENOMEM;
2663 
 
2664 
	reg = RREG32(CG_CAC_CTRL) & ~CAC_WINDOW_MASK;
2665 
	reg |= CAC_WINDOW(si_pi->powertune_data->cac_window);
2666 
	WREG32(CG_CAC_CTRL, reg);
2667 
 
2668 
	si_pi->dyn_powertune_data.cac_leakage = rdev->pm.dpm.cac_leakage;
2669 
	si_pi->dyn_powertune_data.dc_pwr_value =
2670 
		si_pi->powertune_data->dc_cac[NISLANDS_DCCAC_LEVEL_0];
2671 
	si_pi->dyn_powertune_data.wintime = si_calculate_cac_wintime(rdev);
2672 
	si_pi->dyn_powertune_data.shift_n = si_pi->powertune_data->shift_n_default;
2673 
 
2674 
	si_pi->dyn_powertune_data.leakage_minimum_temperature = 80 * 1000;
2675 
 
2676 
	ret = si_get_cac_std_voltage_max_min(rdev, &vddc_max, &vddc_min);
2677 
	if (ret)
2678 
		goto done_free;
2679 
 
2680 
	vddc_step = si_get_cac_std_voltage_step(vddc_max, vddc_min);
2681 
	vddc_min = vddc_max - (vddc_step * (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1));
2682 
	t_step = 4;
2683 
	t0 = 60;
2684 
 
2685 
	if (si_pi->enable_dte || ni_pi->driver_calculate_cac_leakage)
2686 
		ret = si_init_dte_leakage_table(rdev, cac_tables,
2687 
						vddc_max, vddc_min, vddc_step,
2688 
						t0, t_step);
2689 
	else
2690 
		ret = si_init_simplified_leakage_table(rdev, cac_tables,
2691 
						       vddc_max, vddc_min, vddc_step);
2692 
	if (ret)
2693 
		goto done_free;
2694 
 
2695 
	load_line_slope = ((u32)rdev->pm.dpm.load_line_slope << SMC_SISLANDS_SCALE_R) / 100;
2696 
 
2697 
	cac_tables->l2numWin_TDP = cpu_to_be32(si_pi->dyn_powertune_data.l2_lta_window_size);
2698 
	cac_tables->lts_truncate_n = si_pi->dyn_powertune_data.lts_truncate;
2699 
	cac_tables->SHIFT_N = si_pi->dyn_powertune_data.shift_n;
2700 
	cac_tables->lkge_lut_V0 = cpu_to_be32((u32)vddc_min);
2701 
	cac_tables->lkge_lut_Vstep = cpu_to_be32((u32)vddc_step);
2702 
	cac_tables->R_LL = cpu_to_be32(load_line_slope);
2703 
	cac_tables->WinTime = cpu_to_be32(si_pi->dyn_powertune_data.wintime);
2704 
	cac_tables->calculation_repeats = cpu_to_be32(2);
2705 
	cac_tables->dc_cac = cpu_to_be32(0);
2706 
	cac_tables->log2_PG_LKG_SCALE = 12;
2707 
	cac_tables->cac_temp = si_pi->powertune_data->operating_temp;
2708 
	cac_tables->lkge_lut_T0 = cpu_to_be32((u32)t0);
2709 
	cac_tables->lkge_lut_Tstep = cpu_to_be32((u32)t_step);
2710 
 
2711 
	ret = si_copy_bytes_to_smc(rdev, si_pi->cac_table_start, (u8 *)cac_tables,
2712 
				   sizeof(PP_SIslands_CacConfig), si_pi->sram_end);
2713 
 
2714 
	if (ret)
2715 
		goto done_free;
2716 
 
2717 
	ret = si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ticks_per_us, ticks_per_us);
2718 
 
2719 
done_free:
2720 
	if (ret) {
2721 
		ni_pi->enable_cac = false;
2722 
		ni_pi->enable_power_containment = false;
2723 
	}
2724 
 
2725 
	kfree(cac_tables);
2726 
 
2727 
	return 0;
2728 
}
2729 
 
2730 
static int si_program_cac_config_registers(struct radeon_device *rdev,
2731 
					   const struct si_cac_config_reg *cac_config_regs)
2732 
{
2733 
	const struct si_cac_config_reg *config_regs = cac_config_regs;
2734 
	u32 data = 0, offset;
2735 
 
2736 
	if (!config_regs)
2737 
		return -EINVAL;
2738 
 
2739 
	while (config_regs->offset != 0xFFFFFFFF) {
2740 
		switch (config_regs->type) {
2741 
		case SISLANDS_CACCONFIG_CGIND:
2742 
			offset = SMC_CG_IND_START + config_regs->offset;
2743 
			if (offset < SMC_CG_IND_END)
2744 
				data = RREG32_SMC(offset);
2745 
			break;
2746 
		default:
2747 
			data = RREG32(config_regs->offset << 2);
2748 
			break;
2749 
		}
2750 
 
2751 
		data &= ~config_regs->mask;
2752 
		data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
2753 
 
2754 
		switch (config_regs->type) {
2755 
		case SISLANDS_CACCONFIG_CGIND:
2756 
			offset = SMC_CG_IND_START + config_regs->offset;
2757 
			if (offset < SMC_CG_IND_END)
2758 
				WREG32_SMC(offset, data);
2759 
			break;
2760 
		default:
2761 
			WREG32(config_regs->offset << 2, data);
2762 
			break;
2763 
		}
2764 
		config_regs++;
2765 
	}
2766 
	return 0;
2767 
}
2768 
 
2769 
static int si_initialize_hardware_cac_manager(struct radeon_device *rdev)
2770 
{
2771 
	struct ni_power_info *ni_pi = ni_get_pi(rdev);
2772 
	struct si_power_info *si_pi = si_get_pi(rdev);
2773 
	int ret;
2774 
 
2775 
	if ((ni_pi->enable_cac == false) ||
2776 
	    (ni_pi->cac_configuration_required == false))
2777 
		return 0;
2778 
 
2779 
	ret = si_program_cac_config_registers(rdev, si_pi->lcac_config);
2780 
	if (ret)
2781 
		return ret;
2782 
	ret = si_program_cac_config_registers(rdev, si_pi->cac_override);
2783 
	if (ret)
2784 
		return ret;
2785 
	ret = si_program_cac_config_registers(rdev, si_pi->cac_weights);
2786 
	if (ret)
2787 
		return ret;
2788 
 
2789 
	return 0;
2790 
}
2791 
 
2792 
static int si_enable_smc_cac(struct radeon_device *rdev,
2793 
			     struct radeon_ps *radeon_new_state,
2794 
			     bool enable)
2795 
{
2796 
	struct ni_power_info *ni_pi = ni_get_pi(rdev);
2797 
	struct si_power_info *si_pi = si_get_pi(rdev);
2798 
	PPSMC_Result smc_result;
2799 
	int ret = 0;
2800 
 
2801 
	if (ni_pi->enable_cac) {
2802 
		if (enable) {
2803 
			if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) {
2804 
				if (ni_pi->support_cac_long_term_average) {
2805 
					smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgEnable);
2806 
					if (smc_result != PPSMC_Result_OK)
2807 
						ni_pi->support_cac_long_term_average = false;
2808 
				}
2809 
 
2810 
				smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableCac);
2811 
				if (smc_result != PPSMC_Result_OK) {
2812 
					ret = -EINVAL;
2813 
					ni_pi->cac_enabled = false;
2814 
				} else {
2815 
					ni_pi->cac_enabled = true;
2816 
				}
2817 
 
2818 
				if (si_pi->enable_dte) {
2819 
					smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableDTE);
2820 
					if (smc_result != PPSMC_Result_OK)
2821 
						ret = -EINVAL;
2822 
				}
2823 
			}
2824 
		} else if (ni_pi->cac_enabled) {
2825 
			if (si_pi->enable_dte)
2826 
				smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableDTE);
2827 
 
2828 
			smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableCac);
2829 
 
2830 
			ni_pi->cac_enabled = false;
2831 
 
2832 
			if (ni_pi->support_cac_long_term_average)
2833 
				smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgDisable);
2834 
		}
2835 
	}
2836 
	return ret;
2837 
}
2838 
 
2839 
static int si_init_smc_spll_table(struct radeon_device *rdev)
2840 
{
2841 
	struct ni_power_info *ni_pi = ni_get_pi(rdev);
2842 
	struct si_power_info *si_pi = si_get_pi(rdev);
2843 
	SMC_SISLANDS_SPLL_DIV_TABLE *spll_table;
2844 
	SISLANDS_SMC_SCLK_VALUE sclk_params;
2845 
	u32 fb_div, p_div;
2846 
	u32 clk_s, clk_v;
2847 
	u32 sclk = 0;
2848 
	int ret = 0;
2849 
	u32 tmp;
2850 
	int i;
2851 
 
2852 
	if (si_pi->spll_table_start == 0)
2853 
		return -EINVAL;
2854 
 
2855 
	spll_table = kzalloc(sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), GFP_KERNEL);
2856 
	if (spll_table == NULL)
2857 
		return -ENOMEM;
2858 
 
2859 
	for (i = 0; i < 256; i++) {
2860 
		ret = si_calculate_sclk_params(rdev, sclk, &sclk_params);
2861 
		if (ret)
2862 
			break;
2863 
 
2864 
		p_div = (sclk_params.vCG_SPLL_FUNC_CNTL & SPLL_PDIV_A_MASK) >> SPLL_PDIV_A_SHIFT;
2865 
		fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT;
2866 
		clk_s = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM & CLK_S_MASK) >> CLK_S_SHIFT;
2867 
		clk_v = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM_2 & CLK_V_MASK) >> CLK_V_SHIFT;
2868 
 
2869 
		fb_div &= ~0x00001FFF;
2870 
		fb_div >>= 1;
2871 
		clk_v >>= 6;
2872 
 
2873 
		if (p_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT))
2874 
			ret = -EINVAL;
2875 
		if (fb_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT))
2876 
			ret = -EINVAL;
2877 
		if (clk_s & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT))
2878 
			ret = -EINVAL;
2879 
		if (clk_v & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT))
2880 
			ret = -EINVAL;
2881 
 
2882 
		if (ret)
2883 
			break;
2884 
 
2885 
		tmp = ((fb_div << SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK) |
2886 
			((p_div << SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK);
2887 
		spll_table->freq[i] = cpu_to_be32(tmp);
2888 
 
2889 
		tmp = ((clk_v << SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK) |
2890 
			((clk_s << SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK);
2891 
		spll_table->ss[i] = cpu_to_be32(tmp);
2892 
 
2893 
		sclk += 512;
2894 
	}
2895 
 
2896 
 
2897 
	if (!ret)
2898 
		ret = si_copy_bytes_to_smc(rdev, si_pi->spll_table_start,
2899 
					   (u8 *)spll_table, sizeof(SMC_SISLANDS_SPLL_DIV_TABLE),
2900 
					   si_pi->sram_end);
2901 
 
2902 
	if (ret)
2903 
		ni_pi->enable_power_containment = false;
2904 
 
2905 
	kfree(spll_table);
2906 
 
2907 
	return ret;
2908 
}
2909 
 
2910 
static void si_apply_state_adjust_rules(struct radeon_device *rdev,
2911 
					struct radeon_ps *rps)
2912 
{
2913 
	struct ni_ps *ps = ni_get_ps(rps);
2914 
	struct radeon_clock_and_voltage_limits *max_limits;
2915 
	bool disable_mclk_switching = false;
2916 
	bool disable_sclk_switching = false;
2917 
	u32 mclk, sclk;
2918 
	u16 vddc, vddci;
2919 
	u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc;
2920 
	int i;
2921 
 
2922 
	if ((rdev->pm.dpm.new_active_crtc_count > 1) ||
2923 
	    ni_dpm_vblank_too_short(rdev))
2924 
		disable_mclk_switching = true;
2925 
 
2926 
	if (rps->vclk || rps->dclk) {
2927 
		disable_mclk_switching = true;
2928 
		disable_sclk_switching = true;
2929 
	}
2930 
 
2931 
	if (rdev->pm.dpm.ac_power)
2932 
		max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
2933 
	else
2934 
		max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
2935 
 
2936 
	for (i = ps->performance_level_count - 2; i >= 0; i--) {
2937 
		if (ps->performance_levels[i].vddc > ps->performance_levels[i+1].vddc)
2938 
			ps->performance_levels[i].vddc = ps->performance_levels[i+1].vddc;
2939 
	}
2940 
	if (rdev->pm.dpm.ac_power == false) {
2941 
		for (i = 0; i < ps->performance_level_count; i++) {
2942 
			if (ps->performance_levels[i].mclk > max_limits->mclk)
2943 
				ps->performance_levels[i].mclk = max_limits->mclk;
2944 
			if (ps->performance_levels[i].sclk > max_limits->sclk)
2945 
				ps->performance_levels[i].sclk = max_limits->sclk;
2946 
			if (ps->performance_levels[i].vddc > max_limits->vddc)
2947 
				ps->performance_levels[i].vddc = max_limits->vddc;
2948 
			if (ps->performance_levels[i].vddci > max_limits->vddci)
2949 
				ps->performance_levels[i].vddci = max_limits->vddci;
2950 
		}
2951 
	}
2952 
 
2953 
	/* limit clocks to max supported clocks based on voltage dependency tables */
2954 
	btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
2955 
							&max_sclk_vddc);
2956 
	btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
2957 
							&max_mclk_vddci);
2958 
	btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
2959 
							&max_mclk_vddc);
2960 
 
2961 
	for (i = 0; i < ps->performance_level_count; i++) {
2962 
		if (max_sclk_vddc) {
2963 
			if (ps->performance_levels[i].sclk > max_sclk_vddc)
2964 
				ps->performance_levels[i].sclk = max_sclk_vddc;
2965 
		}
2966 
		if (max_mclk_vddci) {
2967 
			if (ps->performance_levels[i].mclk > max_mclk_vddci)
2968 
				ps->performance_levels[i].mclk = max_mclk_vddci;
2969 
		}
2970 
		if (max_mclk_vddc) {
2971 
			if (ps->performance_levels[i].mclk > max_mclk_vddc)
2972 
				ps->performance_levels[i].mclk = max_mclk_vddc;
2973 
		}
2974 
	}
2975 
 
2976 
	/* XXX validate the min clocks required for display */
2977 
 
2978 
	if (disable_mclk_switching) {
2979 
		mclk  = ps->performance_levels[ps->performance_level_count - 1].mclk;
2980 
		vddci = ps->performance_levels[ps->performance_level_count - 1].vddci;
2981 
	} else {
2982 
		mclk = ps->performance_levels[0].mclk;
2983 
		vddci = ps->performance_levels[0].vddci;
2984 
	}
2985 
 
2986 
	if (disable_sclk_switching) {
2987 
		sclk = ps->performance_levels[ps->performance_level_count - 1].sclk;
2988 
		vddc = ps->performance_levels[ps->performance_level_count - 1].vddc;
2989 
	} else {
2990 
		sclk = ps->performance_levels[0].sclk;
2991 
		vddc = ps->performance_levels[0].vddc;
2992 
	}
2993 
 
2994 
	/* adjusted low state */
2995 
	ps->performance_levels[0].sclk = sclk;
2996 
	ps->performance_levels[0].mclk = mclk;
2997 
	ps->performance_levels[0].vddc = vddc;
2998 
	ps->performance_levels[0].vddci = vddci;
2999 
 
3000 
	if (disable_sclk_switching) {
3001 
		sclk = ps->performance_levels[0].sclk;
3002 
		for (i = 1; i < ps->performance_level_count; i++) {
3003 
			if (sclk < ps->performance_levels[i].sclk)
3004 
				sclk = ps->performance_levels[i].sclk;
3005 
		}
3006 
		for (i = 0; i < ps->performance_level_count; i++) {
3007 
			ps->performance_levels[i].sclk = sclk;
3008 
			ps->performance_levels[i].vddc = vddc;
3009 
		}
3010 
	} else {
3011 
		for (i = 1; i < ps->performance_level_count; i++) {
3012 
			if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk)
3013 
				ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk;
3014 
			if (ps->performance_levels[i].vddc < ps->performance_levels[i - 1].vddc)
3015 
				ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc;
3016 
		}
3017 
	}
3018 
 
3019 
	if (disable_mclk_switching) {
3020 
		mclk = ps->performance_levels[0].mclk;
3021 
		for (i = 1; i < ps->performance_level_count; i++) {
3022 
			if (mclk < ps->performance_levels[i].mclk)
3023 
				mclk = ps->performance_levels[i].mclk;
3024 
		}
3025 
		for (i = 0; i < ps->performance_level_count; i++) {
3026 
			ps->performance_levels[i].mclk = mclk;
3027 
			ps->performance_levels[i].vddci = vddci;
3028 
		}
3029 
	} else {
3030 
		for (i = 1; i < ps->performance_level_count; i++) {
3031 
			if (ps->performance_levels[i].mclk < ps->performance_levels[i - 1].mclk)
3032 
				ps->performance_levels[i].mclk = ps->performance_levels[i - 1].mclk;
3033 
			if (ps->performance_levels[i].vddci < ps->performance_levels[i - 1].vddci)
3034 
				ps->performance_levels[i].vddci = ps->performance_levels[i - 1].vddci;
3035 
		}
3036 
	}
3037 
 
3038 
        for (i = 0; i < ps->performance_level_count; i++)
3039 
                btc_adjust_clock_combinations(rdev, max_limits,
3040 
                                              &ps->performance_levels[i]);
3041 
 
3042 
	for (i = 0; i < ps->performance_level_count; i++) {
3043 
		btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
3044 
						   ps->performance_levels[i].sclk,
3045 
						   max_limits->vddc,  &ps->performance_levels[i].vddc);
3046 
		btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
3047 
						   ps->performance_levels[i].mclk,
3048 
						   max_limits->vddci, &ps->performance_levels[i].vddci);
3049 
		btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
3050 
						   ps->performance_levels[i].mclk,
3051 
						   max_limits->vddc,  &ps->performance_levels[i].vddc);
3052 
		btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk,
3053 
						   rdev->clock.current_dispclk,
3054 
						   max_limits->vddc,  &ps->performance_levels[i].vddc);
3055 
	}
3056 
 
3057 
	for (i = 0; i < ps->performance_level_count; i++) {
3058 
		btc_apply_voltage_delta_rules(rdev,
3059 
					      max_limits->vddc, max_limits->vddci,
3060 
					      &ps->performance_levels[i].vddc,
3061 
					      &ps->performance_levels[i].vddci);
3062 
	}
3063 
 
3064 
	ps->dc_compatible = true;
3065 
	for (i = 0; i < ps->performance_level_count; i++) {
3066 
		if (ps->performance_levels[i].vddc > rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc)
3067 
			ps->dc_compatible = false;
3068 
	}
3069 
 
3070 
}
3071 
 
3072 
#if 0
3073 
static int si_read_smc_soft_register(struct radeon_device *rdev,
3074 
				     u16 reg_offset, u32 *value)
3075 
{
3076 
	struct si_power_info *si_pi = si_get_pi(rdev);
3077 
 
3078 
	return si_read_smc_sram_dword(rdev,
3079 
				      si_pi->soft_regs_start + reg_offset, value,
3080 
				      si_pi->sram_end);
3081 
}
3082 
#endif
3083 
 
3084 
static int si_write_smc_soft_register(struct radeon_device *rdev,
3085 
				      u16 reg_offset, u32 value)
3086 
{
3087 
	struct si_power_info *si_pi = si_get_pi(rdev);
3088 
 
3089 
	return si_write_smc_sram_dword(rdev,
3090 
				       si_pi->soft_regs_start + reg_offset,
3091 
				       value, si_pi->sram_end);
3092 
}
3093 
 
3094 
static bool si_is_special_1gb_platform(struct radeon_device *rdev)
3095 
{
3096 
	bool ret = false;
3097 
	u32 tmp, width, row, column, bank, density;
3098 
	bool is_memory_gddr5, is_special;
3099 
 
3100 
	tmp = RREG32(MC_SEQ_MISC0);
3101 
	is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE == ((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT));
3102 
	is_special = (MC_SEQ_MISC0_REV_ID_VALUE == ((tmp & MC_SEQ_MISC0_REV_ID_MASK) >> MC_SEQ_MISC0_REV_ID_SHIFT))
3103 
		& (MC_SEQ_MISC0_VEN_ID_VALUE == ((tmp & MC_SEQ_MISC0_VEN_ID_MASK) >> MC_SEQ_MISC0_VEN_ID_SHIFT));
3104 
 
3105 
	WREG32(MC_SEQ_IO_DEBUG_INDEX, 0xb);
3106 
	width = ((RREG32(MC_SEQ_IO_DEBUG_DATA) >> 1) & 1) ? 16 : 32;
3107 
 
3108 
	tmp = RREG32(MC_ARB_RAMCFG);
3109 
	row = ((tmp & NOOFROWS_MASK) >> NOOFROWS_SHIFT) + 10;
3110 
	column = ((tmp & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) + 8;
3111 
	bank = ((tmp & NOOFBANK_MASK) >> NOOFBANK_SHIFT) + 2;
3112 
 
3113 
	density = (1 << (row + column - 20 + bank)) * width;
3114 
 
3115 
	if ((rdev->pdev->device == 0x6819) &&
3116 
	    is_memory_gddr5 && is_special && (density == 0x400))
3117 
		ret = true;
3118 
 
3119 
	return ret;
3120 
}
3121 
 
3122 
static void si_get_leakage_vddc(struct radeon_device *rdev)
3123 
{
3124 
	struct si_power_info *si_pi = si_get_pi(rdev);
3125 
	u16 vddc, count = 0;
3126 
	int i, ret;
3127 
 
3128 
	for (i = 0; i < SISLANDS_MAX_LEAKAGE_COUNT; i++) {
3129 
		ret = radeon_atom_get_leakage_vddc_based_on_leakage_idx(rdev, &vddc, SISLANDS_LEAKAGE_INDEX0 + i);
3130 
 
3131 
		if (!ret && (vddc > 0) && (vddc != (SISLANDS_LEAKAGE_INDEX0 + i))) {
3132 
			si_pi->leakage_voltage.entries[count].voltage = vddc;
3133 
			si_pi->leakage_voltage.entries[count].leakage_index =
3134 
				SISLANDS_LEAKAGE_INDEX0 + i;
3135 
			count++;
3136 
		}
3137 
	}
3138 
	si_pi->leakage_voltage.count = count;
3139 
}
3140 
 
3141 
static int si_get_leakage_voltage_from_leakage_index(struct radeon_device *rdev,
3142 
						     u32 index, u16 *leakage_voltage)
3143 
{
3144 
	struct si_power_info *si_pi = si_get_pi(rdev);
3145 
	int i;
3146 
 
3147 
	if (leakage_voltage == NULL)
3148 
		return -EINVAL;
3149 
 
3150 
	if ((index & 0xff00) != 0xff00)
3151 
		return -EINVAL;
3152 
 
3153 
	if ((index & 0xff) > SISLANDS_MAX_LEAKAGE_COUNT + 1)
3154 
		return -EINVAL;
3155 
 
3156 
	if (index < SISLANDS_LEAKAGE_INDEX0)
3157 
		return -EINVAL;
3158 
 
3159 
	for (i = 0; i < si_pi->leakage_voltage.count; i++) {
3160 
		if (si_pi->leakage_voltage.entries[i].leakage_index == index) {
3161 
			*leakage_voltage = si_pi->leakage_voltage.entries[i].voltage;
3162 
			return 0;
3163 
		}
3164 
	}
3165 
	return -EAGAIN;
3166 
}
3167 
 
3168 
static void si_set_dpm_event_sources(struct radeon_device *rdev, u32 sources)
3169 
{
3170 
	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3171 
	bool want_thermal_protection;
3172 
	enum radeon_dpm_event_src dpm_event_src;
3173 
 
3174 
	switch (sources) {
3175 
	case 0:
3176 
	default:
3177 
		want_thermal_protection = false;
3178 
                break;
3179 
	case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL):
3180 
		want_thermal_protection = true;
3181 
		dpm_event_src = RADEON_DPM_EVENT_SRC_DIGITAL;
3182 
		break;
3183 
	case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL):
3184 
		want_thermal_protection = true;
3185 
		dpm_event_src = RADEON_DPM_EVENT_SRC_EXTERNAL;
3186 
		break;
3187 
	case ((1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL) |
3188 
	      (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL)):
3189 
		want_thermal_protection = true;
3190 
		dpm_event_src = RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL;
3191 
		break;
3192 
	}
3193 
 
3194 
	if (want_thermal_protection) {
3195 
		WREG32_P(CG_THERMAL_CTRL, DPM_EVENT_SRC(dpm_event_src), ~DPM_EVENT_SRC_MASK);
3196 
		if (pi->thermal_protection)
3197 
			WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
3198 
	} else {
3199 
		WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
3200 
	}
3201 
}
3202 
 
3203 
static void si_enable_auto_throttle_source(struct radeon_device *rdev,
3204 
					   enum radeon_dpm_auto_throttle_src source,
3205 
					   bool enable)
3206 
{
3207 
	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3208 
 
3209 
	if (enable) {
3210 
		if (!(pi->active_auto_throttle_sources & (1 << source))) {
3211 
			pi->active_auto_throttle_sources |= 1 << source;
3212 
			si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
3213 
		}
3214 
	} else {
3215 
		if (pi->active_auto_throttle_sources & (1 << source)) {
3216 
			pi->active_auto_throttle_sources &= ~(1 << source);
3217 
			si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
3218 
		}
3219 
	}
3220 
}
3221 
 
3222 
static void si_start_dpm(struct radeon_device *rdev)
3223 
{
3224 
	WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN);
3225 
}
3226 
 
3227 
static void si_stop_dpm(struct radeon_device *rdev)
3228 
{
3229 
	WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN);
3230 
}
3231 
 
3232 
static void si_enable_sclk_control(struct radeon_device *rdev, bool enable)
3233 
{
3234 
	if (enable)
3235 
		WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF);
3236 
	else
3237 
		WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF);
3238 
 
3239 
}
3240 
 
3241 
#if 0
3242 
static int si_notify_hardware_of_thermal_state(struct radeon_device *rdev,
3243 
					       u32 thermal_level)
3244 
{
3245 
	PPSMC_Result ret;
3246 
 
3247 
	if (thermal_level == 0) {
3248 
		ret = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt);
3249 
		if (ret == PPSMC_Result_OK)
3250 
			return 0;
3251 
		else
3252 
			return -EINVAL;
3253 
	}
3254 
	return 0;
3255 
}
3256 
 
3257 
static void si_notify_hardware_vpu_recovery_event(struct radeon_device *rdev)
3258 
{
3259 
	si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_tdr_is_about_to_happen, true);
3260 
}
3261 
#endif
3262 
 
3263 
#if 0
3264 
static int si_notify_hw_of_powersource(struct radeon_device *rdev, bool ac_power)
3265 
{
3266 
	if (ac_power)
3267 
		return (si_send_msg_to_smc(rdev, PPSMC_MSG_RunningOnAC) == PPSMC_Result_OK) ?
3268 
 
3269 
 
3270 
	return 0;
3271 
}
3272 
#endif
3273 
 
3274 
static PPSMC_Result si_send_msg_to_smc_with_parameter(struct radeon_device *rdev,
3275 
						      PPSMC_Msg msg, u32 parameter)
3276 
{
3277 
	WREG32(SMC_SCRATCH0, parameter);
3278 
	return si_send_msg_to_smc(rdev, msg);
3279 
}
3280 
 
3281 
static int si_restrict_performance_levels_before_switch(struct radeon_device *rdev)
3282 
{
3283 
	if (si_send_msg_to_smc(rdev, PPSMC_MSG_NoForcedLevel) != PPSMC_Result_OK)
3284 
		return -EINVAL;
3285 
 
3286 
	return (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) == PPSMC_Result_OK) ?
3287 
 
3288 
}
3289 
 
3290 
int si_dpm_force_performance_level(struct radeon_device *rdev,
3291 
				   enum radeon_dpm_forced_level level)
3292 
{
3293 
	struct radeon_ps *rps = rdev->pm.dpm.current_ps;
3294 
	struct ni_ps *ps = ni_get_ps(rps);
3295 
	u32 levels = ps->performance_level_count;
3296 
 
3297 
	if (level == RADEON_DPM_FORCED_LEVEL_HIGH) {
3298 
		if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)
3299 
			return -EINVAL;
3300 
 
3301 
		if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 1) != PPSMC_Result_OK)
3302 
			return -EINVAL;
3303 
	} else if (level == RADEON_DPM_FORCED_LEVEL_LOW) {
3304 
		if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
3305 
			return -EINVAL;
3306 
 
3307 
		if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) != PPSMC_Result_OK)
3308 
			return -EINVAL;
3309 
	} else if (level == RADEON_DPM_FORCED_LEVEL_AUTO) {
3310 
		if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
3311 
			return -EINVAL;
3312 
 
3313 
		if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)
3314 
			return -EINVAL;
3315 
	}
3316 
 
3317 
	rdev->pm.dpm.forced_level = level;
3318 
 
3319 
	return 0;
3320 
}
3321 
 
3322 
static int si_set_boot_state(struct radeon_device *rdev)
3323 
{
3324 
	return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToInitialState) == PPSMC_Result_OK) ?
3325 
 
3326 
}
3327 
 
3328 
static int si_set_sw_state(struct radeon_device *rdev)
3329 
{
3330 
	return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToSwState) == PPSMC_Result_OK) ?
3331 
 
3332 
}
3333 
 
3334 
static int si_halt_smc(struct radeon_device *rdev)
3335 
{
3336 
	if (si_send_msg_to_smc(rdev, PPSMC_MSG_Halt) != PPSMC_Result_OK)
3337 
		return -EINVAL;
3338 
 
3339 
	return (si_wait_for_smc_inactive(rdev) == PPSMC_Result_OK) ?
3340 
 
3341 
}
3342 
 
3343 
static int si_resume_smc(struct radeon_device *rdev)
3344 
{
3345 
	if (si_send_msg_to_smc(rdev, PPSMC_FlushDataCache) != PPSMC_Result_OK)
3346 
		return -EINVAL;
3347 
 
3348 
	return (si_send_msg_to_smc(rdev, PPSMC_MSG_Resume) == PPSMC_Result_OK) ?
3349 
 
3350 
}
3351 
 
3352 
static void si_dpm_start_smc(struct radeon_device *rdev)
3353 
{
3354 
	si_program_jump_on_start(rdev);
3355 
	si_start_smc(rdev);
3356 
	si_start_smc_clock(rdev);
3357 
}
3358 
 
3359 
static void si_dpm_stop_smc(struct radeon_device *rdev)
3360 
{
3361 
	si_reset_smc(rdev);
3362 
	si_stop_smc_clock(rdev);
3363 
}
3364 
 
3365 
static int si_process_firmware_header(struct radeon_device *rdev)
3366 
{
3367 
	struct si_power_info *si_pi = si_get_pi(rdev);
3368 
	u32 tmp;
3369 
	int ret;
3370 
 
3371 
	ret = si_read_smc_sram_dword(rdev,
3372 
				     SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3373 
				     SISLANDS_SMC_FIRMWARE_HEADER_stateTable,
3374 
				     &tmp, si_pi->sram_end);
3375 
	if (ret)
3376 
		return ret;
3377 
 
3378 
        si_pi->state_table_start = tmp;
3379 
 
3380 
	ret = si_read_smc_sram_dword(rdev,
3381 
				     SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3382 
				     SISLANDS_SMC_FIRMWARE_HEADER_softRegisters,
3383 
				     &tmp, si_pi->sram_end);
3384 
	if (ret)
3385 
		return ret;
3386 
 
3387 
	si_pi->soft_regs_start = tmp;
3388 
 
3389 
	ret = si_read_smc_sram_dword(rdev,
3390 
				     SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3391 
				     SISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable,
3392 
				     &tmp, si_pi->sram_end);
3393 
	if (ret)
3394 
		return ret;
3395 
 
3396 
	si_pi->mc_reg_table_start = tmp;
3397 
 
3398 
	ret = si_read_smc_sram_dword(rdev,
3399 
				     SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3400 
				     SISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable,
3401 
				     &tmp, si_pi->sram_end);
3402 
	if (ret)
3403 
		return ret;
3404 
 
3405 
	si_pi->arb_table_start = tmp;
3406 
 
3407 
	ret = si_read_smc_sram_dword(rdev,
3408 
				     SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3409 
				     SISLANDS_SMC_FIRMWARE_HEADER_CacConfigTable,
3410 
				     &tmp, si_pi->sram_end);
3411 
	if (ret)
3412 
		return ret;
3413 
 
3414 
	si_pi->cac_table_start = tmp;
3415 
 
3416 
	ret = si_read_smc_sram_dword(rdev,
3417 
				     SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3418 
				     SISLANDS_SMC_FIRMWARE_HEADER_DteConfiguration,
3419 
				     &tmp, si_pi->sram_end);
3420 
	if (ret)
3421 
		return ret;
3422 
 
3423 
	si_pi->dte_table_start = tmp;
3424 
 
3425 
	ret = si_read_smc_sram_dword(rdev,
3426 
				     SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3427 
				     SISLANDS_SMC_FIRMWARE_HEADER_spllTable,
3428 
				     &tmp, si_pi->sram_end);
3429 
	if (ret)
3430 
		return ret;
3431 
 
3432 
	si_pi->spll_table_start = tmp;
3433 
 
3434 
	ret = si_read_smc_sram_dword(rdev,
3435 
				     SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3436 
				     SISLANDS_SMC_FIRMWARE_HEADER_PAPMParameters,
3437 
				     &tmp, si_pi->sram_end);
3438 
	if (ret)
3439 
		return ret;
3440 
 
3441 
	si_pi->papm_cfg_table_start = tmp;
3442 
 
3443 
	return ret;
3444 
}
3445 
 
3446 
static void si_read_clock_registers(struct radeon_device *rdev)
3447 
{
3448 
	struct si_power_info *si_pi = si_get_pi(rdev);
3449 
 
3450 
	si_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL);
3451 
	si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2);
3452 
	si_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3);
3453 
	si_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(CG_SPLL_FUNC_CNTL_4);
3454 
	si_pi->clock_registers.cg_spll_spread_spectrum = RREG32(CG_SPLL_SPREAD_SPECTRUM);
3455 
	si_pi->clock_registers.cg_spll_spread_spectrum_2 = RREG32(CG_SPLL_SPREAD_SPECTRUM_2);
3456 
	si_pi->clock_registers.dll_cntl = RREG32(DLL_CNTL);
3457 
	si_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL);
3458 
	si_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL);
3459 
	si_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL);
3460 
	si_pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL);
3461 
	si_pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1);
3462 
	si_pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2);
3463 
	si_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1);
3464 
	si_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2);
3465 
}
3466 
 
3467 
static void si_enable_thermal_protection(struct radeon_device *rdev,
3468 
					  bool enable)
3469 
{
3470 
	if (enable)
3471 
		WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
3472 
	else
3473 
		WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
3474 
}
3475 
 
3476 
static void si_enable_acpi_power_management(struct radeon_device *rdev)
3477 
{
3478 
	WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN);
3479 
}
3480 
 
3481 
#if 0
3482 
static int si_enter_ulp_state(struct radeon_device *rdev)
3483 
{
3484 
	WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower);
3485 
 
3486 
	udelay(25000);
3487 
 
3488 
	return 0;
3489 
}
3490 
 
3491 
static int si_exit_ulp_state(struct radeon_device *rdev)
3492 
{
3493 
	int i;
3494 
 
3495 
	WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower);
3496 
 
3497 
	udelay(7000);
3498 
 
3499 
	for (i = 0; i < rdev->usec_timeout; i++) {
3500 
		if (RREG32(SMC_RESP_0) == 1)
3501 
			break;
3502 
		udelay(1000);
3503 
	}
3504 
 
3505 
	return 0;
3506 
}
3507 
#endif
3508 
 
3509 
static int si_notify_smc_display_change(struct radeon_device *rdev,
3510 
				     bool has_display)
3511 
{
3512 
	PPSMC_Msg msg = has_display ?
3513 
		PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay;
3514 
 
3515 
	return (si_send_msg_to_smc(rdev, msg) == PPSMC_Result_OK) ?
3516 
 
3517 
}
3518 
 
3519 
static void si_program_response_times(struct radeon_device *rdev)
3520 
{
3521 
	u32 voltage_response_time, backbias_response_time, acpi_delay_time, vbi_time_out;
3522 
	u32 vddc_dly, acpi_dly, vbi_dly;
3523 
	u32 reference_clock;
3524 
 
3525 
	si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mvdd_chg_time, 1);
3526 
 
3527 
	voltage_response_time = (u32)rdev->pm.dpm.voltage_response_time;
3528 
        backbias_response_time = (u32)rdev->pm.dpm.backbias_response_time;
3529 
 
3530 
	if (voltage_response_time == 0)
3531 
		voltage_response_time = 1000;
3532 
 
3533 
	acpi_delay_time = 15000;
3534 
	vbi_time_out = 100000;
3535 
 
3536 
	reference_clock = radeon_get_xclk(rdev);
3537 
 
3538 
	vddc_dly = (voltage_response_time  * reference_clock) / 100;
3539 
	acpi_dly = (acpi_delay_time * reference_clock) / 100;
3540 
	vbi_dly  = (vbi_time_out * reference_clock) / 100;
3541 
 
3542 
	si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_vreg,  vddc_dly);
3543 
	si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_acpi,  acpi_dly);
3544 
	si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mclk_chg_timeout, vbi_dly);
3545 
	si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mc_block_delay, 0xAA);
3546 
}
3547 
 
3548 
static void si_program_ds_registers(struct radeon_device *rdev)
3549 
{
3550 
	struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3551 
	u32 tmp = 1; /* XXX: 0x10 on tahiti A0 */
3552 
 
3553 
	if (eg_pi->sclk_deep_sleep) {
3554 
		WREG32_P(MISC_CLK_CNTL, DEEP_SLEEP_CLK_SEL(tmp), ~DEEP_SLEEP_CLK_SEL_MASK);
3555 
		WREG32_P(CG_SPLL_AUTOSCALE_CNTL, AUTOSCALE_ON_SS_CLEAR,
3556 
			 ~AUTOSCALE_ON_SS_CLEAR);
3557 
	}
3558 
}
3559 
 
3560 
static void si_program_display_gap(struct radeon_device *rdev)
3561 
{
3562 
	u32 tmp, pipe;
3563 
	int i;
3564 
 
3565 
	tmp = RREG32(CG_DISPLAY_GAP_CNTL) & ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
3566 
	if (rdev->pm.dpm.new_active_crtc_count > 0)
3567 
		tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
3568 
	else
3569 
		tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE);
3570 
 
3571 
	if (rdev->pm.dpm.new_active_crtc_count > 1)
3572 
		tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
3573 
	else
3574 
		tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE);
3575 
 
3576 
	WREG32(CG_DISPLAY_GAP_CNTL, tmp);
3577 
 
3578 
	tmp = RREG32(DCCG_DISP_SLOW_SELECT_REG);
3579 
	pipe = (tmp & DCCG_DISP1_SLOW_SELECT_MASK) >> DCCG_DISP1_SLOW_SELECT_SHIFT;
3580 
 
3581 
	if ((rdev->pm.dpm.new_active_crtc_count > 0) &&
3582 
	    (!(rdev->pm.dpm.new_active_crtcs & (1 << pipe)))) {
3583 
		/* find the first active crtc */
3584 
		for (i = 0; i < rdev->num_crtc; i++) {
3585 
			if (rdev->pm.dpm.new_active_crtcs & (1 << i))
3586 
				break;
3587 
		}
3588 
		if (i == rdev->num_crtc)
3589 
			pipe = 0;
3590 
		else
3591 
			pipe = i;
3592 
 
3593 
		tmp &= ~DCCG_DISP1_SLOW_SELECT_MASK;
3594 
		tmp |= DCCG_DISP1_SLOW_SELECT(pipe);
3595 
		WREG32(DCCG_DISP_SLOW_SELECT_REG, tmp);
3596 
	}
3597 
 
3598 
	/* Setting this to false forces the performance state to low if the crtcs are disabled.
3599 
	 * This can be a problem on PowerXpress systems or if you want to use the card
3600 
	 * for offscreen rendering or compute if there are no crtcs enabled.
3601 
	 */
3602 
	si_notify_smc_display_change(rdev, rdev->pm.dpm.new_active_crtc_count > 0);
3603 
}
3604 
 
3605 
static void si_enable_spread_spectrum(struct radeon_device *rdev, bool enable)
3606 
{
3607 
	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3608 
 
3609 
	if (enable) {
3610 
		if (pi->sclk_ss)
3611 
			WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN);
3612 
	} else {
3613 
		WREG32_P(CG_SPLL_SPREAD_SPECTRUM, 0, ~SSEN);
3614 
		WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN);
3615 
	}
3616 
}
3617 
 
3618 
static void si_setup_bsp(struct radeon_device *rdev)
3619 
{
3620 
	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3621 
	u32 xclk = radeon_get_xclk(rdev);
3622 
 
3623 
	r600_calculate_u_and_p(pi->asi,
3624 
			       xclk,
3625 
			       16,
3626 
			       &pi->bsp,
3627 
			       &pi->bsu);
3628 
 
3629 
	r600_calculate_u_and_p(pi->pasi,
3630 
			       xclk,
3631 
			       16,
3632 
			       &pi->pbsp,
3633 
			       &pi->pbsu);
3634 
 
3635 
 
3636 
        pi->dsp = BSP(pi->bsp) | BSU(pi->bsu);
3637 
	pi->psp = BSP(pi->pbsp) | BSU(pi->pbsu);
3638 
 
3639 
	WREG32(CG_BSP, pi->dsp);
3640 
}
3641 
 
3642 
static void si_program_git(struct radeon_device *rdev)
3643 
{
3644 
	WREG32_P(CG_GIT, CG_GICST(R600_GICST_DFLT), ~CG_GICST_MASK);
3645 
}
3646 
 
3647 
static void si_program_tp(struct radeon_device *rdev)
3648 
{
3649 
	int i;
3650 
	enum r600_td td = R600_TD_DFLT;
3651 
 
3652 
	for (i = 0; i < R600_PM_NUMBER_OF_TC; i++)
3653 
		WREG32(CG_FFCT_0 + (i * 4), (UTC_0(r600_utc[i]) | DTC_0(r600_dtc[i])));
3654 
 
3655 
	if (td == R600_TD_AUTO)
3656 
		WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL);
3657 
	else
3658 
		WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL);
3659 
 
3660 
	if (td == R600_TD_UP)
3661 
		WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE);
3662 
 
3663 
	if (td == R600_TD_DOWN)
3664 
		WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE);
3665 
}
3666 
 
3667 
static void si_program_tpp(struct radeon_device *rdev)
3668 
{
3669 
	WREG32(CG_TPC, R600_TPC_DFLT);
3670 
}
3671 
 
3672 
static void si_program_sstp(struct radeon_device *rdev)
3673 
{
3674 
	WREG32(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT)));
3675 
}
3676 
 
3677 
static void si_enable_display_gap(struct radeon_device *rdev)
3678 
{
3679 
	u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);
3680 
 
3681 
	tmp &= ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
3682 
	tmp |= (DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE) |
3683 
		DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE));
3684 
 
3685 
	tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK);
3686 
	tmp |= (DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK) |
3687 
		DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE));
3688 
	WREG32(CG_DISPLAY_GAP_CNTL, tmp);
3689 
}
3690 
 
3691 
static void si_program_vc(struct radeon_device *rdev)
3692 
{
3693 
	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3694 
 
3695 
	WREG32(CG_FTV, pi->vrc);
3696 
}
3697 
 
3698 
static void si_clear_vc(struct radeon_device *rdev)
3699 
{
3700 
	WREG32(CG_FTV, 0);
3701 
}
3702 
 
3703 
u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock)
3704 
{
3705 
	u8 mc_para_index;
3706 
 
3707 
	if (memory_clock < 10000)
3708 
		mc_para_index = 0;
3709 
	else if (memory_clock >= 80000)
3710 
		mc_para_index = 0x0f;
3711 
	else
3712 
		mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1);
3713 
	return mc_para_index;
3714 
}
3715 
 
3716 
u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode)
3717 
{
3718 
	u8 mc_para_index;
3719 
 
3720 
	if (strobe_mode) {
3721 
		if (memory_clock < 12500)
3722 
			mc_para_index = 0x00;
3723 
		else if (memory_clock > 47500)
3724 
			mc_para_index = 0x0f;
3725 
		else
3726 
			mc_para_index = (u8)((memory_clock - 10000) / 2500);
3727 
	} else {
3728 
		if (memory_clock < 65000)
3729 
			mc_para_index = 0x00;
3730 
		else if (memory_clock > 135000)
3731 
			mc_para_index = 0x0f;
3732 
		else
3733 
			mc_para_index = (u8)((memory_clock - 60000) / 5000);
3734 
	}
3735 
	return mc_para_index;
3736 
}
3737 
 
3738 
static u8 si_get_strobe_mode_settings(struct radeon_device *rdev, u32 mclk)
3739 
{
3740 
	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3741 
	bool strobe_mode = false;
3742 
	u8 result = 0;
3743 
 
3744 
	if (mclk <= pi->mclk_strobe_mode_threshold)
3745 
		strobe_mode = true;
3746 
 
3747 
	if (pi->mem_gddr5)
3748 
		result = si_get_mclk_frequency_ratio(mclk, strobe_mode);
3749 
	else
3750 
		result = si_get_ddr3_mclk_frequency_ratio(mclk);
3751 
 
3752 
	if (strobe_mode)
3753 
		result |= SISLANDS_SMC_STROBE_ENABLE;
3754 
 
3755 
	return result;
3756 
}
3757 
 
3758 
static int si_upload_firmware(struct radeon_device *rdev)
3759 
{
3760 
	struct si_power_info *si_pi = si_get_pi(rdev);
3761 
	int ret;
3762 
 
3763 
	si_reset_smc(rdev);
3764 
	si_stop_smc_clock(rdev);
3765 
 
3766 
	ret = si_load_smc_ucode(rdev, si_pi->sram_end);
3767 
 
3768 
	return ret;
3769 
}
3770 
 
3771 
static bool si_validate_phase_shedding_tables(struct radeon_device *rdev,
3772 
					      const struct atom_voltage_table *table,
3773 
					      const struct radeon_phase_shedding_limits_table *limits)
3774 
{
3775 
	u32 data, num_bits, num_levels;
3776 
 
3777 
	if ((table == NULL) || (limits == NULL))
3778 
		return false;
3779 
 
3780 
	data = table->mask_low;
3781 
 
3782 
	num_bits = hweight32(data);
3783 
 
3784 
	if (num_bits == 0)
3785 
		return false;
3786 
 
3787 
	num_levels = (1 << num_bits);
3788 
 
3789 
	if (table->count != num_levels)
3790 
		return false;
3791 
 
3792 
	if (limits->count != (num_levels - 1))
3793 
		return false;
3794 
 
3795 
	return true;
3796 
}
3797 
 
3798 
void si_trim_voltage_table_to_fit_state_table(struct radeon_device *rdev,
3799 
					      u32 max_voltage_steps,
3800 
					      struct atom_voltage_table *voltage_table)
3801 
{
3802 
	unsigned int i, diff;
3803 
 
3804 
	if (voltage_table->count <= max_voltage_steps)
3805 
		return;
3806 
 
3807 
	diff = voltage_table->count - max_voltage_steps;
3808 
 
3809 
	for (i= 0; i < max_voltage_steps; i++)
3810 
		voltage_table->entries[i] = voltage_table->entries[i + diff];
3811 
 
3812 
	voltage_table->count = max_voltage_steps;
3813 
}
3814 
 
3815 
static int si_get_svi2_voltage_table(struct radeon_device *rdev,
3816 
				     struct radeon_clock_voltage_dependency_table *voltage_dependency_table,
3817 
				     struct atom_voltage_table *voltage_table)
3818 
{
3819 
	u32 i;
3820 
 
3821 
	if (voltage_dependency_table == NULL)
3822 
		return -EINVAL;
3823 
 
3824 
	voltage_table->mask_low = 0;
3825 
	voltage_table->phase_delay = 0;
3826 
 
3827 
	voltage_table->count = voltage_dependency_table->count;
3828 
	for (i = 0; i < voltage_table->count; i++) {
3829 
		voltage_table->entries[i].value = voltage_dependency_table->entries[i].v;
3830 
		voltage_table->entries[i].smio_low = 0;
3831 
	}
3832 
 
3833 
	return 0;
3834 
}
3835 
 
3836 
static int si_construct_voltage_tables(struct radeon_device *rdev)
3837 
{
3838 
	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3839 
	struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3840 
	struct si_power_info *si_pi = si_get_pi(rdev);
3841 
	int ret;
3842 
 
3843 
	if (pi->voltage_control) {
3844 
		ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC,
3845 
						    VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddc_voltage_table);
3846 
		if (ret)
3847 
			return ret;
3848 
 
3849 
		if (eg_pi->vddc_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
3850 
			si_trim_voltage_table_to_fit_state_table(rdev,
3851 
								 SISLANDS_MAX_NO_VREG_STEPS,
3852 
								 &eg_pi->vddc_voltage_table);
3853 
	} else if (si_pi->voltage_control_svi2) {
3854 
		ret = si_get_svi2_voltage_table(rdev,
3855 
						&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
3856 
						&eg_pi->vddc_voltage_table);
3857 
		if (ret)
3858 
			return ret;
3859 
	} else {
3860 
		return -EINVAL;
3861 
	}
3862 
 
3863 
	if (eg_pi->vddci_control) {
3864 
		ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDCI,
3865 
						    VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddci_voltage_table);
3866 
		if (ret)
3867 
			return ret;
3868 
 
3869 
		if (eg_pi->vddci_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
3870 
			si_trim_voltage_table_to_fit_state_table(rdev,
3871 
								 SISLANDS_MAX_NO_VREG_STEPS,
3872 
								 &eg_pi->vddci_voltage_table);
3873 
	}
3874 
	if (si_pi->vddci_control_svi2) {
3875 
		ret = si_get_svi2_voltage_table(rdev,
3876 
						&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
3877 
						&eg_pi->vddci_voltage_table);
3878 
		if (ret)
3879 
			return ret;
3880 
	}
3881 
 
3882 
	if (pi->mvdd_control) {
3883 
		ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_MVDDC,
3884 
						    VOLTAGE_OBJ_GPIO_LUT, &si_pi->mvdd_voltage_table);
3885 
 
3886 
		if (ret) {
3887 
			pi->mvdd_control = false;
3888 
			return ret;
3889 
		}
3890 
 
3891 
		if (si_pi->mvdd_voltage_table.count == 0) {
3892 
			pi->mvdd_control = false;
3893 
			return -EINVAL;
3894 
		}
3895 
 
3896 
		if (si_pi->mvdd_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
3897 
			si_trim_voltage_table_to_fit_state_table(rdev,
3898 
								 SISLANDS_MAX_NO_VREG_STEPS,
3899 
								 &si_pi->mvdd_voltage_table);
3900 
	}
3901 
 
3902 
	if (si_pi->vddc_phase_shed_control) {
3903 
		ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC,
3904 
						    VOLTAGE_OBJ_PHASE_LUT, &si_pi->vddc_phase_shed_table);
3905 
		if (ret)
3906 
			si_pi->vddc_phase_shed_control = false;
3907 
 
3908 
		if ((si_pi->vddc_phase_shed_table.count == 0) ||
3909 
		    (si_pi->vddc_phase_shed_table.count > SISLANDS_MAX_NO_VREG_STEPS))
3910 
			si_pi->vddc_phase_shed_control = false;
3911 
	}
3912 
 
3913 
	return 0;
3914 
}
3915 
 
3916 
static void si_populate_smc_voltage_table(struct radeon_device *rdev,
3917 
					  const struct atom_voltage_table *voltage_table,
3918 
					  SISLANDS_SMC_STATETABLE *table)
3919 
{
3920 
	unsigned int i;
3921 
 
3922 
	for (i = 0; i < voltage_table->count; i++)
3923 
		table->lowSMIO[i] |= cpu_to_be32(voltage_table->entries[i].smio_low);
3924 
}
3925 
 
3926 
static int si_populate_smc_voltage_tables(struct radeon_device *rdev,
3927 
					  SISLANDS_SMC_STATETABLE *table)
3928 
{
3929 
	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3930 
	struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3931 
	struct si_power_info *si_pi = si_get_pi(rdev);
3932 
	u8 i;
3933 
 
3934 
	if (si_pi->voltage_control_svi2) {
3935 
		si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svc,
3936 
			si_pi->svc_gpio_id);
3937 
		si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svd,
3938 
			si_pi->svd_gpio_id);
3939 
		si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_plat_type,
3940 
					   2);
3941 
	} else {
3942 
		if (eg_pi->vddc_voltage_table.count) {
3943 
			si_populate_smc_voltage_table(rdev, &eg_pi->vddc_voltage_table, table);
3944 
			table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] =
3945 
				cpu_to_be32(eg_pi->vddc_voltage_table.mask_low);
3946 
 
3947 
			for (i = 0; i < eg_pi->vddc_voltage_table.count; i++) {
3948 
				if (pi->max_vddc_in_table <= eg_pi->vddc_voltage_table.entries[i].value) {
3949 
					table->maxVDDCIndexInPPTable = i;
3950 
					break;
3951 
				}
3952 
			}
3953 
		}
3954 
 
3955 
		if (eg_pi->vddci_voltage_table.count) {
3956 
			si_populate_smc_voltage_table(rdev, &eg_pi->vddci_voltage_table, table);
3957 
 
3958 
			table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDCI] =
3959 
				cpu_to_be32(eg_pi->vddci_voltage_table.mask_low);
3960 
		}
3961 
 
3962 
 
3963 
		if (si_pi->mvdd_voltage_table.count) {
3964 
			si_populate_smc_voltage_table(rdev, &si_pi->mvdd_voltage_table, table);
3965 
 
3966 
			table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_MVDD] =
3967 
				cpu_to_be32(si_pi->mvdd_voltage_table.mask_low);
3968 
		}
3969 
 
3970 
		if (si_pi->vddc_phase_shed_control) {
3971 
			if (si_validate_phase_shedding_tables(rdev, &si_pi->vddc_phase_shed_table,
3972 
							      &rdev->pm.dpm.dyn_state.phase_shedding_limits_table)) {
3973 
				si_populate_smc_voltage_table(rdev, &si_pi->vddc_phase_shed_table, table);
3974 
 
3975 
				table->phaseMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] =
3976 
					cpu_to_be32(si_pi->vddc_phase_shed_table.mask_low);
3977 
 
3978 
				si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_phase_shedding_delay,
3979 
							   (u32)si_pi->vddc_phase_shed_table.phase_delay);
3980 
			} else {
3981 
				si_pi->vddc_phase_shed_control = false;
3982 
			}
3983 
		}
3984 
	}
3985 
 
3986 
	return 0;
3987 
}
3988 
 
3989 
static int si_populate_voltage_value(struct radeon_device *rdev,
3990 
				     const struct atom_voltage_table *table,
3991 
				     u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage)
3992 
{
3993 
	unsigned int i;
3994 
 
3995 
	for (i = 0; i < table->count; i++) {
3996 
		if (value <= table->entries[i].value) {
3997 
			voltage->index = (u8)i;
3998 
			voltage->value = cpu_to_be16(table->entries[i].value);
3999 
			break;
4000 
		}
4001 
	}
4002 
 
4003 
	if (i >= table->count)
4004 
		return -EINVAL;
4005 
 
4006 
	return 0;
4007 
}
4008 
 
4009 
static int si_populate_mvdd_value(struct radeon_device *rdev, u32 mclk,
4010 
				  SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4011 
{
4012 
	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4013 
	struct si_power_info *si_pi = si_get_pi(rdev);
4014 
 
4015 
	if (pi->mvdd_control) {
4016 
		if (mclk <= pi->mvdd_split_frequency)
4017 
			voltage->index = 0;
4018 
		else
4019 
			voltage->index = (u8)(si_pi->mvdd_voltage_table.count) - 1;
4020 
 
4021 
		voltage->value = cpu_to_be16(si_pi->mvdd_voltage_table.entries[voltage->index].value);
4022 
	}
4023 
	return 0;
4024 
}
4025 
 
4026 
static int si_get_std_voltage_value(struct radeon_device *rdev,
4027 
				    SISLANDS_SMC_VOLTAGE_VALUE *voltage,
4028 
				    u16 *std_voltage)
4029 
{
4030 
	u16 v_index;
4031 
	bool voltage_found = false;
4032 
	*std_voltage = be16_to_cpu(voltage->value);
4033 
 
4034 
	if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries) {
4035 
		if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE) {
4036 
			if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL)
4037 
				return -EINVAL;
4038 
 
4039 
			for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
4040 
				if (be16_to_cpu(voltage->value) ==
4041 
				    (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
4042 
					voltage_found = true;
4043 
					if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
4044 
						*std_voltage =
4045 
							rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;
4046 
					else
4047 
						*std_voltage =
4048 
							rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc;
4049 
					break;
4050 
				}
4051 
			}
4052 
 
4053 
			if (!voltage_found) {
4054 
				for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
4055 
					if (be16_to_cpu(voltage->value) <=
4056 
					    (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
4057 
						voltage_found = true;
4058 
						if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
4059 
							*std_voltage =
4060 
								rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;
4061 
						else
4062 
							*std_voltage =
4063 
								rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc;
4064 
						break;
4065 
					}
4066 
				}
4067 
			}
4068 
		} else {
4069 
			if ((u32)voltage->index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
4070 
				*std_voltage = rdev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc;
4071 
		}
4072 
	}
4073 
 
4074 
	return 0;
4075 
}
4076 
 
4077 
static int si_populate_std_voltage_value(struct radeon_device *rdev,
4078 
					 u16 value, u8 index,
4079 
					 SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4080 
{
4081 
	voltage->index = index;
4082 
	voltage->value = cpu_to_be16(value);
4083 
 
4084 
	return 0;
4085 
}
4086 
 
4087 
static int si_populate_phase_shedding_value(struct radeon_device *rdev,
4088 
					    const struct radeon_phase_shedding_limits_table *limits,
4089 
					    u16 voltage, u32 sclk, u32 mclk,
4090 
					    SISLANDS_SMC_VOLTAGE_VALUE *smc_voltage)
4091 
{
4092 
	unsigned int i;
4093 
 
4094 
	for (i = 0; i < limits->count; i++) {
4095 
		if ((voltage <= limits->entries[i].voltage) &&
4096 
		    (sclk <= limits->entries[i].sclk) &&
4097 
		    (mclk <= limits->entries[i].mclk))
4098 
			break;
4099 
	}
4100 
 
4101 
	smc_voltage->phase_settings = (u8)i;
4102 
 
4103 
	return 0;
4104 
}
4105 
 
4106 
static int si_init_arb_table_index(struct radeon_device *rdev)
4107 
{
4108 
	struct si_power_info *si_pi = si_get_pi(rdev);
4109 
	u32 tmp;
4110 
	int ret;
4111 
 
4112 
	ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start, &tmp, si_pi->sram_end);
4113 
	if (ret)
4114 
		return ret;
4115 
 
4116 
	tmp &= 0x00FFFFFF;
4117 
	tmp |= MC_CG_ARB_FREQ_F1 << 24;
4118 
 
4119 
	return si_write_smc_sram_dword(rdev, si_pi->arb_table_start,  tmp, si_pi->sram_end);
4120 
}
4121 
 
4122 
static int si_initial_switch_from_arb_f0_to_f1(struct radeon_device *rdev)
4123 
{
4124 
	return ni_copy_and_switch_arb_sets(rdev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
4125 
}
4126 
 
4127 
static int si_reset_to_default(struct radeon_device *rdev)
4128 
{
4129 
	return (si_send_msg_to_smc(rdev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ?
4130 
 
4131 
}
4132 
 
4133 
static int si_force_switch_to_arb_f0(struct radeon_device *rdev)
4134 
{
4135 
	struct si_power_info *si_pi = si_get_pi(rdev);
4136 
	u32 tmp;
4137 
	int ret;
4138 
 
4139 
	ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start,
4140 
				     &tmp, si_pi->sram_end);
4141 
	if (ret)
4142 
		return ret;
4143 
 
4144 
	tmp = (tmp >> 24) & 0xff;
4145 
 
4146 
	if (tmp == MC_CG_ARB_FREQ_F0)
4147 
		return 0;
4148 
 
4149 
	return ni_copy_and_switch_arb_sets(rdev, tmp, MC_CG_ARB_FREQ_F0);
4150 
}
4151 
 
4152 
static u32 si_calculate_memory_refresh_rate(struct radeon_device *rdev,
4153 
					    u32 engine_clock)
4154 
{
4155 
	u32 dram_rows;
4156 
	u32 dram_refresh_rate;
4157 
	u32 mc_arb_rfsh_rate;
4158 
	u32 tmp = (RREG32(MC_ARB_RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
4159 
 
4160 
	if (tmp >= 4)
4161 
		dram_rows = 16384;
4162 
	else
4163 
		dram_rows = 1 << (tmp + 10);
4164 
 
4165 
	dram_refresh_rate = 1 << ((RREG32(MC_SEQ_MISC0) & 0x3) + 3);
4166 
	mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64;
4167 
 
4168 
	return mc_arb_rfsh_rate;
4169 
}
4170 
 
4171 
static int si_populate_memory_timing_parameters(struct radeon_device *rdev,
4172 
						struct rv7xx_pl *pl,
4173 
						SMC_SIslands_MCArbDramTimingRegisterSet *arb_regs)
4174 
{
4175 
	u32 dram_timing;
4176 
	u32 dram_timing2;
4177 
	u32 burst_time;
4178 
 
4179 
	arb_regs->mc_arb_rfsh_rate =
4180 
		(u8)si_calculate_memory_refresh_rate(rdev, pl->sclk);
4181 
 
4182 
	radeon_atom_set_engine_dram_timings(rdev,
4183 
					    pl->sclk,
4184 
                                            pl->mclk);
4185 
 
4186 
	dram_timing  = RREG32(MC_ARB_DRAM_TIMING);
4187 
	dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
4188 
	burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK;
4189 
 
4190 
	arb_regs->mc_arb_dram_timing  = cpu_to_be32(dram_timing);
4191 
	arb_regs->mc_arb_dram_timing2 = cpu_to_be32(dram_timing2);
4192 
	arb_regs->mc_arb_burst_time = (u8)burst_time;
4193 
 
4194 
	return 0;
4195 
}
4196 
 
4197 
static int si_do_program_memory_timing_parameters(struct radeon_device *rdev,
4198 
						  struct radeon_ps *radeon_state,
4199 
						  unsigned int first_arb_set)
4200 
{
4201 
	struct si_power_info *si_pi = si_get_pi(rdev);
4202 
	struct ni_ps *state = ni_get_ps(radeon_state);
4203 
	SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 };
4204 
	int i, ret = 0;
4205 
 
4206 
	for (i = 0; i < state->performance_level_count; i++) {
4207 
		ret = si_populate_memory_timing_parameters(rdev, &state->performance_levels[i], &arb_regs);
4208 
		if (ret)
4209 
			break;
4210 
		ret = si_copy_bytes_to_smc(rdev,
4211 
					   si_pi->arb_table_start +
4212 
					   offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) +
4213 
					   sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * (first_arb_set + i),
4214 
					   (u8 *)&arb_regs,
4215 
					   sizeof(SMC_SIslands_MCArbDramTimingRegisterSet),
4216 
					   si_pi->sram_end);
4217 
		if (ret)
4218 
			break;
4219 
        }
4220 
 
4221 
	return ret;
4222 
}
4223 
 
4224 
static int si_program_memory_timing_parameters(struct radeon_device *rdev,
4225 
					       struct radeon_ps *radeon_new_state)
4226 
{
4227 
	return si_do_program_memory_timing_parameters(rdev, radeon_new_state,
4228 
						      SISLANDS_DRIVER_STATE_ARB_INDEX);
4229 
}
4230 
 
4231 
static int si_populate_initial_mvdd_value(struct radeon_device *rdev,
4232 
					  struct SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4233 
{
4234 
	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4235 
	struct si_power_info *si_pi = si_get_pi(rdev);
4236 
 
4237 
	if (pi->mvdd_control)
4238 
		return si_populate_voltage_value(rdev, &si_pi->mvdd_voltage_table,
4239 
						 si_pi->mvdd_bootup_value, voltage);
4240 
 
4241 
	return 0;
4242 
}
4243 
 
4244 
static int si_populate_smc_initial_state(struct radeon_device *rdev,
4245 
					 struct radeon_ps *radeon_initial_state,
4246 
					 SISLANDS_SMC_STATETABLE *table)
4247 
{
4248 
	struct ni_ps *initial_state = ni_get_ps(radeon_initial_state);
4249 
	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4250 
	struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4251 
	struct si_power_info *si_pi = si_get_pi(rdev);
4252 
	u32 reg;
4253 
	int ret;
4254 
 
4255 
	table->initialState.levels[0].mclk.vDLL_CNTL =
4256 
		cpu_to_be32(si_pi->clock_registers.dll_cntl);
4257 
	table->initialState.levels[0].mclk.vMCLK_PWRMGT_CNTL =
4258 
		cpu_to_be32(si_pi->clock_registers.mclk_pwrmgt_cntl);
4259 
	table->initialState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =
4260 
		cpu_to_be32(si_pi->clock_registers.mpll_ad_func_cntl);
4261 
	table->initialState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL =
4262 
		cpu_to_be32(si_pi->clock_registers.mpll_dq_func_cntl);
4263 
	table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL =
4264 
		cpu_to_be32(si_pi->clock_registers.mpll_func_cntl);
4265 
	table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_1 =
4266 
		cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_1);
4267 
	table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_2 =
4268 
		cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_2);
4269 
	table->initialState.levels[0].mclk.vMPLL_SS =
4270 
		cpu_to_be32(si_pi->clock_registers.mpll_ss1);
4271 
	table->initialState.levels[0].mclk.vMPLL_SS2 =
4272 
		cpu_to_be32(si_pi->clock_registers.mpll_ss2);
4273 
 
4274 
	table->initialState.levels[0].mclk.mclk_value =
4275 
		cpu_to_be32(initial_state->performance_levels[0].mclk);
4276 
 
4277 
	table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
4278 
		cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl);
4279 
	table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
4280 
		cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_2);
4281 
	table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
4282 
		cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_3);
4283 
	table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =
4284 
		cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_4);
4285 
	table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM =
4286 
		cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum);
4287 
	table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2  =
4288 
		cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum_2);
4289 
 
4290 
	table->initialState.levels[0].sclk.sclk_value =
4291 
		cpu_to_be32(initial_state->performance_levels[0].sclk);
4292 
 
4293 
	table->initialState.levels[0].arbRefreshState =
4294 
		SISLANDS_INITIAL_STATE_ARB_INDEX;
4295 
 
4296 
	table->initialState.levels[0].ACIndex = 0;
4297 
 
4298 
	ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
4299 
					initial_state->performance_levels[0].vddc,
4300 
					&table->initialState.levels[0].vddc);
4301 
 
4302 
	if (!ret) {
4303 
		u16 std_vddc;
4304 
 
4305 
		ret = si_get_std_voltage_value(rdev,
4306 
					       &table->initialState.levels[0].vddc,
4307 
					       &std_vddc);
4308 
		if (!ret)
4309 
			si_populate_std_voltage_value(rdev, std_vddc,
4310 
						      table->initialState.levels[0].vddc.index,
4311 
						      &table->initialState.levels[0].std_vddc);
4312 
	}
4313 
 
4314 
	if (eg_pi->vddci_control)
4315 
		si_populate_voltage_value(rdev,
4316 
					  &eg_pi->vddci_voltage_table,
4317 
					  initial_state->performance_levels[0].vddci,
4318 
					  &table->initialState.levels[0].vddci);
4319 
 
4320 
	if (si_pi->vddc_phase_shed_control)
4321 
		si_populate_phase_shedding_value(rdev,
4322 
						 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
4323 
						 initial_state->performance_levels[0].vddc,
4324 
						 initial_state->performance_levels[0].sclk,
4325 
						 initial_state->performance_levels[0].mclk,
4326 
						 &table->initialState.levels[0].vddc);
4327 
 
4328 
	si_populate_initial_mvdd_value(rdev, &table->initialState.levels[0].mvdd);
4329 
 
4330 
	reg = CG_R(0xffff) | CG_L(0);
4331 
	table->initialState.levels[0].aT = cpu_to_be32(reg);
4332 
 
4333 
	table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp);
4334 
 
4335 
	table->initialState.levels[0].gen2PCIE = (u8)si_pi->boot_pcie_gen;
4336 
 
4337 
	if (pi->mem_gddr5) {
4338 
		table->initialState.levels[0].strobeMode =
4339 
			si_get_strobe_mode_settings(rdev,
4340 
						    initial_state->performance_levels[0].mclk);
4341 
 
4342 
		if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold)
4343 
			table->initialState.levels[0].mcFlags = SISLANDS_SMC_MC_EDC_RD_FLAG | SISLANDS_SMC_MC_EDC_WR_FLAG;
4344 
		else
4345 
			table->initialState.levels[0].mcFlags =  0;
4346 
	}
4347 
 
4348 
	table->initialState.levelCount = 1;
4349 
 
4350 
	table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC;
4351 
 
4352 
	table->initialState.levels[0].dpm2.MaxPS = 0;
4353 
	table->initialState.levels[0].dpm2.NearTDPDec = 0;
4354 
	table->initialState.levels[0].dpm2.AboveSafeInc = 0;
4355 
	table->initialState.levels[0].dpm2.BelowSafeInc = 0;
4356 
	table->initialState.levels[0].dpm2.PwrEfficiencyRatio = 0;
4357 
 
4358 
	reg = MIN_POWER_MASK | MAX_POWER_MASK;
4359 
	table->initialState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
4360 
 
4361 
	reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
4362 
	table->initialState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
4363 
 
4364 
	return 0;
4365 
}
4366 
 
4367 
static int si_populate_smc_acpi_state(struct radeon_device *rdev,
4368 
				      SISLANDS_SMC_STATETABLE *table)
4369 
{
4370 
	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4371 
	struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4372 
	struct si_power_info *si_pi = si_get_pi(rdev);
4373 
	u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;
4374 
	u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;
4375 
	u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;
4376 
	u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;
4377 
	u32 dll_cntl = si_pi->clock_registers.dll_cntl;
4378 
	u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;
4379 
	u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;
4380 
	u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;
4381 
	u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;
4382 
	u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;
4383 
	u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;
4384 
	u32 reg;
4385 
	int ret;
4386 
 
4387 
	table->ACPIState = table->initialState;
4388 
 
4389 
	table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC;
4390 
 
4391 
	if (pi->acpi_vddc) {
4392 
		ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
4393 
						pi->acpi_vddc, &table->ACPIState.levels[0].vddc);
4394 
		if (!ret) {
4395 
			u16 std_vddc;
4396 
 
4397 
			ret = si_get_std_voltage_value(rdev,
4398 
						       &table->ACPIState.levels[0].vddc, &std_vddc);
4399 
			if (!ret)
4400 
				si_populate_std_voltage_value(rdev, std_vddc,
4401 
							      table->ACPIState.levels[0].vddc.index,
4402 
							      &table->ACPIState.levels[0].std_vddc);
4403 
		}
4404 
		table->ACPIState.levels[0].gen2PCIE = si_pi->acpi_pcie_gen;
4405 
 
4406 
		if (si_pi->vddc_phase_shed_control) {
4407 
			si_populate_phase_shedding_value(rdev,
4408 
							 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
4409 
							 pi->acpi_vddc,
4410 
							 0,
4411 
							 0,
4412 
							 &table->ACPIState.levels[0].vddc);
4413 
		}
4414 
	} else {
4415 
		ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
4416 
						pi->min_vddc_in_table, &table->ACPIState.levels[0].vddc);
4417 
		if (!ret) {
4418 
			u16 std_vddc;
4419 
 
4420 
			ret = si_get_std_voltage_value(rdev,
4421 
						       &table->ACPIState.levels[0].vddc, &std_vddc);
4422 
 
4423 
			if (!ret)
4424 
				si_populate_std_voltage_value(rdev, std_vddc,
4425 
							      table->ACPIState.levels[0].vddc.index,
4426 
							      &table->ACPIState.levels[0].std_vddc);
4427 
		}
4428 
		table->ACPIState.levels[0].gen2PCIE = (u8)r600_get_pcie_gen_support(rdev,
4429 
										    si_pi->sys_pcie_mask,
4430 
										    si_pi->boot_pcie_gen,
4431 
										    RADEON_PCIE_GEN1);
4432 
 
4433 
		if (si_pi->vddc_phase_shed_control)
4434 
			si_populate_phase_shedding_value(rdev,
4435 
							 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
4436 
							 pi->min_vddc_in_table,
4437 
							 0,
4438 
							 0,
4439 
							 &table->ACPIState.levels[0].vddc);
4440 
	}
4441 
 
4442 
	if (pi->acpi_vddc) {
4443 
		if (eg_pi->acpi_vddci)
4444 
			si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table,
4445 
						  eg_pi->acpi_vddci,
4446 
						  &table->ACPIState.levels[0].vddci);
4447 
	}
4448 
 
4449 
	mclk_pwrmgt_cntl |= MRDCK0_RESET | MRDCK1_RESET;
4450 
	mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
4451 
 
4452 
	dll_cntl &= ~(MRDCK0_BYPASS | MRDCK1_BYPASS);
4453 
 
4454 
	spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
4455 
	spll_func_cntl_2 |= SCLK_MUX_SEL(4);
4456 
 
4457 
	table->ACPIState.levels[0].mclk.vDLL_CNTL =
4458 
		cpu_to_be32(dll_cntl);
4459 
	table->ACPIState.levels[0].mclk.vMCLK_PWRMGT_CNTL =
4460 
		cpu_to_be32(mclk_pwrmgt_cntl);
4461 
	table->ACPIState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =
4462 
		cpu_to_be32(mpll_ad_func_cntl);
4463 
	table->ACPIState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL =
4464 
		cpu_to_be32(mpll_dq_func_cntl);
4465 
	table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL =
4466 
		cpu_to_be32(mpll_func_cntl);
4467 
	table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_1 =
4468 
		cpu_to_be32(mpll_func_cntl_1);
4469 
	table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_2 =
4470 
		cpu_to_be32(mpll_func_cntl_2);
4471 
	table->ACPIState.levels[0].mclk.vMPLL_SS =
4472 
		cpu_to_be32(si_pi->clock_registers.mpll_ss1);
4473 
	table->ACPIState.levels[0].mclk.vMPLL_SS2 =
4474 
		cpu_to_be32(si_pi->clock_registers.mpll_ss2);
4475 
 
4476 
	table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
4477 
		cpu_to_be32(spll_func_cntl);
4478 
	table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
4479 
		cpu_to_be32(spll_func_cntl_2);
4480 
	table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
4481 
		cpu_to_be32(spll_func_cntl_3);
4482 
	table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =
4483 
		cpu_to_be32(spll_func_cntl_4);
4484 
 
4485 
	table->ACPIState.levels[0].mclk.mclk_value = 0;
4486 
	table->ACPIState.levels[0].sclk.sclk_value = 0;
4487 
 
4488 
	si_populate_mvdd_value(rdev, 0, &table->ACPIState.levels[0].mvdd);
4489 
 
4490 
	if (eg_pi->dynamic_ac_timing)
4491 
		table->ACPIState.levels[0].ACIndex = 0;
4492 
 
4493 
	table->ACPIState.levels[0].dpm2.MaxPS = 0;
4494 
	table->ACPIState.levels[0].dpm2.NearTDPDec = 0;
4495 
	table->ACPIState.levels[0].dpm2.AboveSafeInc = 0;
4496 
	table->ACPIState.levels[0].dpm2.BelowSafeInc = 0;
4497 
	table->ACPIState.levels[0].dpm2.PwrEfficiencyRatio = 0;
4498 
 
4499 
	reg = MIN_POWER_MASK | MAX_POWER_MASK;
4500 
	table->ACPIState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
4501 
 
4502 
	reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
4503 
	table->ACPIState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
4504 
 
4505 
	return 0;
4506 
}
4507 
 
4508 
static int si_populate_ulv_state(struct radeon_device *rdev,
4509 
				 SISLANDS_SMC_SWSTATE *state)
4510 
{
4511 
	struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4512 
	struct si_power_info *si_pi = si_get_pi(rdev);
4513 
	struct si_ulv_param *ulv = &si_pi->ulv;
4514 
	u32 sclk_in_sr = 1350; /* ??? */
4515 
	int ret;
4516 
 
4517 
	ret = si_convert_power_level_to_smc(rdev, &ulv->pl,
4518 
					    &state->levels[0]);
4519 
	if (!ret) {
4520 
		if (eg_pi->sclk_deep_sleep) {
4521 
			if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ)
4522 
				state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS;
4523 
			else
4524 
				state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE;
4525 
		}
4526 
		if (ulv->one_pcie_lane_in_ulv)
4527 
			state->flags |= PPSMC_SWSTATE_FLAG_PCIE_X1;
4528 
		state->levels[0].arbRefreshState = (u8)(SISLANDS_ULV_STATE_ARB_INDEX);
4529 
		state->levels[0].ACIndex = 1;
4530 
		state->levels[0].std_vddc = state->levels[0].vddc;
4531 
		state->levelCount = 1;
4532 
 
4533 
		state->flags |= PPSMC_SWSTATE_FLAG_DC;
4534 
	}
4535 
 
4536 
	return ret;
4537 
}
4538 
 
4539 
static int si_program_ulv_memory_timing_parameters(struct radeon_device *rdev)
4540 
{
4541 
	struct si_power_info *si_pi = si_get_pi(rdev);
4542 
	struct si_ulv_param *ulv = &si_pi->ulv;
4543 
	SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 };
4544 
	int ret;
4545 
 
4546 
	ret = si_populate_memory_timing_parameters(rdev, &ulv->pl,
4547 
						   &arb_regs);
4548 
	if (ret)
4549 
		return ret;
4550 
 
4551 
	si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ulv_volt_change_delay,
4552 
				   ulv->volt_change_delay);
4553 
 
4554 
	ret = si_copy_bytes_to_smc(rdev,
4555 
				   si_pi->arb_table_start +
4556 
				   offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) +
4557 
				   sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * SISLANDS_ULV_STATE_ARB_INDEX,
4558 
				   (u8 *)&arb_regs,
4559 
				   sizeof(SMC_SIslands_MCArbDramTimingRegisterSet),
4560 
				   si_pi->sram_end);
4561 
 
4562 
	return ret;
4563 
}
4564 
 
4565 
static void si_get_mvdd_configuration(struct radeon_device *rdev)
4566 
{
4567 
	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4568 
 
4569 
	pi->mvdd_split_frequency = 30000;
4570 
}
4571 
 
4572 
static int si_init_smc_table(struct radeon_device *rdev)
4573 
{
4574 
	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4575 
	struct si_power_info *si_pi = si_get_pi(rdev);
4576 
	struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps;
4577 
	const struct si_ulv_param *ulv = &si_pi->ulv;
4578 
	SISLANDS_SMC_STATETABLE  *table = &si_pi->smc_statetable;
4579 
	int ret;
4580 
	u32 lane_width;
4581 
	u32 vr_hot_gpio;
4582 
 
4583 
	si_populate_smc_voltage_tables(rdev, table);
4584 
 
4585 
	switch (rdev->pm.int_thermal_type) {
4586 
	case THERMAL_TYPE_SI:
4587 
	case THERMAL_TYPE_EMC2103_WITH_INTERNAL:
4588 
		table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL;
4589 
		break;
4590 
	case THERMAL_TYPE_NONE:
4591 
		table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE;
4592 
		break;
4593 
	default:
4594 
		table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL;
4595 
		break;
4596 
	}
4597 
 
4598 
	if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC)
4599 
		table->systemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
4600 
 
4601 
	if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) {
4602 
		if ((rdev->pdev->device != 0x6818) && (rdev->pdev->device != 0x6819))
4603 
			table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT;
4604 
	}
4605 
 
4606 
	if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
4607 
		table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
4608 
 
4609 
	if (pi->mem_gddr5)
4610 
		table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
4611 
 
4612 
	if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY)
4613 
		table->extraFlags |= PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH;
4614 
 
4615 
	if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE) {
4616 
		table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT_PROG_GPIO;
4617 
		vr_hot_gpio = rdev->pm.dpm.backbias_response_time;
4618 
		si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_vr_hot_gpio,
4619 
					   vr_hot_gpio);
4620 
	}
4621 
 
4622 
	ret = si_populate_smc_initial_state(rdev, radeon_boot_state, table);
4623 
	if (ret)
4624 
		return ret;
4625 
 
4626 
	ret = si_populate_smc_acpi_state(rdev, table);
4627 
	if (ret)
4628 
		return ret;
4629 
 
4630 
	table->driverState = table->initialState;
4631 
 
4632 
	ret = si_do_program_memory_timing_parameters(rdev, radeon_boot_state,
4633 
						     SISLANDS_INITIAL_STATE_ARB_INDEX);
4634 
	if (ret)
4635 
		return ret;
4636 
 
4637 
	if (ulv->supported && ulv->pl.vddc) {
4638 
		ret = si_populate_ulv_state(rdev, &table->ULVState);
4639 
		if (ret)
4640 
			return ret;
4641 
 
4642 
		ret = si_program_ulv_memory_timing_parameters(rdev);
4643 
		if (ret)
4644 
			return ret;
4645 
 
4646 
		WREG32(CG_ULV_CONTROL, ulv->cg_ulv_control);
4647 
		WREG32(CG_ULV_PARAMETER, ulv->cg_ulv_parameter);
4648 
 
4649 
		lane_width = radeon_get_pcie_lanes(rdev);
4650 
		si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
4651 
	} else {
4652 
		table->ULVState = table->initialState;
4653 
	}
4654 
 
4655 
	return si_copy_bytes_to_smc(rdev, si_pi->state_table_start,
4656 
				    (u8 *)table, sizeof(SISLANDS_SMC_STATETABLE),
4657 
				    si_pi->sram_end);
4658 
}
4659 
 
4660 
static int si_calculate_sclk_params(struct radeon_device *rdev,
4661 
				    u32 engine_clock,
4662 
				    SISLANDS_SMC_SCLK_VALUE *sclk)
4663 
{
4664 
	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4665 
	struct si_power_info *si_pi = si_get_pi(rdev);
4666 
	struct atom_clock_dividers dividers;
4667 
	u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;
4668 
	u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;
4669 
	u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;
4670 
	u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;
4671 
	u32 cg_spll_spread_spectrum = si_pi->clock_registers.cg_spll_spread_spectrum;
4672 
	u32 cg_spll_spread_spectrum_2 = si_pi->clock_registers.cg_spll_spread_spectrum_2;
4673 
	u64 tmp;
4674 
	u32 reference_clock = rdev->clock.spll.reference_freq;
4675 
	u32 reference_divider;
4676 
	u32 fbdiv;
4677 
	int ret;
4678 
 
4679 
	ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
4680 
					     engine_clock, false, ÷rs);
4681 
	if (ret)
4682 
		return ret;
4683 
 
4684 
	reference_divider = 1 + dividers.ref_div;
4685 
 
4686 
	tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384;
4687 
	do_div(tmp, reference_clock);
4688 
	fbdiv = (u32) tmp;
4689 
 
4690 
	spll_func_cntl &= ~(SPLL_PDIV_A_MASK | SPLL_REF_DIV_MASK);
4691 
	spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div);
4692 
	spll_func_cntl |= SPLL_PDIV_A(dividers.post_div);
4693 
 
4694 
	spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
4695 
	spll_func_cntl_2 |= SCLK_MUX_SEL(2);
4696 
 
4697 
        spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK;
4698 
        spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv);
4699 
        spll_func_cntl_3 |= SPLL_DITHEN;
4700 
 
4701 
	if (pi->sclk_ss) {
4702 
		struct radeon_atom_ss ss;
4703 
		u32 vco_freq = engine_clock * dividers.post_div;
4704 
 
4705 
		if (radeon_atombios_get_asic_ss_info(rdev, &ss,
4706 
						     ASIC_INTERNAL_ENGINE_SS, vco_freq)) {
4707 
			u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);
4708 
			u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);
4709 
 
4710 
			cg_spll_spread_spectrum &= ~CLK_S_MASK;
4711 
			cg_spll_spread_spectrum |= CLK_S(clk_s);
4712 
			cg_spll_spread_spectrum |= SSEN;
4713 
 
4714 
			cg_spll_spread_spectrum_2 &= ~CLK_V_MASK;
4715 
			cg_spll_spread_spectrum_2 |= CLK_V(clk_v);
4716 
		}
4717 
	}
4718 
 
4719 
	sclk->sclk_value = engine_clock;
4720 
	sclk->vCG_SPLL_FUNC_CNTL = spll_func_cntl;
4721 
	sclk->vCG_SPLL_FUNC_CNTL_2 = spll_func_cntl_2;
4722 
	sclk->vCG_SPLL_FUNC_CNTL_3 = spll_func_cntl_3;
4723 
	sclk->vCG_SPLL_FUNC_CNTL_4 = spll_func_cntl_4;
4724 
	sclk->vCG_SPLL_SPREAD_SPECTRUM = cg_spll_spread_spectrum;
4725 
	sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cg_spll_spread_spectrum_2;
4726 
 
4727 
	return 0;
4728 
}
4729 
 
4730 
static int si_populate_sclk_value(struct radeon_device *rdev,
4731 
				  u32 engine_clock,
4732 
				  SISLANDS_SMC_SCLK_VALUE *sclk)
4733 
{
4734 
	SISLANDS_SMC_SCLK_VALUE sclk_tmp;
4735 
	int ret;
4736 
 
4737 
	ret = si_calculate_sclk_params(rdev, engine_clock, &sclk_tmp);
4738 
	if (!ret) {
4739 
		sclk->sclk_value = cpu_to_be32(sclk_tmp.sclk_value);
4740 
		sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL);
4741 
		sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_2);
4742 
		sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_3);
4743 
		sclk->vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_4);
4744 
		sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM);
4745 
		sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM_2);
4746 
	}
4747 
 
4748 
	return ret;
4749 
}
4750 
 
4751 
static int si_populate_mclk_value(struct radeon_device *rdev,
4752 
				  u32 engine_clock,
4753 
				  u32 memory_clock,
4754 
				  SISLANDS_SMC_MCLK_VALUE *mclk,
4755 
				  bool strobe_mode,
4756 
				  bool dll_state_on)
4757 
{
4758 
	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4759 
	struct si_power_info *si_pi = si_get_pi(rdev);
4760 
	u32  dll_cntl = si_pi->clock_registers.dll_cntl;
4761 
	u32  mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;
4762 
	u32  mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;
4763 
	u32  mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;
4764 
	u32  mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;
4765 
	u32  mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;
4766 
	u32  mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;
4767 
	u32  mpll_ss1 = si_pi->clock_registers.mpll_ss1;
4768 
	u32  mpll_ss2 = si_pi->clock_registers.mpll_ss2;
4769 
	struct atom_mpll_param mpll_param;
4770 
	int ret;
4771 
 
4772 
	ret = radeon_atom_get_memory_pll_dividers(rdev, memory_clock, strobe_mode, &mpll_param);
4773 
	if (ret)
4774 
		return ret;
4775 
 
4776 
	mpll_func_cntl &= ~BWCTRL_MASK;
4777 
	mpll_func_cntl |= BWCTRL(mpll_param.bwcntl);
4778 
 
4779 
	mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK);
4780 
	mpll_func_cntl_1 |= CLKF(mpll_param.clkf) |
4781 
		CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode);
4782 
 
4783 
	mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK;
4784 
	mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div);
4785 
 
4786 
	if (pi->mem_gddr5) {
4787 
		mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK);
4788 
		mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) |
4789 
			YCLK_POST_DIV(mpll_param.post_div);
4790 
	}
4791 
 
4792 
	if (pi->mclk_ss) {
4793 
		struct radeon_atom_ss ss;
4794 
		u32 freq_nom;
4795 
		u32 tmp;
4796 
		u32 reference_clock = rdev->clock.mpll.reference_freq;
4797 
 
4798 
		if (pi->mem_gddr5)
4799 
			freq_nom = memory_clock * 4;
4800 
		else
4801 
			freq_nom = memory_clock * 2;
4802 
 
4803 
		tmp = freq_nom / reference_clock;
4804 
		tmp = tmp * tmp;
4805 
		if (radeon_atombios_get_asic_ss_info(rdev, &ss,
4806 
                                                     ASIC_INTERNAL_MEMORY_SS, freq_nom)) {
4807 
			u32 clks = reference_clock * 5 / ss.rate;
4808 
			u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom);
4809 
 
4810 
                        mpll_ss1 &= ~CLKV_MASK;
4811 
                        mpll_ss1 |= CLKV(clkv);
4812 
 
4813 
                        mpll_ss2 &= ~CLKS_MASK;
4814 
                        mpll_ss2 |= CLKS(clks);
4815 
		}
4816 
	}
4817 
 
4818 
	mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK;
4819 
	mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed);
4820 
 
4821 
	if (dll_state_on)
4822 
		mclk_pwrmgt_cntl |= MRDCK0_PDNB | MRDCK1_PDNB;
4823 
	else
4824 
		mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
4825 
 
4826 
	mclk->mclk_value = cpu_to_be32(memory_clock);
4827 
	mclk->vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl);
4828 
	mclk->vMPLL_FUNC_CNTL_1 = cpu_to_be32(mpll_func_cntl_1);
4829 
	mclk->vMPLL_FUNC_CNTL_2 = cpu_to_be32(mpll_func_cntl_2);
4830 
	mclk->vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl);
4831 
	mclk->vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl);
4832 
	mclk->vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl);
4833 
	mclk->vDLL_CNTL = cpu_to_be32(dll_cntl);
4834 
	mclk->vMPLL_SS = cpu_to_be32(mpll_ss1);
4835 
	mclk->vMPLL_SS2 = cpu_to_be32(mpll_ss2);
4836 
 
4837 
	return 0;
4838 
}
4839 
 
4840 
static void si_populate_smc_sp(struct radeon_device *rdev,
4841 
			       struct radeon_ps *radeon_state,
4842 
			       SISLANDS_SMC_SWSTATE *smc_state)
4843 
{
4844 
	struct ni_ps *ps = ni_get_ps(radeon_state);
4845 
	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4846 
	int i;
4847 
 
4848 
	for (i = 0; i < ps->performance_level_count - 1; i++)
4849 
		smc_state->levels[i].bSP = cpu_to_be32(pi->dsp);
4850 
 
4851 
	smc_state->levels[ps->performance_level_count - 1].bSP =
4852 
		cpu_to_be32(pi->psp);
4853 
}
4854 
 
4855 
static int si_convert_power_level_to_smc(struct radeon_device *rdev,
4856 
					 struct rv7xx_pl *pl,
4857 
					 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level)
4858 
{
4859 
	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4860 
	struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4861 
	struct si_power_info *si_pi = si_get_pi(rdev);
4862 
	int ret;
4863 
	bool dll_state_on;
4864 
	u16 std_vddc;
4865 
	bool gmc_pg = false;
4866 
 
4867 
	if (eg_pi->pcie_performance_request &&
4868 
	    (si_pi->force_pcie_gen != RADEON_PCIE_GEN_INVALID))
4869 
		level->gen2PCIE = (u8)si_pi->force_pcie_gen;
4870 
	else
4871 
		level->gen2PCIE = (u8)pl->pcie_gen;
4872 
 
4873 
	ret = si_populate_sclk_value(rdev, pl->sclk, &level->sclk);
4874 
	if (ret)
4875 
		return ret;
4876 
 
4877 
	level->mcFlags =  0;
4878 
 
4879 
	if (pi->mclk_stutter_mode_threshold &&
4880 
	    (pl->mclk <= pi->mclk_stutter_mode_threshold) &&
4881 
	    !eg_pi->uvd_enabled &&
4882 
	    (RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) &&
4883 
	    (rdev->pm.dpm.new_active_crtc_count <= 2)) {
4884 
		level->mcFlags |= SISLANDS_SMC_MC_STUTTER_EN;
4885 
 
4886 
		if (gmc_pg)
4887 
			level->mcFlags |= SISLANDS_SMC_MC_PG_EN;
4888 
	}
4889 
 
4890 
	if (pi->mem_gddr5) {
4891 
		if (pl->mclk > pi->mclk_edc_enable_threshold)
4892 
			level->mcFlags |= SISLANDS_SMC_MC_EDC_RD_FLAG;
4893 
 
4894 
		if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold)
4895 
			level->mcFlags |= SISLANDS_SMC_MC_EDC_WR_FLAG;
4896 
 
4897 
		level->strobeMode = si_get_strobe_mode_settings(rdev, pl->mclk);
4898 
 
4899 
		if (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) {
4900 
			if (si_get_mclk_frequency_ratio(pl->mclk, true) >=
4901 
			    ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf))
4902 
				dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
4903 
			else
4904 
				dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false;
4905 
		} else {
4906 
			dll_state_on = false;
4907 
		}
4908 
	} else {
4909 
		level->strobeMode = si_get_strobe_mode_settings(rdev,
4910 
								pl->mclk);
4911 
 
4912 
		dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
4913 
	}
4914 
 
4915 
	ret = si_populate_mclk_value(rdev,
4916 
				     pl->sclk,
4917 
				     pl->mclk,
4918 
				     &level->mclk,
4919 
				     (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) != 0, dll_state_on);
4920 
	if (ret)
4921 
		return ret;
4922 
 
4923 
	ret = si_populate_voltage_value(rdev,
4924 
					&eg_pi->vddc_voltage_table,
4925 
					pl->vddc, &level->vddc);
4926 
	if (ret)
4927 
		return ret;
4928 
 
4929 
 
4930 
	ret = si_get_std_voltage_value(rdev, &level->vddc, &std_vddc);
4931 
	if (ret)
4932 
		return ret;
4933 
 
4934 
	ret = si_populate_std_voltage_value(rdev, std_vddc,
4935 
					    level->vddc.index, &level->std_vddc);
4936 
	if (ret)
4937 
		return ret;
4938 
 
4939 
	if (eg_pi->vddci_control) {
4940 
		ret = si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table,
4941 
						pl->vddci, &level->vddci);
4942 
		if (ret)
4943 
			return ret;
4944 
	}
4945 
 
4946 
	if (si_pi->vddc_phase_shed_control) {
4947 
		ret = si_populate_phase_shedding_value(rdev,
4948 
						       &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
4949 
						       pl->vddc,
4950 
						       pl->sclk,
4951 
						       pl->mclk,
4952 
						       &level->vddc);
4953 
		if (ret)
4954 
			return ret;
4955 
	}
4956 
 
4957 
	level->MaxPoweredUpCU = si_pi->max_cu;
4958 
 
4959 
	ret = si_populate_mvdd_value(rdev, pl->mclk, &level->mvdd);
4960 
 
4961 
	return ret;
4962 
}
4963 
 
4964 
static int si_populate_smc_t(struct radeon_device *rdev,
4965 
			     struct radeon_ps *radeon_state,
4966 
			     SISLANDS_SMC_SWSTATE *smc_state)
4967 
{
4968 
	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4969 
	struct ni_ps *state = ni_get_ps(radeon_state);
4970 
	u32 a_t;
4971 
	u32 t_l, t_h;
4972 
	u32 high_bsp;
4973 
	int i, ret;
4974 
 
4975 
	if (state->performance_level_count >= 9)
4976 
		return -EINVAL;
4977 
 
4978 
	if (state->performance_level_count < 2) {
4979 
		a_t = CG_R(0xffff) | CG_L(0);
4980 
		smc_state->levels[0].aT = cpu_to_be32(a_t);
4981 
		return 0;
4982 
	}
4983 
 
4984 
	smc_state->levels[0].aT = cpu_to_be32(0);
4985 
 
4986 
	for (i = 0; i <= state->performance_level_count - 2; i++) {
4987 
		ret = r600_calculate_at(
4988 
			(50 / SISLANDS_MAX_HARDWARE_POWERLEVELS) * 100 * (i + 1),
4989 
			100 * R600_AH_DFLT,
4990 
			state->performance_levels[i + 1].sclk,
4991 
			state->performance_levels[i].sclk,
4992 
			&t_l,
4993 
			&t_h);
4994 
 
4995 
		if (ret) {
4996 
			t_h = (i + 1) * 1000 - 50 * R600_AH_DFLT;
4997 
			t_l = (i + 1) * 1000 + 50 * R600_AH_DFLT;
4998 
		}
4999 
 
5000 
		a_t = be32_to_cpu(smc_state->levels[i].aT) & ~CG_R_MASK;
5001 
		a_t |= CG_R(t_l * pi->bsp / 20000);
5002 
		smc_state->levels[i].aT = cpu_to_be32(a_t);
5003 
 
5004 
		high_bsp = (i == state->performance_level_count - 2) ?
5005 
			pi->pbsp : pi->bsp;
5006 
		a_t = CG_R(0xffff) | CG_L(t_h * high_bsp / 20000);
5007 
		smc_state->levels[i + 1].aT = cpu_to_be32(a_t);
5008 
	}
5009 
 
5010 
	return 0;
5011 
}
5012 
 
5013 
static int si_disable_ulv(struct radeon_device *rdev)
5014 
{
5015 
	struct si_power_info *si_pi = si_get_pi(rdev);
5016 
	struct si_ulv_param *ulv = &si_pi->ulv;
5017 
 
5018 
	if (ulv->supported)
5019 
		return (si_send_msg_to_smc(rdev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ?
5020 
 
5021 
 
5022 
	return 0;
5023 
}
5024 
 
5025 
static bool si_is_state_ulv_compatible(struct radeon_device *rdev,
5026 
				       struct radeon_ps *radeon_state)
5027 
{
5028 
	const struct si_power_info *si_pi = si_get_pi(rdev);
5029 
	const struct si_ulv_param *ulv = &si_pi->ulv;
5030 
	const struct ni_ps *state = ni_get_ps(radeon_state);
5031 
	int i;
5032 
 
5033 
	if (state->performance_levels[0].mclk != ulv->pl.mclk)
5034 
		return false;
5035 
 
5036 
	/* XXX validate against display requirements! */
5037 
 
5038 
	for (i = 0; i < rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count; i++) {
5039 
		if (rdev->clock.current_dispclk <=
5040 
		    rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].clk) {
5041 
			if (ulv->pl.vddc <
5042 
			    rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].v)
5043 
				return false;
5044 
		}
5045 
	}
5046 
 
5047 
	if ((radeon_state->vclk != 0) || (radeon_state->dclk != 0))
5048 
		return false;
5049 
 
5050 
	return true;
5051 
}
5052 
 
5053 
static int si_set_power_state_conditionally_enable_ulv(struct radeon_device *rdev,
5054 
						       struct radeon_ps *radeon_new_state)
5055 
{
5056 
	const struct si_power_info *si_pi = si_get_pi(rdev);
5057 
	const struct si_ulv_param *ulv = &si_pi->ulv;
5058 
 
5059 
	if (ulv->supported) {
5060 
		if (si_is_state_ulv_compatible(rdev, radeon_new_state))
5061 
			return (si_send_msg_to_smc(rdev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ?
5062 
 
5063 
	}
5064 
	return 0;
5065 
}
5066 
 
5067 
static int si_convert_power_state_to_smc(struct radeon_device *rdev,
5068 
					 struct radeon_ps *radeon_state,
5069 
					 SISLANDS_SMC_SWSTATE *smc_state)
5070 
{
5071 
	struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
5072 
	struct ni_power_info *ni_pi = ni_get_pi(rdev);
5073 
	struct si_power_info *si_pi = si_get_pi(rdev);
5074 
	struct ni_ps *state = ni_get_ps(radeon_state);
5075 
	int i, ret;
5076 
	u32 threshold;
5077 
	u32 sclk_in_sr = 1350; /* ??? */
5078 
 
5079 
	if (state->performance_level_count > SISLANDS_MAX_HARDWARE_POWERLEVELS)
5080 
		return -EINVAL;
5081 
 
5082 
	threshold = state->performance_levels[state->performance_level_count-1].sclk * 100 / 100;
5083 
 
5084 
	if (radeon_state->vclk && radeon_state->dclk) {
5085 
		eg_pi->uvd_enabled = true;
5086 
		if (eg_pi->smu_uvd_hs)
5087 
			smc_state->flags |= PPSMC_SWSTATE_FLAG_UVD;
5088 
	} else {
5089 
		eg_pi->uvd_enabled = false;
5090 
	}
5091 
 
5092 
	if (state->dc_compatible)
5093 
		smc_state->flags |= PPSMC_SWSTATE_FLAG_DC;
5094 
 
5095 
	smc_state->levelCount = 0;
5096 
	for (i = 0; i < state->performance_level_count; i++) {
5097 
		if (eg_pi->sclk_deep_sleep) {
5098 
			if ((i == 0) || si_pi->sclk_deep_sleep_above_low) {
5099 
				if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ)
5100 
					smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS;
5101 
				else
5102 
					smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE;
5103 
			}
5104 
		}
5105 
 
5106 
		ret = si_convert_power_level_to_smc(rdev, &state->performance_levels[i],
5107 
						    &smc_state->levels[i]);
5108 
		smc_state->levels[i].arbRefreshState =
5109 
			(u8)(SISLANDS_DRIVER_STATE_ARB_INDEX + i);
5110 
 
5111 
		if (ret)
5112 
			return ret;
5113 
 
5114 
		if (ni_pi->enable_power_containment)
5115 
			smc_state->levels[i].displayWatermark =
5116 
				(state->performance_levels[i].sclk < threshold) ?
5117 
				PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH;
5118 
		else
5119 
			smc_state->levels[i].displayWatermark = (i < 2) ?
5120 
				PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH;
5121 
 
5122 
		if (eg_pi->dynamic_ac_timing)
5123 
			smc_state->levels[i].ACIndex = SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i;
5124 
		else
5125 
			smc_state->levels[i].ACIndex = 0;
5126 
 
5127 
		smc_state->levelCount++;
5128 
	}
5129 
 
5130 
	si_write_smc_soft_register(rdev,
5131 
				   SI_SMC_SOFT_REGISTER_watermark_threshold,
5132 
				   threshold / 512);
5133 
 
5134 
	si_populate_smc_sp(rdev, radeon_state, smc_state);
5135 
 
5136 
	ret = si_populate_power_containment_values(rdev, radeon_state, smc_state);
5137 
	if (ret)
5138 
		ni_pi->enable_power_containment = false;
5139 
 
5140 
	ret = si_populate_sq_ramping_values(rdev, radeon_state, smc_state);
5141 
        if (ret)
5142 
		ni_pi->enable_sq_ramping = false;
5143 
 
5144 
	return si_populate_smc_t(rdev, radeon_state, smc_state);
5145 
}
5146 
 
5147 
static int si_upload_sw_state(struct radeon_device *rdev,
5148 
			      struct radeon_ps *radeon_new_state)
5149 
{
5150 
	struct si_power_info *si_pi = si_get_pi(rdev);
5151 
	struct ni_ps *new_state = ni_get_ps(radeon_new_state);
5152 
	int ret;
5153 
	u32 address = si_pi->state_table_start +
5154 
		offsetof(SISLANDS_SMC_STATETABLE, driverState);
5155 
	u32 state_size = sizeof(SISLANDS_SMC_SWSTATE) +
5156 
		((new_state->performance_level_count - 1) *
5157 
		 sizeof(SISLANDS_SMC_HW_PERFORMANCE_LEVEL));
5158 
	SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.driverState;
5159 
 
5160 
	memset(smc_state, 0, state_size);
5161 
 
5162 
	ret = si_convert_power_state_to_smc(rdev, radeon_new_state, smc_state);
5163 
	if (ret)
5164 
		return ret;
5165 
 
5166 
	ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state,
5167 
				   state_size, si_pi->sram_end);
5168 
 
5169 
	return ret;
5170 
}
5171 
 
5172 
static int si_upload_ulv_state(struct radeon_device *rdev)
5173 
{
5174 
	struct si_power_info *si_pi = si_get_pi(rdev);
5175 
	struct si_ulv_param *ulv = &si_pi->ulv;
5176 
	int ret = 0;
5177 
 
5178 
	if (ulv->supported && ulv->pl.vddc) {
5179 
		u32 address = si_pi->state_table_start +
5180 
			offsetof(SISLANDS_SMC_STATETABLE, ULVState);
5181 
		SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.ULVState;
5182 
		u32 state_size = sizeof(SISLANDS_SMC_SWSTATE);
5183 
 
5184 
		memset(smc_state, 0, state_size);
5185 
 
5186 
		ret = si_populate_ulv_state(rdev, smc_state);
5187 
		if (!ret)
5188 
			ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state,
5189 
						   state_size, si_pi->sram_end);
5190 
	}
5191 
 
5192 
	return ret;
5193 
}
5194 
 
5195 
static int si_upload_smc_data(struct radeon_device *rdev)
5196 
{
5197 
	struct radeon_crtc *radeon_crtc = NULL;
5198 
	int i;
5199 
 
5200 
	if (rdev->pm.dpm.new_active_crtc_count == 0)
5201 
		return 0;
5202 
 
5203 
	for (i = 0; i < rdev->num_crtc; i++) {
5204 
		if (rdev->pm.dpm.new_active_crtcs & (1 << i)) {
5205 
			radeon_crtc = rdev->mode_info.crtcs[i];
5206 
			break;
5207 
		}
5208 
	}
5209 
 
5210 
	if (radeon_crtc == NULL)
5211 
		return 0;
5212 
 
5213 
	if (radeon_crtc->line_time <= 0)
5214 
		return 0;
5215 
 
5216 
	if (si_write_smc_soft_register(rdev,
5217 
				       SI_SMC_SOFT_REGISTER_crtc_index,
5218 
				       radeon_crtc->crtc_id) != PPSMC_Result_OK)
5219 
		return 0;
5220 
 
5221 
	if (si_write_smc_soft_register(rdev,
5222 
				       SI_SMC_SOFT_REGISTER_mclk_change_block_cp_min,
5223 
				       radeon_crtc->wm_high / radeon_crtc->line_time) != PPSMC_Result_OK)
5224 
		return 0;
5225 
 
5226 
	if (si_write_smc_soft_register(rdev,
5227 
				       SI_SMC_SOFT_REGISTER_mclk_change_block_cp_max,
5228 
				       radeon_crtc->wm_low / radeon_crtc->line_time) != PPSMC_Result_OK)
5229 
		return 0;
5230 
 
5231 
	return 0;
5232 
}
5233 
 
5234 
static int si_set_mc_special_registers(struct radeon_device *rdev,
5235 
				       struct si_mc_reg_table *table)
5236 
{
5237 
	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
5238 
	u8 i, j, k;
5239 
	u32 temp_reg;
5240 
 
5241 
	for (i = 0, j = table->last; i < table->last; i++) {
5242 
		if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5243 
			return -EINVAL;
5244 
		switch (table->mc_reg_address[i].s1 << 2) {
5245 
		case MC_SEQ_MISC1:
5246 
			temp_reg = RREG32(MC_PMG_CMD_EMRS);
5247 
			table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2;
5248 
			table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
5249 
			for (k = 0; k < table->num_entries; k++)
5250 
				table->mc_reg_table_entry[k].mc_data[j] =
5251 
					((temp_reg & 0xffff0000)) |
5252 
					((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
5253 
			j++;
5254 
			if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5255 
				return -EINVAL;
5256 
 
5257 
			temp_reg = RREG32(MC_PMG_CMD_MRS);
5258 
			table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2;
5259 
			table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2;
5260 
			for (k = 0; k < table->num_entries; k++) {
5261 
				table->mc_reg_table_entry[k].mc_data[j] =
5262 
					(temp_reg & 0xffff0000) |
5263 
					(table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
5264 
				if (!pi->mem_gddr5)
5265 
					table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
5266 
			}
5267 
			j++;
5268 
			if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5269 
				return -EINVAL;
5270 
 
5271 
			if (!pi->mem_gddr5) {
5272 
				table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD >> 2;
5273 
				table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD >> 2;
5274 
				for (k = 0; k < table->num_entries; k++)
5275 
					table->mc_reg_table_entry[k].mc_data[j] =
5276 
						(table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
5277 
				j++;
5278 
				if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5279 
					return -EINVAL;
5280 
			}
5281 
			break;
5282 
		case MC_SEQ_RESERVE_M:
5283 
			temp_reg = RREG32(MC_PMG_CMD_MRS1);
5284 
			table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2;
5285 
			table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
5286 
			for(k = 0; k < table->num_entries; k++)
5287 
				table->mc_reg_table_entry[k].mc_data[j] =
5288 
					(temp_reg & 0xffff0000) |
5289 
					(table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
5290 
			j++;
5291 
			if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5292 
				return -EINVAL;
5293 
			break;
5294 
		default:
5295 
			break;
5296 
		}
5297 
	}
5298 
 
5299 
	table->last = j;
5300 
 
5301 
	return 0;
5302 
}
5303 
 
5304 
static bool si_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg)
5305 
{
5306 
	bool result = true;
5307 
 
5308 
	switch (in_reg) {
5309 
	case  MC_SEQ_RAS_TIMING >> 2:
5310 
		*out_reg = MC_SEQ_RAS_TIMING_LP >> 2;
5311 
		break;
5312 
        case MC_SEQ_CAS_TIMING >> 2:
5313 
		*out_reg = MC_SEQ_CAS_TIMING_LP >> 2;
5314 
		break;
5315 
        case MC_SEQ_MISC_TIMING >> 2:
5316 
		*out_reg = MC_SEQ_MISC_TIMING_LP >> 2;
5317 
		break;
5318 
        case MC_SEQ_MISC_TIMING2 >> 2:
5319 
		*out_reg = MC_SEQ_MISC_TIMING2_LP >> 2;
5320 
		break;
5321 
        case MC_SEQ_RD_CTL_D0 >> 2:
5322 
		*out_reg = MC_SEQ_RD_CTL_D0_LP >> 2;
5323 
		break;
5324 
        case MC_SEQ_RD_CTL_D1 >> 2:
5325 
		*out_reg = MC_SEQ_RD_CTL_D1_LP >> 2;
5326 
		break;
5327 
        case MC_SEQ_WR_CTL_D0 >> 2:
5328 
		*out_reg = MC_SEQ_WR_CTL_D0_LP >> 2;
5329 
		break;
5330 
        case MC_SEQ_WR_CTL_D1 >> 2:
5331 
		*out_reg = MC_SEQ_WR_CTL_D1_LP >> 2;
5332 
		break;
5333 
        case MC_PMG_CMD_EMRS >> 2:
5334 
		*out_reg = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
5335 
		break;
5336 
        case MC_PMG_CMD_MRS >> 2:
5337 
		*out_reg = MC_SEQ_PMG_CMD_MRS_LP >> 2;
5338 
		break;
5339 
        case MC_PMG_CMD_MRS1 >> 2:
5340 
		*out_reg = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
5341 
		break;
5342 
        case MC_SEQ_PMG_TIMING >> 2:
5343 
		*out_reg = MC_SEQ_PMG_TIMING_LP >> 2;
5344 
		break;
5345 
        case MC_PMG_CMD_MRS2 >> 2:
5346 
		*out_reg = MC_SEQ_PMG_CMD_MRS2_LP >> 2;
5347 
		break;
5348 
        case MC_SEQ_WR_CTL_2 >> 2:
5349 
		*out_reg = MC_SEQ_WR_CTL_2_LP >> 2;
5350 
		break;
5351 
        default:
5352 
		result = false;
5353 
		break;
5354 
	}
5355 
 
5356 
	return result;
5357 
}
5358 
 
5359 
static void si_set_valid_flag(struct si_mc_reg_table *table)
5360 
{
5361 
	u8 i, j;
5362 
 
5363 
	for (i = 0; i < table->last; i++) {
5364 
		for (j = 1; j < table->num_entries; j++) {
5365 
			if (table->mc_reg_table_entry[j-1].mc_data[i] != table->mc_reg_table_entry[j].mc_data[i]) {
5366 
				table->valid_flag |= 1 << i;
5367 
				break;
5368 
			}
5369 
		}
5370 
	}
5371 
}
5372 
 
5373 
static void si_set_s0_mc_reg_index(struct si_mc_reg_table *table)
5374 
{
5375 
	u32 i;
5376 
	u16 address;
5377 
 
5378 
	for (i = 0; i < table->last; i++)
5379 
		table->mc_reg_address[i].s0 = si_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ?
5380 
			address : table->mc_reg_address[i].s1;
5381 
 
5382 
}
5383 
 
5384 
static int si_copy_vbios_mc_reg_table(struct atom_mc_reg_table *table,
5385 
				      struct si_mc_reg_table *si_table)
5386 
{
5387 
	u8 i, j;
5388 
 
5389 
	if (table->last > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5390 
		return -EINVAL;
5391 
	if (table->num_entries > MAX_AC_TIMING_ENTRIES)
5392 
		return -EINVAL;
5393 
 
5394 
	for (i = 0; i < table->last; i++)
5395 
		si_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
5396 
	si_table->last = table->last;
5397 
 
5398 
	for (i = 0; i < table->num_entries; i++) {
5399 
		si_table->mc_reg_table_entry[i].mclk_max =
5400 
			table->mc_reg_table_entry[i].mclk_max;
5401 
		for (j = 0; j < table->last; j++) {
5402 
			si_table->mc_reg_table_entry[i].mc_data[j] =
5403 
				table->mc_reg_table_entry[i].mc_data[j];
5404 
		}
5405 
	}
5406 
	si_table->num_entries = table->num_entries;
5407 
 
5408 
	return 0;
5409 
}
5410 
 
5411 
static int si_initialize_mc_reg_table(struct radeon_device *rdev)
5412 
{
5413 
	struct si_power_info *si_pi = si_get_pi(rdev);
5414 
	struct atom_mc_reg_table *table;
5415 
	struct si_mc_reg_table *si_table = &si_pi->mc_reg_table;
5416 
	u8 module_index = rv770_get_memory_module_index(rdev);
5417 
	int ret;
5418 
 
5419 
	table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL);
5420 
	if (!table)
5421 
		return -ENOMEM;
5422 
 
5423 
	WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING));
5424 
	WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING));
5425 
	WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING));
5426 
	WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));
5427 
	WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS));
5428 
	WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS));
5429 
	WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1));
5430 
	WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));
5431 
	WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));
5432 
	WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0));
5433 
	WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1));
5434 
	WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING));
5435 
	WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2));
5436 
	WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2));
5437 
 
5438 
        ret = radeon_atom_init_mc_reg_table(rdev, module_index, table);
5439 
        if (ret)
5440 
                goto init_mc_done;
5441 
 
5442 
        ret = si_copy_vbios_mc_reg_table(table, si_table);
5443 
        if (ret)
5444 
                goto init_mc_done;
5445 
 
5446 
	si_set_s0_mc_reg_index(si_table);
5447 
 
5448 
	ret = si_set_mc_special_registers(rdev, si_table);
5449 
        if (ret)
5450 
                goto init_mc_done;
5451 
 
5452 
	si_set_valid_flag(si_table);
5453 
 
5454 
init_mc_done:
5455 
	kfree(table);
5456 
 
5457 
	return ret;
5458 
 
5459 
}
5460 
 
5461 
static void si_populate_mc_reg_addresses(struct radeon_device *rdev,
5462 
					 SMC_SIslands_MCRegisters *mc_reg_table)
5463 
{
5464 
	struct si_power_info *si_pi = si_get_pi(rdev);
5465 
	u32 i, j;
5466 
 
5467 
	for (i = 0, j = 0; j < si_pi->mc_reg_table.last; j++) {
5468 
		if (si_pi->mc_reg_table.valid_flag & (1 << j)) {
5469 
			if (i >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5470 
				break;
5471 
			mc_reg_table->address[i].s0 =
5472 
				cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s0);
5473 
			mc_reg_table->address[i].s1 =
5474 
				cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s1);
5475 
			i++;
5476 
		}
5477 
	}
5478 
	mc_reg_table->last = (u8)i;
5479 
}
5480 
 
5481 
static void si_convert_mc_registers(const struct si_mc_reg_entry *entry,
5482 
				    SMC_SIslands_MCRegisterSet *data,
5483 
				    u32 num_entries, u32 valid_flag)
5484 
{
5485 
	u32 i, j;
5486 
 
5487 
	for(i = 0, j = 0; j < num_entries; j++) {
5488 
		if (valid_flag & (1 << j)) {
5489 
			data->value[i] = cpu_to_be32(entry->mc_data[j]);
5490 
			i++;
5491 
		}
5492 
	}
5493 
}
5494 
 
5495 
static void si_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev,
5496 
						 struct rv7xx_pl *pl,
5497 
						 SMC_SIslands_MCRegisterSet *mc_reg_table_data)
5498 
{
5499 
	struct si_power_info *si_pi = si_get_pi(rdev);
5500 
	u32 i = 0;
5501 
 
5502 
	for (i = 0; i < si_pi->mc_reg_table.num_entries; i++) {
5503 
		if (pl->mclk <= si_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max)
5504 
			break;
5505 
	}
5506 
 
5507 
	if ((i == si_pi->mc_reg_table.num_entries) && (i > 0))
5508 
		--i;
5509 
 
5510 
	si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[i],
5511 
				mc_reg_table_data, si_pi->mc_reg_table.last,
5512 
				si_pi->mc_reg_table.valid_flag);
5513 
}
5514 
 
5515 
static void si_convert_mc_reg_table_to_smc(struct radeon_device *rdev,
5516 
					   struct radeon_ps *radeon_state,
5517 
					   SMC_SIslands_MCRegisters *mc_reg_table)
5518 
{
5519 
	struct ni_ps *state = ni_get_ps(radeon_state);
5520 
	int i;
5521 
 
5522 
	for (i = 0; i < state->performance_level_count; i++) {
5523 
		si_convert_mc_reg_table_entry_to_smc(rdev,
5524 
						     &state->performance_levels[i],
5525 
						     &mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i]);
5526 
	}
5527 
}
5528 
 
5529 
static int si_populate_mc_reg_table(struct radeon_device *rdev,
5530 
				    struct radeon_ps *radeon_boot_state)
5531 
{
5532 
	struct ni_ps *boot_state = ni_get_ps(radeon_boot_state);
5533 
	struct si_power_info *si_pi = si_get_pi(rdev);
5534 
	struct si_ulv_param *ulv = &si_pi->ulv;
5535 
	SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table;
5536 
 
5537 
	memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters));
5538 
 
5539 
	si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_seq_index, 1);
5540 
 
5541 
	si_populate_mc_reg_addresses(rdev, smc_mc_reg_table);
5542 
 
5543 
	si_convert_mc_reg_table_entry_to_smc(rdev, &boot_state->performance_levels[0],
5544 
					     &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_INITIAL_SLOT]);
5545 
 
5546 
	si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0],
5547 
				&smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ACPI_SLOT],
5548 
				si_pi->mc_reg_table.last,
5549 
				si_pi->mc_reg_table.valid_flag);
5550 
 
5551 
	if (ulv->supported && ulv->pl.vddc != 0)
5552 
		si_convert_mc_reg_table_entry_to_smc(rdev, &ulv->pl,
5553 
						     &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT]);
5554 
	else
5555 
		si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0],
5556 
					&smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT],
5557 
					si_pi->mc_reg_table.last,
5558 
					si_pi->mc_reg_table.valid_flag);
5559 
 
5560 
	si_convert_mc_reg_table_to_smc(rdev, radeon_boot_state, smc_mc_reg_table);
5561 
 
5562 
	return si_copy_bytes_to_smc(rdev, si_pi->mc_reg_table_start,
5563 
				    (u8 *)smc_mc_reg_table,
5564 
				    sizeof(SMC_SIslands_MCRegisters), si_pi->sram_end);
5565 
}
5566 
 
5567 
static int si_upload_mc_reg_table(struct radeon_device *rdev,
5568 
				  struct radeon_ps *radeon_new_state)
5569 
{
5570 
	struct ni_ps *new_state = ni_get_ps(radeon_new_state);
5571 
	struct si_power_info *si_pi = si_get_pi(rdev);
5572 
	u32 address = si_pi->mc_reg_table_start +
5573 
		offsetof(SMC_SIslands_MCRegisters,
5574 
			 data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT]);
5575 
	SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table;
5576 
 
5577 
	memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters));
5578 
 
5579 
	si_convert_mc_reg_table_to_smc(rdev, radeon_new_state, smc_mc_reg_table);
5580 
 
5581 
 
5582 
	return si_copy_bytes_to_smc(rdev, address,
5583 
				    (u8 *)&smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT],
5584 
				    sizeof(SMC_SIslands_MCRegisterSet) * new_state->performance_level_count,
5585 
				    si_pi->sram_end);
5586 
 
5587 
}
5588 
 
5589 
static void si_enable_voltage_control(struct radeon_device *rdev, bool enable)
5590 
{
5591 
        if (enable)
5592 
                WREG32_P(GENERAL_PWRMGT, VOLT_PWRMGT_EN, ~VOLT_PWRMGT_EN);
5593 
        else
5594 
                WREG32_P(GENERAL_PWRMGT, 0, ~VOLT_PWRMGT_EN);
5595 
}
5596 
 
5597 
static enum radeon_pcie_gen si_get_maximum_link_speed(struct radeon_device *rdev,
5598 
						      struct radeon_ps *radeon_state)
5599 
{
5600 
	struct ni_ps *state = ni_get_ps(radeon_state);
5601 
	int i;
5602 
	u16 pcie_speed, max_speed = 0;
5603 
 
5604 
	for (i = 0; i < state->performance_level_count; i++) {
5605 
		pcie_speed = state->performance_levels[i].pcie_gen;
5606 
		if (max_speed < pcie_speed)
5607 
			max_speed = pcie_speed;
5608 
	}
5609 
	return max_speed;
5610 
}
5611 
 
5612 
static u16 si_get_current_pcie_speed(struct radeon_device *rdev)
5613 
{
5614 
	u32 speed_cntl;
5615 
 
5616 
	speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE_MASK;
5617 
	speed_cntl >>= LC_CURRENT_DATA_RATE_SHIFT;
5618 
 
5619 
	return (u16)speed_cntl;
5620 
}
5621 
 
5622 
static void si_request_link_speed_change_before_state_change(struct radeon_device *rdev,
5623 
							     struct radeon_ps *radeon_new_state,
5624 
							     struct radeon_ps *radeon_current_state)
5625 
{
5626 
	struct si_power_info *si_pi = si_get_pi(rdev);
5627 
	enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state);
5628 
	enum radeon_pcie_gen current_link_speed;
5629 
 
5630 
	if (si_pi->force_pcie_gen == RADEON_PCIE_GEN_INVALID)
5631 
		current_link_speed = si_get_maximum_link_speed(rdev, radeon_current_state);
5632 
	else
5633 
		current_link_speed = si_pi->force_pcie_gen;
5634 
 
5635 
	si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID;
5636 
	si_pi->pspp_notify_required = false;
5637 
	if (target_link_speed > current_link_speed) {
5638 
		switch (target_link_speed) {
5639 
#if defined(CONFIG_ACPI)
5640 
		case RADEON_PCIE_GEN3:
5641 
			if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN3, false) == 0)
5642 
				break;
5643 
			si_pi->force_pcie_gen = RADEON_PCIE_GEN2;
5644 
			if (current_link_speed == RADEON_PCIE_GEN2)
5645 
				break;
5646 
		case RADEON_PCIE_GEN2:
5647 
			if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN2, false) == 0)
5648 
				break;
5649 
#endif
5650 
		default:
5651 
			si_pi->force_pcie_gen = si_get_current_pcie_speed(rdev);
5652 
			break;
5653 
		}
5654 
	} else {
5655 
		if (target_link_speed < current_link_speed)
5656 
			si_pi->pspp_notify_required = true;
5657 
	}
5658 
}
5659 
 
5660 
static void si_notify_link_speed_change_after_state_change(struct radeon_device *rdev,
5661 
							   struct radeon_ps *radeon_new_state,
5662 
							   struct radeon_ps *radeon_current_state)
5663 
{
5664 
	struct si_power_info *si_pi = si_get_pi(rdev);
5665 
	enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state);
5666 
	u8 request;
5667 
 
5668 
	if (si_pi->pspp_notify_required) {
5669 
		if (target_link_speed == RADEON_PCIE_GEN3)
5670 
			request = PCIE_PERF_REQ_PECI_GEN3;
5671 
		else if (target_link_speed == RADEON_PCIE_GEN2)
5672 
			request = PCIE_PERF_REQ_PECI_GEN2;
5673 
		else
5674 
			request = PCIE_PERF_REQ_PECI_GEN1;
5675 
 
5676 
		if ((request == PCIE_PERF_REQ_PECI_GEN1) &&
5677 
		    (si_get_current_pcie_speed(rdev) > 0))
5678 
			return;
5679 
 
5680 
#if defined(CONFIG_ACPI)
5681 
		radeon_acpi_pcie_performance_request(rdev, request, false);
5682 
#endif
5683 
	}
5684 
}
5685 
 
5686 
#if 0
5687 
static int si_ds_request(struct radeon_device *rdev,
5688 
			 bool ds_status_on, u32 count_write)
5689 
{
5690 
	struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
5691 
 
5692 
	if (eg_pi->sclk_deep_sleep) {
5693 
		if (ds_status_on)
5694 
			return (si_send_msg_to_smc(rdev, PPSMC_MSG_CancelThrottleOVRDSCLKDS) ==
5695 
				PPSMC_Result_OK) ?
5696 
 
5697 
		else
5698 
			return (si_send_msg_to_smc(rdev, PPSMC_MSG_ThrottleOVRDSCLKDS) ==
5699 
				PPSMC_Result_OK) ? 0 : -EINVAL;
5700 
	}
5701 
	return 0;
5702 
}
5703 
#endif
5704 
 
5705 
static void si_set_max_cu_value(struct radeon_device *rdev)
5706 
{
5707 
	struct si_power_info *si_pi = si_get_pi(rdev);
5708 
 
5709 
	if (rdev->family == CHIP_VERDE) {
5710 
		switch (rdev->pdev->device) {
5711 
		case 0x6820:
5712 
		case 0x6825:
5713 
		case 0x6821:
5714 
		case 0x6823:
5715 
		case 0x6827:
5716 
			si_pi->max_cu = 10;
5717 
			break;
5718 
		case 0x682D:
5719 
		case 0x6824:
5720 
		case 0x682F:
5721 
		case 0x6826:
5722 
			si_pi->max_cu = 8;
5723 
			break;
5724 
		case 0x6828:
5725 
		case 0x6830:
5726 
		case 0x6831:
5727 
		case 0x6838:
5728 
		case 0x6839:
5729 
		case 0x683D:
5730 
			si_pi->max_cu = 10;
5731 
			break;
5732 
		case 0x683B:
5733 
		case 0x683F:
5734 
		case 0x6829:
5735 
			si_pi->max_cu = 8;
5736 
			break;
5737 
		default:
5738 
			si_pi->max_cu = 0;
5739 
			break;
5740 
		}
5741 
	} else {
5742 
		si_pi->max_cu = 0;
5743 
	}
5744 
}
5745 
 
5746 
static int si_patch_single_dependency_table_based_on_leakage(struct radeon_device *rdev,
5747 
							     struct radeon_clock_voltage_dependency_table *table)
5748 
{
5749 
	u32 i;
5750 
	int j;
5751 
	u16 leakage_voltage;
5752 
 
5753 
	if (table) {
5754 
		for (i = 0; i < table->count; i++) {
5755 
			switch (si_get_leakage_voltage_from_leakage_index(rdev,
5756 
									  table->entries[i].v,
5757 
									  &leakage_voltage)) {
5758 
			case 0:
5759 
				table->entries[i].v = leakage_voltage;
5760 
				break;
5761 
			case -EAGAIN:
5762 
				return -EINVAL;
5763 
			case -EINVAL:
5764 
			default:
5765 
				break;
5766 
			}
5767 
		}
5768 
 
5769 
		for (j = (table->count - 2); j >= 0; j--) {
5770 
			table->entries[j].v = (table->entries[j].v <= table->entries[j + 1].v) ?
5771 
				table->entries[j].v : table->entries[j + 1].v;
5772 
		}
5773 
	}
5774 
	return 0;
5775 
}
5776 
 
5777 
static int si_patch_dependency_tables_based_on_leakage(struct radeon_device *rdev)
5778 
{
5779 
	int ret = 0;
5780 
 
5781 
	ret = si_patch_single_dependency_table_based_on_leakage(rdev,
5782 
								&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk);
5783 
	ret = si_patch_single_dependency_table_based_on_leakage(rdev,
5784 
								&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk);
5785 
	ret = si_patch_single_dependency_table_based_on_leakage(rdev,
5786 
								&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk);
5787 
	return ret;
5788 
}
5789 
 
5790 
static void si_set_pcie_lane_width_in_smc(struct radeon_device *rdev,
5791 
					  struct radeon_ps *radeon_new_state,
5792 
					  struct radeon_ps *radeon_current_state)
5793 
{
5794 
	u32 lane_width;
5795 
	u32 new_lane_width =
5796 
		(radeon_new_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT;
5797 
	u32 current_lane_width =
5798 
		(radeon_current_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT;
5799 
 
5800 
	if (new_lane_width != current_lane_width) {
5801 
		radeon_set_pcie_lanes(rdev, new_lane_width);
5802 
		lane_width = radeon_get_pcie_lanes(rdev);
5803 
		si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
5804 
	}
5805 
}
5806 
 
5807 
void si_dpm_setup_asic(struct radeon_device *rdev)
5808 
{
5809 
	int r;
5810 
 
5811 
	r = si_mc_load_microcode(rdev);
5812 
	if (r)
5813 
		DRM_ERROR("Failed to load MC firmware!\n");
5814 
	rv770_get_memory_type(rdev);
5815 
	si_read_clock_registers(rdev);
5816 
	si_enable_acpi_power_management(rdev);
5817 
}
5818 
 
5819 
static int si_set_thermal_temperature_range(struct radeon_device *rdev,
5820 
					int min_temp, int max_temp)
5821 
{
5822 
	int low_temp = 0 * 1000;
5823 
	int high_temp = 255 * 1000;
5824 
 
5825 
	if (low_temp < min_temp)
5826 
		low_temp = min_temp;
5827 
	if (high_temp > max_temp)
5828 
		high_temp = max_temp;
5829 
	if (high_temp < low_temp) {
5830 
		DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
5831 
		return -EINVAL;
5832 
	}
5833 
 
5834 
	WREG32_P(CG_THERMAL_INT, DIG_THERM_INTH(high_temp / 1000), ~DIG_THERM_INTH_MASK);
5835 
	WREG32_P(CG_THERMAL_INT, DIG_THERM_INTL(low_temp / 1000), ~DIG_THERM_INTL_MASK);
5836 
	WREG32_P(CG_THERMAL_CTRL, DIG_THERM_DPM(high_temp / 1000), ~DIG_THERM_DPM_MASK);
5837 
 
5838 
	rdev->pm.dpm.thermal.min_temp = low_temp;
5839 
	rdev->pm.dpm.thermal.max_temp = high_temp;
5840 
 
5841 
	return 0;
5842 
}
5843 
 
5844 
int si_dpm_enable(struct radeon_device *rdev)
5845 
{
5846 
	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
5847 
	struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
5848 
	struct si_power_info *si_pi = si_get_pi(rdev);
5849 
	struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
5850 
	int ret;
5851 
 
5852 
	if (si_is_smc_running(rdev))
5853 
		return -EINVAL;
5854 
	if (pi->voltage_control || si_pi->voltage_control_svi2)
5855 
		si_enable_voltage_control(rdev, true);
5856 
	if (pi->mvdd_control)
5857 
		si_get_mvdd_configuration(rdev);
5858 
	if (pi->voltage_control || si_pi->voltage_control_svi2) {
5859 
		ret = si_construct_voltage_tables(rdev);
5860 
		if (ret) {
5861 
			DRM_ERROR("si_construct_voltage_tables failed\n");
5862 
			return ret;
5863 
		}
5864 
	}
5865 
	if (eg_pi->dynamic_ac_timing) {
5866 
		ret = si_initialize_mc_reg_table(rdev);
5867 
		if (ret)
5868 
			eg_pi->dynamic_ac_timing = false;
5869 
	}
5870 
	if (pi->dynamic_ss)
5871 
		si_enable_spread_spectrum(rdev, true);
5872 
	if (pi->thermal_protection)
5873 
		si_enable_thermal_protection(rdev, true);
5874 
	si_setup_bsp(rdev);
5875 
	si_program_git(rdev);
5876 
	si_program_tp(rdev);
5877 
	si_program_tpp(rdev);
5878 
	si_program_sstp(rdev);
5879 
	si_enable_display_gap(rdev);
5880 
	si_program_vc(rdev);
5881 
	ret = si_upload_firmware(rdev);
5882 
	if (ret) {
5883 
		DRM_ERROR("si_upload_firmware failed\n");
5884 
		return ret;
5885 
	}
5886 
	ret = si_process_firmware_header(rdev);
5887 
	if (ret) {
5888 
		DRM_ERROR("si_process_firmware_header failed\n");
5889 
		return ret;
5890 
	}
5891 
	ret = si_initial_switch_from_arb_f0_to_f1(rdev);
5892 
	if (ret) {
5893 
		DRM_ERROR("si_initial_switch_from_arb_f0_to_f1 failed\n");
5894 
		return ret;
5895 
	}
5896 
	ret = si_init_smc_table(rdev);
5897 
	if (ret) {
5898 
		DRM_ERROR("si_init_smc_table failed\n");
5899 
		return ret;
5900 
	}
5901 
	ret = si_init_smc_spll_table(rdev);
5902 
	if (ret) {
5903 
		DRM_ERROR("si_init_smc_spll_table failed\n");
5904 
		return ret;
5905 
	}
5906 
	ret = si_init_arb_table_index(rdev);
5907 
	if (ret) {
5908 
		DRM_ERROR("si_init_arb_table_index failed\n");
5909 
		return ret;
5910 
	}
5911 
	if (eg_pi->dynamic_ac_timing) {
5912 
		ret = si_populate_mc_reg_table(rdev, boot_ps);
5913 
		if (ret) {
5914 
			DRM_ERROR("si_populate_mc_reg_table failed\n");
5915 
			return ret;
5916 
		}
5917 
	}
5918 
	ret = si_initialize_smc_cac_tables(rdev);
5919 
	if (ret) {
5920 
		DRM_ERROR("si_initialize_smc_cac_tables failed\n");
5921 
		return ret;
5922 
	}
5923 
	ret = si_initialize_hardware_cac_manager(rdev);
5924 
	if (ret) {
5925 
		DRM_ERROR("si_initialize_hardware_cac_manager failed\n");
5926 
		return ret;
5927 
	}
5928 
	ret = si_initialize_smc_dte_tables(rdev);
5929 
	if (ret) {
5930 
		DRM_ERROR("si_initialize_smc_dte_tables failed\n");
5931 
		return ret;
5932 
	}
5933 
	ret = si_populate_smc_tdp_limits(rdev, boot_ps);
5934 
	if (ret) {
5935 
		DRM_ERROR("si_populate_smc_tdp_limits failed\n");
5936 
		return ret;
5937 
	}
5938 
	ret = si_populate_smc_tdp_limits_2(rdev, boot_ps);
5939 
	if (ret) {
5940 
		DRM_ERROR("si_populate_smc_tdp_limits_2 failed\n");
5941 
		return ret;
5942 
	}
5943 
	si_program_response_times(rdev);
5944 
	si_program_ds_registers(rdev);
5945 
	si_dpm_start_smc(rdev);
5946 
	ret = si_notify_smc_display_change(rdev, false);
5947 
	if (ret) {
5948 
		DRM_ERROR("si_notify_smc_display_change failed\n");
5949 
		return ret;
5950 
	}
5951 
	si_enable_sclk_control(rdev, true);
5952 
	si_start_dpm(rdev);
5953 
 
5954 
	si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
5955 
 
5956 
	ni_update_current_ps(rdev, boot_ps);
5957 
 
5958 
	return 0;
5959 
}
5960 
 
5961 
int si_dpm_late_enable(struct radeon_device *rdev)
5962 
{
5963 
	int ret;
5964 
 
5965 
	if (rdev->irq.installed &&
5966 
	    r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
5967 
		PPSMC_Result result;
5968 
 
5969 
		ret = si_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
5970 
		if (ret)
5971 
			return ret;
5972 
		rdev->irq.dpm_thermal = true;
5973 
		radeon_irq_set(rdev);
5974 
		result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt);
5975 
 
5976 
		if (result != PPSMC_Result_OK)
5977 
			DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
5978 
	}
5979 
 
5980 
	return 0;
5981 
}
5982 
 
5983 
void si_dpm_disable(struct radeon_device *rdev)
5984 
{
5985 
	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
5986 
	struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
5987 
 
5988 
	if (!si_is_smc_running(rdev))
5989 
		return;
5990 
	si_disable_ulv(rdev);
5991 
	si_clear_vc(rdev);
5992 
	if (pi->thermal_protection)
5993 
		si_enable_thermal_protection(rdev, false);
5994 
	si_enable_power_containment(rdev, boot_ps, false);
5995 
	si_enable_smc_cac(rdev, boot_ps, false);
5996 
	si_enable_spread_spectrum(rdev, false);
5997 
	si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, false);
5998 
	si_stop_dpm(rdev);
5999 
	si_reset_to_default(rdev);
6000 
	si_dpm_stop_smc(rdev);
6001 
	si_force_switch_to_arb_f0(rdev);
6002 
 
6003 
	ni_update_current_ps(rdev, boot_ps);
6004 
}
6005 
 
6006 
int si_dpm_pre_set_power_state(struct radeon_device *rdev)
6007 
{
6008 
	struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6009 
	struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps;
6010 
	struct radeon_ps *new_ps = &requested_ps;
6011 
 
6012 
	ni_update_requested_ps(rdev, new_ps);
6013 
 
6014 
	si_apply_state_adjust_rules(rdev, &eg_pi->requested_rps);
6015 
 
6016 
	return 0;
6017 
}
6018 
 
6019 
static int si_power_control_set_level(struct radeon_device *rdev)
6020 
{
6021 
	struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps;
6022 
	int ret;
6023 
 
6024 
	ret = si_restrict_performance_levels_before_switch(rdev);
6025 
	if (ret)
6026 
		return ret;
6027 
	ret = si_halt_smc(rdev);
6028 
	if (ret)
6029 
		return ret;
6030 
	ret = si_populate_smc_tdp_limits(rdev, new_ps);
6031 
	if (ret)
6032 
		return ret;
6033 
	ret = si_populate_smc_tdp_limits_2(rdev, new_ps);
6034 
	if (ret)
6035 
		return ret;
6036 
	ret = si_resume_smc(rdev);
6037 
	if (ret)
6038 
		return ret;
6039 
	ret = si_set_sw_state(rdev);
6040 
	if (ret)
6041 
		return ret;
6042 
	return 0;
6043 
}
6044 
 
6045 
int si_dpm_set_power_state(struct radeon_device *rdev)
6046 
{
6047 
	struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6048 
	struct radeon_ps *new_ps = &eg_pi->requested_rps;
6049 
	struct radeon_ps *old_ps = &eg_pi->current_rps;
6050 
	int ret;
6051 
 
6052 
	ret = si_disable_ulv(rdev);
6053 
	if (ret) {
6054 
		DRM_ERROR("si_disable_ulv failed\n");
6055 
		return ret;
6056 
	}
6057 
	ret = si_restrict_performance_levels_before_switch(rdev);
6058 
	if (ret) {
6059 
		DRM_ERROR("si_restrict_performance_levels_before_switch failed\n");
6060 
		return ret;
6061 
	}
6062 
	if (eg_pi->pcie_performance_request)
6063 
		si_request_link_speed_change_before_state_change(rdev, new_ps, old_ps);
6064 
	ni_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps);
6065 
	ret = si_enable_power_containment(rdev, new_ps, false);
6066 
	if (ret) {
6067 
		DRM_ERROR("si_enable_power_containment failed\n");
6068 
		return ret;
6069 
	}
6070 
	ret = si_enable_smc_cac(rdev, new_ps, false);
6071 
	if (ret) {
6072 
		DRM_ERROR("si_enable_smc_cac failed\n");
6073 
		return ret;
6074 
	}
6075 
	ret = si_halt_smc(rdev);
6076 
	if (ret) {
6077 
		DRM_ERROR("si_halt_smc failed\n");
6078 
		return ret;
6079 
	}
6080 
	ret = si_upload_sw_state(rdev, new_ps);
6081 
	if (ret) {
6082 
		DRM_ERROR("si_upload_sw_state failed\n");
6083 
		return ret;
6084 
	}
6085 
	ret = si_upload_smc_data(rdev);
6086 
	if (ret) {
6087 
		DRM_ERROR("si_upload_smc_data failed\n");
6088 
		return ret;
6089 
	}
6090 
	ret = si_upload_ulv_state(rdev);
6091 
	if (ret) {
6092 
		DRM_ERROR("si_upload_ulv_state failed\n");
6093 
		return ret;
6094 
	}
6095 
	if (eg_pi->dynamic_ac_timing) {
6096 
		ret = si_upload_mc_reg_table(rdev, new_ps);
6097 
		if (ret) {
6098 
			DRM_ERROR("si_upload_mc_reg_table failed\n");
6099 
			return ret;
6100 
		}
6101 
	}
6102 
	ret = si_program_memory_timing_parameters(rdev, new_ps);
6103 
	if (ret) {
6104 
		DRM_ERROR("si_program_memory_timing_parameters failed\n");
6105 
		return ret;
6106 
	}
6107 
	si_set_pcie_lane_width_in_smc(rdev, new_ps, old_ps);
6108 
 
6109 
	ret = si_resume_smc(rdev);
6110 
	if (ret) {
6111 
		DRM_ERROR("si_resume_smc failed\n");
6112 
		return ret;
6113 
	}
6114 
	ret = si_set_sw_state(rdev);
6115 
	if (ret) {
6116 
		DRM_ERROR("si_set_sw_state failed\n");
6117 
		return ret;
6118 
	}
6119 
	ni_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps);
6120 
	if (eg_pi->pcie_performance_request)
6121 
		si_notify_link_speed_change_after_state_change(rdev, new_ps, old_ps);
6122 
	ret = si_set_power_state_conditionally_enable_ulv(rdev, new_ps);
6123 
	if (ret) {
6124 
		DRM_ERROR("si_set_power_state_conditionally_enable_ulv failed\n");
6125 
		return ret;
6126 
	}
6127 
	ret = si_enable_smc_cac(rdev, new_ps, true);
6128 
	if (ret) {
6129 
		DRM_ERROR("si_enable_smc_cac failed\n");
6130 
		return ret;
6131 
	}
6132 
	ret = si_enable_power_containment(rdev, new_ps, true);
6133 
	if (ret) {
6134 
		DRM_ERROR("si_enable_power_containment failed\n");
6135 
		return ret;
6136 
	}
6137 
 
6138 
	ret = si_power_control_set_level(rdev);
6139 
	if (ret) {
6140 
		DRM_ERROR("si_power_control_set_level failed\n");
6141 
		return ret;
6142 
	}
6143 
 
6144 
	return 0;
6145 
}
6146 
 
6147 
void si_dpm_post_set_power_state(struct radeon_device *rdev)
6148 
{
6149 
	struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6150 
	struct radeon_ps *new_ps = &eg_pi->requested_rps;
6151 
 
6152 
	ni_update_current_ps(rdev, new_ps);
6153 
}
6154 
 
6155 
 
6156 
void si_dpm_reset_asic(struct radeon_device *rdev)
6157 
{
6158 
	si_restrict_performance_levels_before_switch(rdev);
6159 
	si_disable_ulv(rdev);
6160 
	si_set_boot_state(rdev);
6161 
}
6162 
 
6163 
void si_dpm_display_configuration_changed(struct radeon_device *rdev)
6164 
{
6165 
	si_program_display_gap(rdev);
6166 
}
6167 
 
6168 
union power_info {
6169 
	struct _ATOM_POWERPLAY_INFO info;
6170 
	struct _ATOM_POWERPLAY_INFO_V2 info_2;
6171 
	struct _ATOM_POWERPLAY_INFO_V3 info_3;
6172 
	struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
6173 
	struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
6174 
	struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
6175 
};
6176 
 
6177 
union pplib_clock_info {
6178 
	struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
6179 
	struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
6180 
	struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
6181 
	struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
6182 
	struct _ATOM_PPLIB_SI_CLOCK_INFO si;
6183 
};
6184 
 
6185 
union pplib_power_state {
6186 
	struct _ATOM_PPLIB_STATE v1;
6187 
	struct _ATOM_PPLIB_STATE_V2 v2;
6188 
};
6189 
 
6190 
static void si_parse_pplib_non_clock_info(struct radeon_device *rdev,
6191 
					  struct radeon_ps *rps,
6192 
					  struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
6193 
					  u8 table_rev)
6194 
{
6195 
	rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
6196 
	rps->class = le16_to_cpu(non_clock_info->usClassification);
6197 
	rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
6198 
 
6199 
	if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
6200 
		rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
6201 
		rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
6202 
	} else if (r600_is_uvd_state(rps->class, rps->class2)) {
6203 
		rps->vclk = RV770_DEFAULT_VCLK_FREQ;
6204 
		rps->dclk = RV770_DEFAULT_DCLK_FREQ;
6205 
	} else {
6206 
		rps->vclk = 0;
6207 
		rps->dclk = 0;
6208 
	}
6209 
 
6210 
	if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)
6211 
		rdev->pm.dpm.boot_ps = rps;
6212 
	if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
6213 
		rdev->pm.dpm.uvd_ps = rps;
6214 
}
6215 
 
6216 
static void si_parse_pplib_clock_info(struct radeon_device *rdev,
6217 
				      struct radeon_ps *rps, int index,
6218 
				      union pplib_clock_info *clock_info)
6219 
{
6220 
	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
6221 
	struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6222 
	struct si_power_info *si_pi = si_get_pi(rdev);
6223 
	struct ni_ps *ps = ni_get_ps(rps);
6224 
	u16 leakage_voltage;
6225 
	struct rv7xx_pl *pl = &ps->performance_levels[index];
6226 
	int ret;
6227 
 
6228 
	ps->performance_level_count = index + 1;
6229 
 
6230 
	pl->sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
6231 
	pl->sclk |= clock_info->si.ucEngineClockHigh << 16;
6232 
	pl->mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
6233 
	pl->mclk |= clock_info->si.ucMemoryClockHigh << 16;
6234 
 
6235 
	pl->vddc = le16_to_cpu(clock_info->si.usVDDC);
6236 
	pl->vddci = le16_to_cpu(clock_info->si.usVDDCI);
6237 
	pl->flags = le32_to_cpu(clock_info->si.ulFlags);
6238 
	pl->pcie_gen = r600_get_pcie_gen_support(rdev,
6239 
						 si_pi->sys_pcie_mask,
6240 
						 si_pi->boot_pcie_gen,
6241 
						 clock_info->si.ucPCIEGen);
6242 
 
6243 
	/* patch up vddc if necessary */
6244 
	ret = si_get_leakage_voltage_from_leakage_index(rdev, pl->vddc,
6245 
							&leakage_voltage);
6246 
	if (ret == 0)
6247 
		pl->vddc = leakage_voltage;
6248 
 
6249 
	if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) {
6250 
		pi->acpi_vddc = pl->vddc;
6251 
		eg_pi->acpi_vddci = pl->vddci;
6252 
		si_pi->acpi_pcie_gen = pl->pcie_gen;
6253 
	}
6254 
 
6255 
	if ((rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) &&
6256 
	    index == 0) {
6257 
		/* XXX disable for A0 tahiti */
5179 serge 6258 
		si_pi->ulv.supported = false;
5078 serge 6259 
		si_pi->ulv.pl = *pl;
6260 
		si_pi->ulv.one_pcie_lane_in_ulv = false;
6261 
		si_pi->ulv.volt_change_delay = SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT;
6262 
		si_pi->ulv.cg_ulv_parameter = SISLANDS_CGULVPARAMETER_DFLT;
6263 
		si_pi->ulv.cg_ulv_control = SISLANDS_CGULVCONTROL_DFLT;
6264 
	}
6265 
 
6266 
	if (pi->min_vddc_in_table > pl->vddc)
6267 
		pi->min_vddc_in_table = pl->vddc;
6268 
 
6269 
	if (pi->max_vddc_in_table < pl->vddc)
6270 
		pi->max_vddc_in_table = pl->vddc;
6271 
 
6272 
	/* patch up boot state */
6273 
	if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
6274 
		u16 vddc, vddci, mvdd;
6275 
		radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd);
6276 
		pl->mclk = rdev->clock.default_mclk;
6277 
		pl->sclk = rdev->clock.default_sclk;
6278 
		pl->vddc = vddc;
6279 
		pl->vddci = vddci;
6280 
		si_pi->mvdd_bootup_value = mvdd;
6281 
	}
6282 
 
6283 
	if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) ==
6284 
	    ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
6285 
		rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk;
6286 
		rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk;
6287 
		rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc;
6288 
		rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci;
6289 
	}
6290 
}
6291 
 
6292 
static int si_parse_power_table(struct radeon_device *rdev)
6293 
{
6294 
	struct radeon_mode_info *mode_info = &rdev->mode_info;
6295 
	struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
6296 
	union pplib_power_state *power_state;
6297 
	int i, j, k, non_clock_array_index, clock_array_index;
6298 
	union pplib_clock_info *clock_info;
6299 
	struct _StateArray *state_array;
6300 
	struct _ClockInfoArray *clock_info_array;
6301 
	struct _NonClockInfoArray *non_clock_info_array;
6302 
	union power_info *power_info;
6303 
	int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
6304 
        u16 data_offset;
6305 
	u8 frev, crev;
6306 
	u8 *power_state_offset;
6307 
	struct ni_ps *ps;
6308 
 
6309 
	if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
6310 
				   &frev, &crev, &data_offset))
6311 
		return -EINVAL;
6312 
	power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
6313 
 
6314 
	state_array = (struct _StateArray *)
6315 
		(mode_info->atom_context->bios + data_offset +
6316 
		 le16_to_cpu(power_info->pplib.usStateArrayOffset));
6317 
	clock_info_array = (struct _ClockInfoArray *)
6318 
		(mode_info->atom_context->bios + data_offset +
6319 
		 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
6320 
	non_clock_info_array = (struct _NonClockInfoArray *)
6321 
		(mode_info->atom_context->bios + data_offset +
6322 
		 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
6323 
 
6324 
	rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) *
6325 
				  state_array->ucNumEntries, GFP_KERNEL);
6326 
	if (!rdev->pm.dpm.ps)
6327 
		return -ENOMEM;
6328 
	power_state_offset = (u8 *)state_array->states;
6329 
	for (i = 0; i < state_array->ucNumEntries; i++) {
6330 
		u8 *idx;
6331 
		power_state = (union pplib_power_state *)power_state_offset;
6332 
		non_clock_array_index = power_state->v2.nonClockInfoIndex;
6333 
		non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
6334 
			&non_clock_info_array->nonClockInfo[non_clock_array_index];
6335 
		if (!rdev->pm.power_state[i].clock_info)
6336 
			return -EINVAL;
6337 
		ps = kzalloc(sizeof(struct ni_ps), GFP_KERNEL);
6338 
		if (ps == NULL) {
6339 
			kfree(rdev->pm.dpm.ps);
6340 
			return -ENOMEM;
6341 
		}
6342 
		rdev->pm.dpm.ps[i].ps_priv = ps;
6343 
		si_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i],
6344 
					      non_clock_info,
6345 
					      non_clock_info_array->ucEntrySize);
6346 
		k = 0;
6347 
		idx = (u8 *)&power_state->v2.clockInfoIndex[0];
6348 
		for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
6349 
			clock_array_index = idx[j];
6350 
			if (clock_array_index >= clock_info_array->ucNumEntries)
6351 
				continue;
6352 
			if (k >= SISLANDS_MAX_HARDWARE_POWERLEVELS)
6353 
				break;
6354 
			clock_info = (union pplib_clock_info *)
6355 
				((u8 *)&clock_info_array->clockInfo[0] +
6356 
				 (clock_array_index * clock_info_array->ucEntrySize));
6357 
			si_parse_pplib_clock_info(rdev,
6358 
						  &rdev->pm.dpm.ps[i], k,
6359 
						  clock_info);
6360 
			k++;
6361 
		}
6362 
		power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
6363 
	}
6364 
	rdev->pm.dpm.num_ps = state_array->ucNumEntries;
6365 
	return 0;
6366 
}
6367 
 
6368 
int si_dpm_init(struct radeon_device *rdev)
6369 
{
6370 
	struct rv7xx_power_info *pi;
6371 
	struct evergreen_power_info *eg_pi;
6372 
	struct ni_power_info *ni_pi;
6373 
	struct si_power_info *si_pi;
6374 
	struct atom_clock_dividers dividers;
6375 
	int ret;
6376 
	u32 mask;
6377 
 
6378 
	si_pi = kzalloc(sizeof(struct si_power_info), GFP_KERNEL);
6379 
	if (si_pi == NULL)
6380 
		return -ENOMEM;
6381 
	rdev->pm.dpm.priv = si_pi;
6382 
	ni_pi = &si_pi->ni;
6383 
	eg_pi = &ni_pi->eg;
6384 
	pi = &eg_pi->rv7xx;
6385 
 
6386 
	ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask);
6387 
	if (ret)
6388 
		si_pi->sys_pcie_mask = 0;
6389 
	else
6390 
		si_pi->sys_pcie_mask = mask;
6391 
	si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID;
6392 
	si_pi->boot_pcie_gen = si_get_current_pcie_speed(rdev);
6393 
 
6394 
	si_set_max_cu_value(rdev);
6395 
 
6396 
	rv770_get_max_vddc(rdev);
6397 
	si_get_leakage_vddc(rdev);
6398 
	si_patch_dependency_tables_based_on_leakage(rdev);
6399 
 
6400 
	pi->acpi_vddc = 0;
6401 
	eg_pi->acpi_vddci = 0;
6402 
	pi->min_vddc_in_table = 0;
6403 
	pi->max_vddc_in_table = 0;
6404 
 
6405 
	ret = r600_get_platform_caps(rdev);
6406 
	if (ret)
6407 
		return ret;
6408 
 
6409 
	ret = si_parse_power_table(rdev);
6410 
	if (ret)
6411 
		return ret;
6412 
	ret = r600_parse_extended_power_table(rdev);
6413 
	if (ret)
6414 
		return ret;
6415 
 
6416 
	rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries =
6417 
		kzalloc(4 * sizeof(struct radeon_clock_voltage_dependency_entry), GFP_KERNEL);
6418 
	if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) {
6419 
		r600_free_extended_power_table(rdev);
6420 
		return -ENOMEM;
6421 
	}
6422 
	rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4;
6423 
	rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0;
6424 
	rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0;
6425 
	rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000;
6426 
	rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720;
6427 
	rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000;
6428 
	rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810;
6429 
	rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000;
6430 
	rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900;
6431 
 
6432 
	if (rdev->pm.dpm.voltage_response_time == 0)
6433 
		rdev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT;
6434 
	if (rdev->pm.dpm.backbias_response_time == 0)
6435 
		rdev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT;
6436 
 
6437 
	ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
6438 
					     0, false, ÷rs);
6439 
	if (ret)
6440 
		pi->ref_div = dividers.ref_div + 1;
6441 
	else
6442 
		pi->ref_div = R600_REFERENCEDIVIDER_DFLT;
6443 
 
6444 
	eg_pi->smu_uvd_hs = false;
6445 
 
6446 
	pi->mclk_strobe_mode_threshold = 40000;
6447 
	if (si_is_special_1gb_platform(rdev))
6448 
		pi->mclk_stutter_mode_threshold = 0;
6449 
	else
6450 
		pi->mclk_stutter_mode_threshold = pi->mclk_strobe_mode_threshold;
6451 
	pi->mclk_edc_enable_threshold = 40000;
6452 
	eg_pi->mclk_edc_wr_enable_threshold = 40000;
6453 
 
6454 
	ni_pi->mclk_rtt_mode_threshold = eg_pi->mclk_edc_wr_enable_threshold;
6455 
 
6456 
	pi->voltage_control =
6457 
		radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC,
6458 
					    VOLTAGE_OBJ_GPIO_LUT);
6459 
	if (!pi->voltage_control) {
6460 
		si_pi->voltage_control_svi2 =
6461 
			radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC,
6462 
						    VOLTAGE_OBJ_SVID2);
6463 
		if (si_pi->voltage_control_svi2)
6464 
			radeon_atom_get_svi2_info(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC,
6465 
						  &si_pi->svd_gpio_id, &si_pi->svc_gpio_id);
6466 
	}
6467 
 
6468 
	pi->mvdd_control =
6469 
		radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_MVDDC,
6470 
					    VOLTAGE_OBJ_GPIO_LUT);
6471 
 
6472 
	eg_pi->vddci_control =
6473 
		radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI,
6474 
					    VOLTAGE_OBJ_GPIO_LUT);
6475 
	if (!eg_pi->vddci_control)
6476 
		si_pi->vddci_control_svi2 =
6477 
			radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI,
6478 
						    VOLTAGE_OBJ_SVID2);
6479 
 
6480 
	si_pi->vddc_phase_shed_control =
6481 
		radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC,
6482 
					    VOLTAGE_OBJ_PHASE_LUT);
6483 
 
6484 
	rv770_get_engine_memory_ss(rdev);
6485 
 
6486 
	pi->asi = RV770_ASI_DFLT;
6487 
	pi->pasi = CYPRESS_HASI_DFLT;
6488 
	pi->vrc = SISLANDS_VRC_DFLT;
6489 
 
6490 
	pi->gfx_clock_gating = true;
6491 
 
6492 
	eg_pi->sclk_deep_sleep = true;
6493 
	si_pi->sclk_deep_sleep_above_low = false;
6494 
 
6495 
	if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE)
6496 
		pi->thermal_protection = true;
6497 
	else
6498 
		pi->thermal_protection = false;
6499 
 
6500 
	eg_pi->dynamic_ac_timing = true;
6501 
 
6502 
	eg_pi->light_sleep = true;
6503 
#if defined(CONFIG_ACPI)
6504 
	eg_pi->pcie_performance_request =
6505 
		radeon_acpi_is_pcie_performance_request_supported(rdev);
6506 
#else
6507 
	eg_pi->pcie_performance_request = false;
6508 
#endif
6509 
 
6510 
	si_pi->sram_end = SMC_RAM_END;
6511 
 
6512 
	rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 4;
6513 
	rdev->pm.dpm.dyn_state.sclk_mclk_delta = 15000;
6514 
	rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200;
6515 
	rdev->pm.dpm.dyn_state.valid_sclk_values.count = 0;
6516 
	rdev->pm.dpm.dyn_state.valid_sclk_values.values = NULL;
6517 
	rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0;
6518 
	rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL;
6519 
 
6520 
	si_initialize_powertune_defaults(rdev);
6521 
 
6522 
	/* make sure dc limits are valid */
6523 
	if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) ||
6524 
	    (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0))
6525 
		rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc =
6526 
			rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
6527 
 
6528 
	return 0;
6529 
}
6530 
 
6531 
void si_dpm_fini(struct radeon_device *rdev)
6532 
{
6533 
	int i;
6534 
 
6535 
	for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
6536 
		kfree(rdev->pm.dpm.ps[i].ps_priv);
6537 
	}
6538 
	kfree(rdev->pm.dpm.ps);
6539 
	kfree(rdev->pm.dpm.priv);
6540 
	kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries);
6541 
	r600_free_extended_power_table(rdev);
6542 
}
6543 
 
6544 
void si_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
6545 
						    struct seq_file *m)
6546 
{
6547 
	struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6548 
	struct radeon_ps *rps = &eg_pi->current_rps;
6549 
	struct ni_ps *ps = ni_get_ps(rps);
6550 
	struct rv7xx_pl *pl;
6551 
	u32 current_index =
6552 
		(RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>
6553 
		CURRENT_STATE_INDEX_SHIFT;
6554 
 
6555 
	if (current_index >= ps->performance_level_count) {
6556 
		seq_printf(m, "invalid dpm profile %d\n", current_index);
6557 
	} else {
6558 
		pl = &ps->performance_levels[current_index];
6559 
		seq_printf(m, "uvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
6560 
		seq_printf(m, "power level %d    sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n",
6561 
			   current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1);
6562 
	}
6563 
}