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5078 | serge | 1 | /* |
2 | * Copyright 2013 Advanced Micro Devices, Inc. |
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3 | * |
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4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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5 | * copy of this software and associated documentation files (the "Software"), |
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6 | * to deal in the Software without restriction, including without limitation |
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7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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8 | * and/or sell copies of the Software, and to permit persons to whom the |
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9 | * Software is furnished to do so, subject to the following conditions: |
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10 | * |
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11 | * The above copyright notice and this permission notice shall be included in |
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12 | * all copies or substantial portions of the Software. |
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13 | * |
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14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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20 | * OTHER DEALINGS IN THE SOFTWARE. |
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21 | * |
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22 | * Authors: Alex Deucher |
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23 | */ |
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24 | #include |
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25 | #include "radeon.h" |
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26 | #include "radeon_asic.h" |
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27 | #include "radeon_trace.h" |
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28 | #include "sid.h" |
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29 | |||
30 | u32 si_gpu_check_soft_reset(struct radeon_device *rdev); |
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31 | |||
32 | /** |
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33 | * si_dma_is_lockup - Check if the DMA engine is locked up |
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34 | * |
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35 | * @rdev: radeon_device pointer |
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36 | * @ring: radeon_ring structure holding ring information |
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37 | * |
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38 | * Check if the async DMA engine is locked up. |
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39 | * Returns true if the engine appears to be locked up, false if not. |
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40 | */ |
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41 | bool si_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring) |
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42 | { |
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43 | u32 reset_mask = si_gpu_check_soft_reset(rdev); |
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44 | u32 mask; |
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45 | |||
46 | if (ring->idx == R600_RING_TYPE_DMA_INDEX) |
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47 | mask = RADEON_RESET_DMA; |
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48 | else |
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49 | mask = RADEON_RESET_DMA1; |
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50 | |||
51 | if (!(reset_mask & mask)) { |
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52 | radeon_ring_lockup_update(rdev, ring); |
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53 | return false; |
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54 | } |
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55 | return radeon_ring_test_lockup(rdev, ring); |
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56 | } |
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57 | |||
58 | /** |
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59 | * si_dma_vm_copy_pages - update PTEs by copying them from the GART |
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60 | * |
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61 | * @rdev: radeon_device pointer |
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62 | * @ib: indirect buffer to fill with commands |
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63 | * @pe: addr of the page entry |
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64 | * @src: src addr where to copy from |
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65 | * @count: number of page entries to update |
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66 | * |
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67 | * Update PTEs by copying them from the GART using the DMA (SI). |
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68 | */ |
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69 | void si_dma_vm_copy_pages(struct radeon_device *rdev, |
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6104 | serge | 70 | struct radeon_ib *ib, |
5078 | serge | 71 | uint64_t pe, uint64_t src, |
72 | unsigned count) |
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73 | { |
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6104 | serge | 74 | while (count) { |
75 | unsigned bytes = count * 8; |
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76 | if (bytes > 0xFFFF8) |
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77 | bytes = 0xFFFF8; |
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5078 | serge | 78 | |
6104 | serge | 79 | ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_COPY, |
80 | 1, 0, 0, bytes); |
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81 | ib->ptr[ib->length_dw++] = lower_32_bits(pe); |
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82 | ib->ptr[ib->length_dw++] = lower_32_bits(src); |
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83 | ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff; |
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84 | ib->ptr[ib->length_dw++] = upper_32_bits(src) & 0xff; |
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5078 | serge | 85 | |
6104 | serge | 86 | pe += bytes; |
87 | src += bytes; |
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88 | count -= bytes / 8; |
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89 | } |
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5078 | serge | 90 | } |
91 | |||
92 | /** |
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93 | * si_dma_vm_write_pages - update PTEs by writing them manually |
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94 | * |
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95 | * @rdev: radeon_device pointer |
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96 | * @ib: indirect buffer to fill with commands |
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97 | * @pe: addr of the page entry |
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98 | * @addr: dst addr to write into pe |
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99 | * @count: number of page entries to update |
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100 | * @incr: increase next addr by incr bytes |
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101 | * @flags: access flags |
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102 | * |
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103 | * Update PTEs by writing them manually using the DMA (SI). |
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104 | */ |
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105 | void si_dma_vm_write_pages(struct radeon_device *rdev, |
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106 | struct radeon_ib *ib, |
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107 | uint64_t pe, |
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108 | uint64_t addr, unsigned count, |
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109 | uint32_t incr, uint32_t flags) |
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110 | { |
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111 | uint64_t value; |
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112 | unsigned ndw; |
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113 | |||
6104 | serge | 114 | while (count) { |
115 | ndw = count * 2; |
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116 | if (ndw > 0xFFFFE) |
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117 | ndw = 0xFFFFE; |
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5078 | serge | 118 | |
6104 | serge | 119 | /* for non-physically contiguous pages (system) */ |
120 | ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 0, ndw); |
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121 | ib->ptr[ib->length_dw++] = pe; |
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122 | ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff; |
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123 | for (; ndw > 0; ndw -= 2, --count, pe += 8) { |
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5078 | serge | 124 | if (flags & R600_PTE_SYSTEM) { |
125 | value = radeon_vm_map_gart(rdev, addr); |
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126 | } else if (flags & R600_PTE_VALID) { |
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127 | value = addr; |
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128 | } else { |
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129 | value = 0; |
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130 | } |
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6104 | serge | 131 | addr += incr; |
132 | value |= flags; |
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133 | ib->ptr[ib->length_dw++] = value; |
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134 | ib->ptr[ib->length_dw++] = upper_32_bits(value); |
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5078 | serge | 135 | } |
6104 | serge | 136 | } |
5078 | serge | 137 | } |
138 | |||
139 | /** |
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140 | * si_dma_vm_set_pages - update the page tables using the DMA |
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141 | * |
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142 | * @rdev: radeon_device pointer |
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143 | * @ib: indirect buffer to fill with commands |
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144 | * @pe: addr of the page entry |
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145 | * @addr: dst addr to write into pe |
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146 | * @count: number of page entries to update |
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147 | * @incr: increase next addr by incr bytes |
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148 | * @flags: access flags |
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149 | * |
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150 | * Update the page tables using the DMA (SI). |
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151 | */ |
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152 | void si_dma_vm_set_pages(struct radeon_device *rdev, |
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153 | struct radeon_ib *ib, |
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154 | uint64_t pe, |
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155 | uint64_t addr, unsigned count, |
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156 | uint32_t incr, uint32_t flags) |
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157 | { |
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158 | uint64_t value; |
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159 | unsigned ndw; |
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160 | |||
6104 | serge | 161 | while (count) { |
162 | ndw = count * 2; |
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163 | if (ndw > 0xFFFFE) |
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164 | ndw = 0xFFFFE; |
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5078 | serge | 165 | |
6104 | serge | 166 | if (flags & R600_PTE_VALID) |
167 | value = addr; |
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168 | else |
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169 | value = 0; |
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5078 | serge | 170 | |
6104 | serge | 171 | /* for physically contiguous pages (vram) */ |
172 | ib->ptr[ib->length_dw++] = DMA_PTE_PDE_PACKET(ndw); |
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173 | ib->ptr[ib->length_dw++] = pe; /* dst addr */ |
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174 | ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff; |
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175 | ib->ptr[ib->length_dw++] = flags; /* mask */ |
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176 | ib->ptr[ib->length_dw++] = 0; |
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177 | ib->ptr[ib->length_dw++] = value; /* value */ |
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178 | ib->ptr[ib->length_dw++] = upper_32_bits(value); |
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179 | ib->ptr[ib->length_dw++] = incr; /* increment size */ |
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180 | ib->ptr[ib->length_dw++] = 0; |
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181 | pe += ndw * 4; |
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182 | addr += (ndw / 2) * incr; |
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183 | count -= ndw / 2; |
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184 | } |
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5078 | serge | 185 | } |
186 | |||
5271 | serge | 187 | void si_dma_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring, |
188 | unsigned vm_id, uint64_t pd_addr) |
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189 | |||
5078 | serge | 190 | { |
191 | radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0, 0)); |
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5271 | serge | 192 | if (vm_id < 8) { |
193 | radeon_ring_write(ring, (0xf << 16) | ((VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm_id << 2)) >> 2)); |
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5078 | serge | 194 | } else { |
5271 | serge | 195 | radeon_ring_write(ring, (0xf << 16) | ((VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((vm_id - 8) << 2)) >> 2)); |
5078 | serge | 196 | } |
5271 | serge | 197 | radeon_ring_write(ring, pd_addr >> 12); |
5078 | serge | 198 | |
199 | /* flush hdp cache */ |
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200 | radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0, 0)); |
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201 | radeon_ring_write(ring, (0xf << 16) | (HDP_MEM_COHERENCY_FLUSH_CNTL >> 2)); |
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202 | radeon_ring_write(ring, 1); |
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203 | |||
204 | /* bits 0-7 are the VM contexts0-7 */ |
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205 | radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0, 0)); |
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206 | radeon_ring_write(ring, (0xf << 16) | (VM_INVALIDATE_REQUEST >> 2)); |
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5271 | serge | 207 | radeon_ring_write(ring, 1 << vm_id); |
6104 | serge | 208 | |
209 | /* wait for invalidate to complete */ |
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210 | radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_POLL_REG_MEM, 0, 0, 0, 0)); |
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211 | radeon_ring_write(ring, VM_INVALIDATE_REQUEST); |
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212 | radeon_ring_write(ring, 0xff << 16); /* retry */ |
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213 | radeon_ring_write(ring, 1 << vm_id); /* mask */ |
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214 | radeon_ring_write(ring, 0); /* value */ |
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215 | radeon_ring_write(ring, (0 << 28) | 0x20); /* func(always) | poll interval */ |
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5078 | serge | 216 | } |
217 | |||
218 | /** |
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219 | * si_copy_dma - copy pages using the DMA engine |
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220 | * |
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221 | * @rdev: radeon_device pointer |
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222 | * @src_offset: src GPU address |
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223 | * @dst_offset: dst GPU address |
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224 | * @num_gpu_pages: number of GPU pages to xfer |
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5271 | serge | 225 | * @resv: reservation object to sync to |
5078 | serge | 226 | * |
227 | * Copy GPU paging using the DMA engine (SI). |
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228 | * Used by the radeon ttm implementation to move pages if |
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229 | * registered as the asic copy callback. |
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230 | */ |
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5271 | serge | 231 | struct radeon_fence *si_copy_dma(struct radeon_device *rdev, |
6104 | serge | 232 | uint64_t src_offset, uint64_t dst_offset, |
233 | unsigned num_gpu_pages, |
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5271 | serge | 234 | struct reservation_object *resv) |
5078 | serge | 235 | { |
5271 | serge | 236 | struct radeon_fence *fence; |
237 | struct radeon_sync sync; |
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5078 | serge | 238 | int ring_index = rdev->asic->copy.dma_ring_index; |
239 | struct radeon_ring *ring = &rdev->ring[ring_index]; |
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240 | u32 size_in_bytes, cur_size_in_bytes; |
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241 | int i, num_loops; |
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242 | int r = 0; |
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243 | |||
5271 | serge | 244 | radeon_sync_create(&sync); |
5078 | serge | 245 | |
246 | size_in_bytes = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT); |
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247 | num_loops = DIV_ROUND_UP(size_in_bytes, 0xfffff); |
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248 | r = radeon_ring_lock(rdev, ring, num_loops * 5 + 11); |
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249 | if (r) { |
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250 | DRM_ERROR("radeon: moving bo (%d).\n", r); |
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5271 | serge | 251 | radeon_sync_free(rdev, &sync, NULL); |
252 | return ERR_PTR(r); |
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5078 | serge | 253 | } |
254 | |||
5271 | serge | 255 | radeon_sync_resv(rdev, &sync, resv, false); |
256 | radeon_sync_rings(rdev, &sync, ring->idx); |
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5078 | serge | 257 | |
258 | for (i = 0; i < num_loops; i++) { |
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259 | cur_size_in_bytes = size_in_bytes; |
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260 | if (cur_size_in_bytes > 0xFFFFF) |
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261 | cur_size_in_bytes = 0xFFFFF; |
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262 | size_in_bytes -= cur_size_in_bytes; |
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263 | radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_COPY, 1, 0, 0, cur_size_in_bytes)); |
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264 | radeon_ring_write(ring, lower_32_bits(dst_offset)); |
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265 | radeon_ring_write(ring, lower_32_bits(src_offset)); |
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266 | radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff); |
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267 | radeon_ring_write(ring, upper_32_bits(src_offset) & 0xff); |
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268 | src_offset += cur_size_in_bytes; |
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269 | dst_offset += cur_size_in_bytes; |
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270 | } |
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271 | |||
5271 | serge | 272 | r = radeon_fence_emit(rdev, &fence, ring->idx); |
5078 | serge | 273 | if (r) { |
274 | radeon_ring_unlock_undo(rdev, ring); |
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5271 | serge | 275 | radeon_sync_free(rdev, &sync, NULL); |
276 | return ERR_PTR(r); |
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5078 | serge | 277 | } |
278 | |||
279 | radeon_ring_unlock_commit(rdev, ring, false); |
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5271 | serge | 280 | radeon_sync_free(rdev, &sync, fence); |
5078 | serge | 281 | |
5271 | serge | 282 | return fence; |
5078 | serge | 283 | }>><>><>><>><>><>><>><>><>><>><>><>> |
284 |