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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 1246 | serge | 1 | /* |
| 2 | * Copyright 2008 Advanced Micro Devices, Inc. |
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| 3 | * Copyright 2008 Red Hat Inc. |
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| 4 | * Copyright 2009 Jerome Glisse. |
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| 5 | * |
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| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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| 7 | * copy of this software and associated documentation files (the "Software"), |
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| 8 | * to deal in the Software without restriction, including without limitation |
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| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
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| 11 | * Software is furnished to do so, subject to the following conditions: |
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| 12 | * |
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| 13 | * The above copyright notice and this permission notice shall be included in |
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| 14 | * all copies or substantial portions of the Software. |
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| 15 | * |
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| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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| 19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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| 20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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| 21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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| 22 | * OTHER DEALINGS IN THE SOFTWARE. |
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| 23 | * |
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| 24 | * Authors: Dave Airlie |
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| 25 | * Alex Deucher |
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| 26 | * Jerome Glisse |
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| 27 | */ |
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| 1413 | serge | 28 | #include |
| 1246 | serge | 29 | //#include |
| 1963 | serge | 30 | #include |
| 2997 | Serge | 31 | #include |
| 1246 | serge | 32 | #include "radeon.h" |
| 1963 | serge | 33 | #include "radeon_asic.h" |
| 2997 | Serge | 34 | #include |
| 1246 | serge | 35 | #include "rv770d.h" |
| 36 | #include "atom.h" |
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| 37 | #include "avivod.h" |
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| 38 | |||
| 39 | #define R700_PFP_UCODE_SIZE 848 |
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| 40 | #define R700_PM4_UCODE_SIZE 1360 |
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| 41 | |||
| 42 | static void rv770_gpu_init(struct radeon_device *rdev); |
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| 43 | void rv770_fini(struct radeon_device *rdev); |
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| 1963 | serge | 44 | static void rv770_pcie_gen2_enable(struct radeon_device *rdev); |
| 1246 | serge | 45 | |
| 46 | |||
| 47 | /* |
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| 48 | * GART |
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| 49 | */ |
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| 2997 | Serge | 50 | static int rv770_pcie_gart_enable(struct radeon_device *rdev) |
| 1246 | serge | 51 | { |
| 52 | u32 tmp; |
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| 53 | int r, i; |
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| 54 | |||
| 2997 | Serge | 55 | if (rdev->gart.robj == NULL) { |
| 1246 | serge | 56 | dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); |
| 57 | return -EINVAL; |
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| 58 | } |
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| 59 | r = radeon_gart_table_vram_pin(rdev); |
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| 60 | if (r) |
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| 61 | return r; |
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| 1430 | serge | 62 | radeon_gart_restore(rdev); |
| 1246 | serge | 63 | /* Setup L2 cache */ |
| 64 | WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | |
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| 65 | ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | |
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| 66 | EFFECTIVE_L2_QUEUE_SIZE(7)); |
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| 67 | WREG32(VM_L2_CNTL2, 0); |
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| 68 | WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); |
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| 69 | /* Setup TLB control */ |
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| 70 | tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | |
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| 71 | SYSTEM_ACCESS_MODE_NOT_IN_SYS | |
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| 72 | SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU | |
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| 73 | EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5); |
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| 74 | WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp); |
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| 75 | WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp); |
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| 76 | WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp); |
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| 2997 | Serge | 77 | if (rdev->family == CHIP_RV740) |
| 78 | WREG32(MC_VM_MD_L1_TLB3_CNTL, tmp); |
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| 1246 | serge | 79 | WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp); |
| 80 | WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); |
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| 81 | WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp); |
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| 82 | WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp); |
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| 83 | WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); |
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| 84 | WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12); |
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| 85 | WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); |
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| 86 | WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | |
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| 87 | RANGE_PROTECTION_FAULT_ENABLE_DEFAULT); |
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| 88 | WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, |
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| 89 | (u32)(rdev->dummy_page.addr >> 12)); |
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| 90 | for (i = 1; i < 7; i++) |
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| 91 | WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); |
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| 92 | |||
| 93 | r600_pcie_gart_tlb_flush(rdev); |
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| 2997 | Serge | 94 | DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", |
| 95 | (unsigned)(rdev->mc.gtt_size >> 20), |
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| 96 | (unsigned long long)rdev->gart.table_addr); |
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| 1246 | serge | 97 | rdev->gart.ready = true; |
| 98 | return 0; |
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| 99 | } |
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| 100 | |||
| 2997 | Serge | 101 | static void rv770_pcie_gart_disable(struct radeon_device *rdev) |
| 1246 | serge | 102 | { |
| 103 | u32 tmp; |
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| 2997 | Serge | 104 | int i; |
| 1246 | serge | 105 | |
| 106 | /* Disable all tables */ |
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| 107 | for (i = 0; i < 7; i++) |
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| 108 | WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); |
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| 109 | |||
| 110 | /* Setup L2 cache */ |
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| 111 | WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING | |
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| 112 | EFFECTIVE_L2_QUEUE_SIZE(7)); |
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| 113 | WREG32(VM_L2_CNTL2, 0); |
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| 114 | WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); |
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| 115 | /* Setup TLB control */ |
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| 116 | tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5); |
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| 117 | WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp); |
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| 118 | WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp); |
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| 119 | WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp); |
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| 120 | WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp); |
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| 121 | WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); |
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| 122 | WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp); |
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| 123 | WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp); |
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| 2997 | Serge | 124 | radeon_gart_table_vram_unpin(rdev); |
| 1246 | serge | 125 | } |
| 126 | |||
| 2997 | Serge | 127 | static void rv770_pcie_gart_fini(struct radeon_device *rdev) |
| 1246 | serge | 128 | { |
| 1963 | serge | 129 | radeon_gart_fini(rdev); |
| 1246 | serge | 130 | rv770_pcie_gart_disable(rdev); |
| 1404 | serge | 131 | radeon_gart_table_vram_free(rdev); |
| 1246 | serge | 132 | } |
| 133 | |||
| 134 | |||
| 2997 | Serge | 135 | static void rv770_agp_enable(struct radeon_device *rdev) |
| 1246 | serge | 136 | { |
| 137 | u32 tmp; |
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| 138 | int i; |
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| 139 | |||
| 140 | /* Setup L2 cache */ |
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| 141 | WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | |
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| 142 | ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | |
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| 143 | EFFECTIVE_L2_QUEUE_SIZE(7)); |
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| 144 | WREG32(VM_L2_CNTL2, 0); |
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| 145 | WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); |
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| 146 | /* Setup TLB control */ |
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| 147 | tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | |
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| 148 | SYSTEM_ACCESS_MODE_NOT_IN_SYS | |
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| 149 | SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU | |
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| 150 | EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5); |
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| 151 | WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp); |
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| 152 | WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp); |
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| 153 | WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp); |
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| 154 | WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp); |
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| 155 | WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); |
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| 156 | WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp); |
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| 157 | WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp); |
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| 158 | for (i = 0; i < 7; i++) |
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| 159 | WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); |
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| 160 | } |
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| 161 | |||
| 162 | static void rv770_mc_program(struct radeon_device *rdev) |
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| 163 | { |
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| 164 | struct rv515_mc_save save; |
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| 165 | u32 tmp; |
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| 166 | int i, j; |
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| 167 | |||
| 168 | /* Initialize HDP */ |
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| 169 | for (i = 0, j = 0; i < 32; i++, j += 0x18) { |
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| 170 | WREG32((0x2c14 + j), 0x00000000); |
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| 171 | WREG32((0x2c18 + j), 0x00000000); |
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| 172 | WREG32((0x2c1c + j), 0x00000000); |
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| 173 | WREG32((0x2c20 + j), 0x00000000); |
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| 174 | WREG32((0x2c24 + j), 0x00000000); |
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| 175 | } |
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| 1963 | serge | 176 | /* r7xx hw bug. Read from HDP_DEBUG1 rather |
| 177 | * than writing to HDP_REG_COHERENCY_FLUSH_CNTL |
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| 178 | */ |
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| 179 | tmp = RREG32(HDP_DEBUG1); |
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| 1246 | serge | 180 | |
| 181 | rv515_mc_stop(rdev, &save); |
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| 182 | if (r600_mc_wait_for_idle(rdev)) { |
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| 183 | dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); |
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| 184 | } |
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| 185 | /* Lockout access through VGA aperture*/ |
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| 186 | WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE); |
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| 187 | /* Update configuration */ |
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| 188 | if (rdev->flags & RADEON_IS_AGP) { |
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| 189 | if (rdev->mc.vram_start < rdev->mc.gtt_start) { |
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| 190 | /* VRAM before AGP */ |
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| 191 | WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, |
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| 192 | rdev->mc.vram_start >> 12); |
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| 193 | WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, |
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| 194 | rdev->mc.gtt_end >> 12); |
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| 195 | } else { |
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| 196 | /* VRAM after AGP */ |
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| 197 | WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, |
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| 198 | rdev->mc.gtt_start >> 12); |
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| 199 | WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, |
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| 200 | rdev->mc.vram_end >> 12); |
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| 201 | } |
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| 202 | } else { |
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| 203 | WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, |
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| 204 | rdev->mc.vram_start >> 12); |
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| 205 | WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, |
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| 206 | rdev->mc.vram_end >> 12); |
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| 207 | } |
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| 2997 | Serge | 208 | WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12); |
| 1246 | serge | 209 | tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16; |
| 210 | tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF); |
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| 211 | WREG32(MC_VM_FB_LOCATION, tmp); |
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| 212 | WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8)); |
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| 213 | WREG32(HDP_NONSURFACE_INFO, (2 << 7)); |
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| 1963 | serge | 214 | WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF); |
| 1246 | serge | 215 | if (rdev->flags & RADEON_IS_AGP) { |
| 216 | WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16); |
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| 217 | WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16); |
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| 218 | WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22); |
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| 219 | } else { |
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| 220 | WREG32(MC_VM_AGP_BASE, 0); |
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| 221 | WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF); |
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| 222 | WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF); |
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| 223 | } |
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| 224 | if (r600_mc_wait_for_idle(rdev)) { |
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| 225 | dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); |
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| 226 | } |
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| 227 | rv515_mc_resume(rdev, &save); |
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| 228 | /* we need to own VRAM, so turn off the VGA renderer here |
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| 229 | * to stop it overwriting our objects */ |
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| 230 | rv515_vga_render_disable(rdev); |
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| 231 | } |
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| 232 | |||
| 233 | |||
| 234 | /* |
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| 235 | * CP. |
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| 236 | */ |
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| 237 | void r700_cp_stop(struct radeon_device *rdev) |
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| 238 | { |
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| 1963 | serge | 239 | // radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); |
| 1246 | serge | 240 | WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT)); |
| 1963 | serge | 241 | WREG32(SCRATCH_UMSK, 0); |
| 1246 | serge | 242 | } |
| 243 | |||
| 244 | static int rv770_cp_load_microcode(struct radeon_device *rdev) |
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| 245 | { |
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| 246 | const __be32 *fw_data; |
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| 247 | int i; |
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| 248 | |||
| 249 | if (!rdev->me_fw || !rdev->pfp_fw) |
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| 250 | return -EINVAL; |
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| 251 | |||
| 252 | r700_cp_stop(rdev); |
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| 1963 | serge | 253 | WREG32(CP_RB_CNTL, |
| 254 | #ifdef __BIG_ENDIAN |
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| 255 | BUF_SWAP_32BIT | |
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| 256 | #endif |
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| 257 | RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3)); |
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| 1246 | serge | 258 | |
| 259 | /* Reset cp */ |
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| 260 | WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP); |
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| 261 | RREG32(GRBM_SOFT_RESET); |
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| 262 | mdelay(15); |
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| 263 | WREG32(GRBM_SOFT_RESET, 0); |
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| 264 | |||
| 265 | fw_data = (const __be32 *)rdev->pfp_fw->data; |
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| 266 | WREG32(CP_PFP_UCODE_ADDR, 0); |
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| 267 | for (i = 0; i < R700_PFP_UCODE_SIZE; i++) |
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| 268 | WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++)); |
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| 269 | WREG32(CP_PFP_UCODE_ADDR, 0); |
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| 270 | |||
| 271 | fw_data = (const __be32 *)rdev->me_fw->data; |
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| 272 | WREG32(CP_ME_RAM_WADDR, 0); |
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| 273 | for (i = 0; i < R700_PM4_UCODE_SIZE; i++) |
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| 274 | WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++)); |
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| 275 | |||
| 276 | WREG32(CP_PFP_UCODE_ADDR, 0); |
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| 277 | WREG32(CP_ME_RAM_WADDR, 0); |
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| 278 | WREG32(CP_ME_RAM_RADDR, 0); |
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| 279 | return 0; |
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| 280 | } |
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| 281 | |||
| 282 | |||
| 283 | /* |
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| 284 | * Core functions |
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| 285 | */ |
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| 286 | static void rv770_gpu_init(struct radeon_device *rdev) |
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| 287 | { |
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| 288 | int i, j, num_qd_pipes; |
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| 1430 | serge | 289 | u32 ta_aux_cntl; |
| 1246 | serge | 290 | u32 sx_debug_1; |
| 291 | u32 smx_dc_ctl0; |
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| 1430 | serge | 292 | u32 db_debug3; |
| 1246 | serge | 293 | u32 num_gs_verts_per_thread; |
| 294 | u32 vgt_gs_per_es; |
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| 295 | u32 gs_prim_buffer_depth = 0; |
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| 296 | u32 sq_ms_fifo_sizes; |
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| 297 | u32 sq_config; |
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| 298 | u32 sq_thread_resource_mgmt; |
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| 299 | u32 hdp_host_path_cntl; |
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| 300 | u32 sq_dyn_gpr_size_simd_ab_0; |
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| 301 | u32 gb_tiling_config = 0; |
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| 302 | u32 cc_rb_backend_disable = 0; |
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| 303 | u32 cc_gc_shader_pipe_config = 0; |
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| 304 | u32 mc_arb_ramcfg; |
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| 2997 | Serge | 305 | u32 db_debug4, tmp; |
| 306 | u32 inactive_pipes, shader_pipe_config; |
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| 307 | u32 disabled_rb_mask; |
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| 308 | unsigned active_number; |
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| 1246 | serge | 309 | |
| 310 | /* setup chip specs */ |
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| 2997 | Serge | 311 | rdev->config.rv770.tiling_group_size = 256; |
| 1246 | serge | 312 | switch (rdev->family) { |
| 313 | case CHIP_RV770: |
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| 314 | rdev->config.rv770.max_pipes = 4; |
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| 315 | rdev->config.rv770.max_tile_pipes = 8; |
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| 316 | rdev->config.rv770.max_simds = 10; |
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| 317 | rdev->config.rv770.max_backends = 4; |
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| 318 | rdev->config.rv770.max_gprs = 256; |
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| 319 | rdev->config.rv770.max_threads = 248; |
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| 320 | rdev->config.rv770.max_stack_entries = 512; |
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| 321 | rdev->config.rv770.max_hw_contexts = 8; |
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| 322 | rdev->config.rv770.max_gs_threads = 16 * 2; |
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| 323 | rdev->config.rv770.sx_max_export_size = 128; |
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| 324 | rdev->config.rv770.sx_max_export_pos_size = 16; |
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| 325 | rdev->config.rv770.sx_max_export_smx_size = 112; |
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| 326 | rdev->config.rv770.sq_num_cf_insts = 2; |
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| 327 | |||
| 328 | rdev->config.rv770.sx_num_of_sets = 7; |
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| 329 | rdev->config.rv770.sc_prim_fifo_size = 0xF9; |
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| 330 | rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30; |
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| 331 | rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130; |
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| 332 | break; |
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| 333 | case CHIP_RV730: |
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| 334 | rdev->config.rv770.max_pipes = 2; |
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| 335 | rdev->config.rv770.max_tile_pipes = 4; |
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| 336 | rdev->config.rv770.max_simds = 8; |
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| 337 | rdev->config.rv770.max_backends = 2; |
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| 338 | rdev->config.rv770.max_gprs = 128; |
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| 339 | rdev->config.rv770.max_threads = 248; |
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| 340 | rdev->config.rv770.max_stack_entries = 256; |
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| 341 | rdev->config.rv770.max_hw_contexts = 8; |
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| 342 | rdev->config.rv770.max_gs_threads = 16 * 2; |
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| 343 | rdev->config.rv770.sx_max_export_size = 256; |
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| 344 | rdev->config.rv770.sx_max_export_pos_size = 32; |
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| 345 | rdev->config.rv770.sx_max_export_smx_size = 224; |
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| 346 | rdev->config.rv770.sq_num_cf_insts = 2; |
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| 347 | |||
| 348 | rdev->config.rv770.sx_num_of_sets = 7; |
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| 349 | rdev->config.rv770.sc_prim_fifo_size = 0xf9; |
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| 350 | rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30; |
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| 351 | rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130; |
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| 352 | if (rdev->config.rv770.sx_max_export_pos_size > 16) { |
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| 353 | rdev->config.rv770.sx_max_export_pos_size -= 16; |
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| 354 | rdev->config.rv770.sx_max_export_smx_size += 16; |
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| 355 | } |
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| 356 | break; |
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| 357 | case CHIP_RV710: |
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| 358 | rdev->config.rv770.max_pipes = 2; |
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| 359 | rdev->config.rv770.max_tile_pipes = 2; |
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| 360 | rdev->config.rv770.max_simds = 2; |
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| 361 | rdev->config.rv770.max_backends = 1; |
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| 362 | rdev->config.rv770.max_gprs = 256; |
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| 363 | rdev->config.rv770.max_threads = 192; |
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| 364 | rdev->config.rv770.max_stack_entries = 256; |
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| 365 | rdev->config.rv770.max_hw_contexts = 4; |
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| 366 | rdev->config.rv770.max_gs_threads = 8 * 2; |
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| 367 | rdev->config.rv770.sx_max_export_size = 128; |
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| 368 | rdev->config.rv770.sx_max_export_pos_size = 16; |
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| 369 | rdev->config.rv770.sx_max_export_smx_size = 112; |
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| 370 | rdev->config.rv770.sq_num_cf_insts = 1; |
||
| 371 | |||
| 372 | rdev->config.rv770.sx_num_of_sets = 7; |
||
| 373 | rdev->config.rv770.sc_prim_fifo_size = 0x40; |
||
| 374 | rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30; |
||
| 375 | rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130; |
||
| 376 | break; |
||
| 377 | case CHIP_RV740: |
||
| 378 | rdev->config.rv770.max_pipes = 4; |
||
| 379 | rdev->config.rv770.max_tile_pipes = 4; |
||
| 380 | rdev->config.rv770.max_simds = 8; |
||
| 381 | rdev->config.rv770.max_backends = 4; |
||
| 382 | rdev->config.rv770.max_gprs = 256; |
||
| 383 | rdev->config.rv770.max_threads = 248; |
||
| 384 | rdev->config.rv770.max_stack_entries = 512; |
||
| 385 | rdev->config.rv770.max_hw_contexts = 8; |
||
| 386 | rdev->config.rv770.max_gs_threads = 16 * 2; |
||
| 387 | rdev->config.rv770.sx_max_export_size = 256; |
||
| 388 | rdev->config.rv770.sx_max_export_pos_size = 32; |
||
| 389 | rdev->config.rv770.sx_max_export_smx_size = 224; |
||
| 390 | rdev->config.rv770.sq_num_cf_insts = 2; |
||
| 391 | |||
| 392 | rdev->config.rv770.sx_num_of_sets = 7; |
||
| 393 | rdev->config.rv770.sc_prim_fifo_size = 0x100; |
||
| 394 | rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30; |
||
| 395 | rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130; |
||
| 396 | |||
| 397 | if (rdev->config.rv770.sx_max_export_pos_size > 16) { |
||
| 398 | rdev->config.rv770.sx_max_export_pos_size -= 16; |
||
| 399 | rdev->config.rv770.sx_max_export_smx_size += 16; |
||
| 400 | } |
||
| 401 | break; |
||
| 402 | default: |
||
| 403 | break; |
||
| 404 | } |
||
| 405 | |||
| 406 | /* Initialize HDP */ |
||
| 407 | j = 0; |
||
| 408 | for (i = 0; i < 32; i++) { |
||
| 409 | WREG32((0x2c14 + j), 0x00000000); |
||
| 410 | WREG32((0x2c18 + j), 0x00000000); |
||
| 411 | WREG32((0x2c1c + j), 0x00000000); |
||
| 412 | WREG32((0x2c20 + j), 0x00000000); |
||
| 413 | WREG32((0x2c24 + j), 0x00000000); |
||
| 414 | j += 0x18; |
||
| 415 | } |
||
| 416 | |||
| 417 | WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); |
||
| 418 | |||
| 419 | /* setup tiling, simd, pipe config */ |
||
| 420 | mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG); |
||
| 421 | |||
| 2997 | Serge | 422 | shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG); |
| 423 | inactive_pipes = (shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> INACTIVE_QD_PIPES_SHIFT; |
||
| 424 | for (i = 0, tmp = 1, active_number = 0; i < R7XX_MAX_PIPES; i++) { |
||
| 425 | if (!(inactive_pipes & tmp)) { |
||
| 426 | active_number++; |
||
| 427 | } |
||
| 428 | tmp <<= 1; |
||
| 429 | } |
||
| 430 | if (active_number == 1) { |
||
| 431 | WREG32(SPI_CONFIG_CNTL, DISABLE_INTERP_1); |
||
| 432 | } else { |
||
| 433 | WREG32(SPI_CONFIG_CNTL, 0); |
||
| 434 | } |
||
| 435 | |||
| 436 | cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000; |
||
| 437 | tmp = R7XX_MAX_BACKENDS - r600_count_pipe_bits(cc_rb_backend_disable >> 16); |
||
| 438 | if (tmp < rdev->config.rv770.max_backends) { |
||
| 439 | rdev->config.rv770.max_backends = tmp; |
||
| 440 | } |
||
| 441 | |||
| 442 | cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00; |
||
| 443 | tmp = R7XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config >> 8) & R7XX_MAX_PIPES_MASK); |
||
| 444 | if (tmp < rdev->config.rv770.max_pipes) { |
||
| 445 | rdev->config.rv770.max_pipes = tmp; |
||
| 446 | } |
||
| 447 | tmp = R7XX_MAX_SIMDS - r600_count_pipe_bits((cc_gc_shader_pipe_config >> 16) & R7XX_MAX_SIMDS_MASK); |
||
| 448 | if (tmp < rdev->config.rv770.max_simds) { |
||
| 449 | rdev->config.rv770.max_simds = tmp; |
||
| 450 | } |
||
| 451 | |||
| 1246 | serge | 452 | switch (rdev->config.rv770.max_tile_pipes) { |
| 453 | case 1: |
||
| 1430 | serge | 454 | default: |
| 2997 | Serge | 455 | gb_tiling_config = PIPE_TILING(0); |
| 1246 | serge | 456 | break; |
| 457 | case 2: |
||
| 2997 | Serge | 458 | gb_tiling_config = PIPE_TILING(1); |
| 1246 | serge | 459 | break; |
| 460 | case 4: |
||
| 2997 | Serge | 461 | gb_tiling_config = PIPE_TILING(2); |
| 1246 | serge | 462 | break; |
| 463 | case 8: |
||
| 2997 | Serge | 464 | gb_tiling_config = PIPE_TILING(3); |
| 1246 | serge | 465 | break; |
| 466 | } |
||
| 1430 | serge | 467 | rdev->config.rv770.tiling_npipes = rdev->config.rv770.max_tile_pipes; |
| 1246 | serge | 468 | |
| 2997 | Serge | 469 | disabled_rb_mask = (RREG32(CC_RB_BACKEND_DISABLE) >> 16) & R7XX_MAX_BACKENDS_MASK; |
| 470 | tmp = (gb_tiling_config & PIPE_TILING__MASK) >> PIPE_TILING__SHIFT; |
||
| 471 | tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.rv770.max_backends, |
||
| 472 | R7XX_MAX_BACKENDS, disabled_rb_mask); |
||
| 473 | gb_tiling_config |= tmp << 16; |
||
| 474 | rdev->config.rv770.backend_map = tmp; |
||
| 475 | |||
| 1246 | serge | 476 | if (rdev->family == CHIP_RV770) |
| 477 | gb_tiling_config |= BANK_TILING(1); |
||
| 2997 | Serge | 478 | else { |
| 479 | if ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) |
||
| 480 | gb_tiling_config |= BANK_TILING(1); |
||
| 1246 | serge | 481 | else |
| 2997 | Serge | 482 | gb_tiling_config |= BANK_TILING(0); |
| 483 | } |
||
| 1430 | serge | 484 | rdev->config.rv770.tiling_nbanks = 4 << ((gb_tiling_config >> 4) & 0x3); |
| 1963 | serge | 485 | gb_tiling_config |= GROUP_SIZE((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT); |
| 1268 | serge | 486 | if (((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT) > 3) { |
| 1246 | serge | 487 | gb_tiling_config |= ROW_TILING(3); |
| 488 | gb_tiling_config |= SAMPLE_SPLIT(3); |
||
| 489 | } else { |
||
| 490 | gb_tiling_config |= |
||
| 491 | ROW_TILING(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT)); |
||
| 492 | gb_tiling_config |= |
||
| 493 | SAMPLE_SPLIT(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT)); |
||
| 494 | } |
||
| 495 | |||
| 496 | gb_tiling_config |= BANK_SWAPS(1); |
||
| 1963 | serge | 497 | rdev->config.rv770.tile_config = gb_tiling_config; |
| 1246 | serge | 498 | |
| 499 | WREG32(GB_TILING_CONFIG, gb_tiling_config); |
||
| 500 | WREG32(DCP_TILING_CONFIG, (gb_tiling_config & 0xffff)); |
||
| 501 | WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff)); |
||
| 502 | |||
| 503 | WREG32(CGTS_SYS_TCC_DISABLE, 0); |
||
| 504 | WREG32(CGTS_TCC_DISABLE, 0); |
||
| 1963 | serge | 505 | WREG32(CGTS_USER_SYS_TCC_DISABLE, 0); |
| 506 | WREG32(CGTS_USER_TCC_DISABLE, 0); |
||
| 1246 | serge | 507 | |
| 2997 | Serge | 508 | |
| 509 | num_qd_pipes = R7XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8); |
||
| 1246 | serge | 510 | WREG32(VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & DEALLOC_DIST_MASK); |
| 511 | WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & VTX_REUSE_DEPTH_MASK); |
||
| 512 | |||
| 513 | /* set HW defaults for 3D engine */ |
||
| 514 | WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | |
||
| 515 | ROQ_IB2_START(0x2b))); |
||
| 516 | |||
| 517 | WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30)); |
||
| 518 | |||
| 1430 | serge | 519 | ta_aux_cntl = RREG32(TA_CNTL_AUX); |
| 520 | WREG32(TA_CNTL_AUX, ta_aux_cntl | DISABLE_CUBE_ANISO); |
||
| 1246 | serge | 521 | |
| 522 | sx_debug_1 = RREG32(SX_DEBUG_1); |
||
| 523 | sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS; |
||
| 524 | WREG32(SX_DEBUG_1, sx_debug_1); |
||
| 525 | |||
| 526 | smx_dc_ctl0 = RREG32(SMX_DC_CTL0); |
||
| 527 | smx_dc_ctl0 &= ~CACHE_DEPTH(0x1ff); |
||
| 528 | smx_dc_ctl0 |= CACHE_DEPTH((rdev->config.rv770.sx_num_of_sets * 64) - 1); |
||
| 529 | WREG32(SMX_DC_CTL0, smx_dc_ctl0); |
||
| 530 | |||
| 1430 | serge | 531 | if (rdev->family != CHIP_RV740) |
| 1246 | serge | 532 | WREG32(SMX_EVENT_CTL, (ES_FLUSH_CTL(4) | |
| 533 | GS_FLUSH_CTL(4) | |
||
| 534 | ACK_FLUSH_CTL(3) | |
||
| 535 | SYNC_FLUSH_CTL)); |
||
| 536 | |||
| 2997 | Serge | 537 | if (rdev->family != CHIP_RV770) |
| 538 | WREG32(SMX_SAR_CTL0, 0x00003f3f); |
||
| 539 | |||
| 1430 | serge | 540 | db_debug3 = RREG32(DB_DEBUG3); |
| 541 | db_debug3 &= ~DB_CLK_OFF_DELAY(0x1f); |
||
| 542 | switch (rdev->family) { |
||
| 543 | case CHIP_RV770: |
||
| 544 | case CHIP_RV740: |
||
| 545 | db_debug3 |= DB_CLK_OFF_DELAY(0x1f); |
||
| 546 | break; |
||
| 547 | case CHIP_RV710: |
||
| 548 | case CHIP_RV730: |
||
| 549 | default: |
||
| 550 | db_debug3 |= DB_CLK_OFF_DELAY(2); |
||
| 551 | break; |
||
| 552 | } |
||
| 553 | WREG32(DB_DEBUG3, db_debug3); |
||
| 554 | |||
| 555 | if (rdev->family != CHIP_RV770) { |
||
| 1246 | serge | 556 | db_debug4 = RREG32(DB_DEBUG4); |
| 557 | db_debug4 |= DISABLE_TILE_COVERED_FOR_PS_ITER; |
||
| 558 | WREG32(DB_DEBUG4, db_debug4); |
||
| 559 | } |
||
| 560 | |||
| 561 | WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.rv770.sx_max_export_size / 4) - 1) | |
||
| 562 | POSITION_BUFFER_SIZE((rdev->config.rv770.sx_max_export_pos_size / 4) - 1) | |
||
| 563 | SMX_BUFFER_SIZE((rdev->config.rv770.sx_max_export_smx_size / 4) - 1))); |
||
| 564 | |||
| 565 | WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.rv770.sc_prim_fifo_size) | |
||
| 566 | SC_HIZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_hiz_tile_fifo_size) | |
||
| 567 | SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_earlyz_tile_fifo_fize))); |
||
| 568 | |||
| 569 | WREG32(PA_SC_MULTI_CHIP_CNTL, 0); |
||
| 570 | |||
| 571 | WREG32(VGT_NUM_INSTANCES, 1); |
||
| 572 | |||
| 573 | WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4)); |
||
| 574 | |||
| 575 | WREG32(CP_PERFMON_CNTL, 0); |
||
| 576 | |||
| 577 | sq_ms_fifo_sizes = (CACHE_FIFO_SIZE(16 * rdev->config.rv770.sq_num_cf_insts) | |
||
| 578 | DONE_FIFO_HIWATER(0xe0) | |
||
| 579 | ALU_UPDATE_FIFO_HIWATER(0x8)); |
||
| 580 | switch (rdev->family) { |
||
| 581 | case CHIP_RV770: |
||
| 1430 | serge | 582 | case CHIP_RV730: |
| 583 | case CHIP_RV710: |
||
| 1246 | serge | 584 | sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x1); |
| 585 | break; |
||
| 586 | case CHIP_RV740: |
||
| 587 | default: |
||
| 588 | sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x4); |
||
| 589 | break; |
||
| 590 | } |
||
| 591 | WREG32(SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes); |
||
| 592 | |||
| 593 | /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT |
||
| 594 | * should be adjusted as needed by the 2D/3D drivers. This just sets default values |
||
| 595 | */ |
||
| 596 | sq_config = RREG32(SQ_CONFIG); |
||
| 597 | sq_config &= ~(PS_PRIO(3) | |
||
| 598 | VS_PRIO(3) | |
||
| 599 | GS_PRIO(3) | |
||
| 600 | ES_PRIO(3)); |
||
| 601 | sq_config |= (DX9_CONSTS | |
||
| 602 | VC_ENABLE | |
||
| 603 | EXPORT_SRC_C | |
||
| 604 | PS_PRIO(0) | |
||
| 605 | VS_PRIO(1) | |
||
| 606 | GS_PRIO(2) | |
||
| 607 | ES_PRIO(3)); |
||
| 608 | if (rdev->family == CHIP_RV710) |
||
| 609 | /* no vertex cache */ |
||
| 610 | sq_config &= ~VC_ENABLE; |
||
| 611 | |||
| 612 | WREG32(SQ_CONFIG, sq_config); |
||
| 613 | |||
| 614 | WREG32(SQ_GPR_RESOURCE_MGMT_1, (NUM_PS_GPRS((rdev->config.rv770.max_gprs * 24)/64) | |
||
| 615 | NUM_VS_GPRS((rdev->config.rv770.max_gprs * 24)/64) | |
||
| 616 | NUM_CLAUSE_TEMP_GPRS(((rdev->config.rv770.max_gprs * 24)/64)/2))); |
||
| 617 | |||
| 618 | WREG32(SQ_GPR_RESOURCE_MGMT_2, (NUM_GS_GPRS((rdev->config.rv770.max_gprs * 7)/64) | |
||
| 619 | NUM_ES_GPRS((rdev->config.rv770.max_gprs * 7)/64))); |
||
| 620 | |||
| 621 | sq_thread_resource_mgmt = (NUM_PS_THREADS((rdev->config.rv770.max_threads * 4)/8) | |
||
| 622 | NUM_VS_THREADS((rdev->config.rv770.max_threads * 2)/8) | |
||
| 623 | NUM_ES_THREADS((rdev->config.rv770.max_threads * 1)/8)); |
||
| 624 | if (((rdev->config.rv770.max_threads * 1) / 8) > rdev->config.rv770.max_gs_threads) |
||
| 625 | sq_thread_resource_mgmt |= NUM_GS_THREADS(rdev->config.rv770.max_gs_threads); |
||
| 626 | else |
||
| 627 | sq_thread_resource_mgmt |= NUM_GS_THREADS((rdev->config.rv770.max_gs_threads * 1)/8); |
||
| 628 | WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt); |
||
| 629 | |||
| 630 | WREG32(SQ_STACK_RESOURCE_MGMT_1, (NUM_PS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) | |
||
| 631 | NUM_VS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4))); |
||
| 632 | |||
| 633 | WREG32(SQ_STACK_RESOURCE_MGMT_2, (NUM_GS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) | |
||
| 634 | NUM_ES_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4))); |
||
| 635 | |||
| 636 | sq_dyn_gpr_size_simd_ab_0 = (SIMDA_RING0((rdev->config.rv770.max_gprs * 38)/64) | |
||
| 637 | SIMDA_RING1((rdev->config.rv770.max_gprs * 38)/64) | |
||
| 638 | SIMDB_RING0((rdev->config.rv770.max_gprs * 38)/64) | |
||
| 639 | SIMDB_RING1((rdev->config.rv770.max_gprs * 38)/64)); |
||
| 640 | |||
| 641 | WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_0, sq_dyn_gpr_size_simd_ab_0); |
||
| 642 | WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_1, sq_dyn_gpr_size_simd_ab_0); |
||
| 643 | WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_2, sq_dyn_gpr_size_simd_ab_0); |
||
| 644 | WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_3, sq_dyn_gpr_size_simd_ab_0); |
||
| 645 | WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_4, sq_dyn_gpr_size_simd_ab_0); |
||
| 646 | WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_5, sq_dyn_gpr_size_simd_ab_0); |
||
| 647 | WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_6, sq_dyn_gpr_size_simd_ab_0); |
||
| 648 | WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_7, sq_dyn_gpr_size_simd_ab_0); |
||
| 649 | |||
| 650 | WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) | |
||
| 651 | FORCE_EOV_MAX_REZ_CNT(255))); |
||
| 652 | |||
| 653 | if (rdev->family == CHIP_RV710) |
||
| 654 | WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(TC_ONLY) | |
||
| 655 | AUTO_INVLD_EN(ES_AND_GS_AUTO))); |
||
| 656 | else |
||
| 657 | WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(VC_AND_TC) | |
||
| 658 | AUTO_INVLD_EN(ES_AND_GS_AUTO))); |
||
| 659 | |||
| 660 | switch (rdev->family) { |
||
| 661 | case CHIP_RV770: |
||
| 662 | case CHIP_RV730: |
||
| 663 | case CHIP_RV740: |
||
| 664 | gs_prim_buffer_depth = 384; |
||
| 665 | break; |
||
| 666 | case CHIP_RV710: |
||
| 667 | gs_prim_buffer_depth = 128; |
||
| 668 | break; |
||
| 669 | default: |
||
| 670 | break; |
||
| 671 | } |
||
| 672 | |||
| 673 | num_gs_verts_per_thread = rdev->config.rv770.max_pipes * 16; |
||
| 674 | vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread; |
||
| 675 | /* Max value for this is 256 */ |
||
| 676 | if (vgt_gs_per_es > 256) |
||
| 677 | vgt_gs_per_es = 256; |
||
| 678 | |||
| 679 | WREG32(VGT_ES_PER_GS, 128); |
||
| 680 | WREG32(VGT_GS_PER_ES, vgt_gs_per_es); |
||
| 681 | WREG32(VGT_GS_PER_VS, 2); |
||
| 682 | |||
| 683 | /* more default values. 2D/3D driver should adjust as needed */ |
||
| 684 | WREG32(VGT_GS_VERTEX_REUSE, 16); |
||
| 685 | WREG32(PA_SC_LINE_STIPPLE_STATE, 0); |
||
| 686 | WREG32(VGT_STRMOUT_EN, 0); |
||
| 687 | WREG32(SX_MISC, 0); |
||
| 688 | WREG32(PA_SC_MODE_CNTL, 0); |
||
| 689 | WREG32(PA_SC_EDGERULE, 0xaaaaaaaa); |
||
| 690 | WREG32(PA_SC_AA_CONFIG, 0); |
||
| 691 | WREG32(PA_SC_CLIPRECT_RULE, 0xffff); |
||
| 692 | WREG32(PA_SC_LINE_STIPPLE, 0); |
||
| 693 | WREG32(SPI_INPUT_Z, 0); |
||
| 694 | WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2)); |
||
| 695 | WREG32(CB_COLOR7_FRAG, 0); |
||
| 696 | |||
| 697 | /* clear render buffer base addresses */ |
||
| 698 | WREG32(CB_COLOR0_BASE, 0); |
||
| 699 | WREG32(CB_COLOR1_BASE, 0); |
||
| 700 | WREG32(CB_COLOR2_BASE, 0); |
||
| 701 | WREG32(CB_COLOR3_BASE, 0); |
||
| 702 | WREG32(CB_COLOR4_BASE, 0); |
||
| 703 | WREG32(CB_COLOR5_BASE, 0); |
||
| 704 | WREG32(CB_COLOR6_BASE, 0); |
||
| 705 | WREG32(CB_COLOR7_BASE, 0); |
||
| 706 | |||
| 707 | WREG32(TCP_CNTL, 0); |
||
| 708 | |||
| 709 | hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL); |
||
| 710 | WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl); |
||
| 711 | |||
| 712 | WREG32(PA_SC_MULTI_CHIP_CNTL, 0); |
||
| 713 | |||
| 714 | WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA | |
||
| 715 | NUM_CLIP_SEQ(3))); |
||
| 2997 | Serge | 716 | WREG32(VC_ENHANCE, 0); |
| 1246 | serge | 717 | } |
| 718 | |||
| 1963 | serge | 719 | void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc) |
| 720 | { |
||
| 721 | u64 size_bf, size_af; |
||
| 722 | |||
| 723 | if (mc->mc_vram_size > 0xE0000000) { |
||
| 724 | /* leave room for at least 512M GTT */ |
||
| 725 | dev_warn(rdev->dev, "limiting VRAM\n"); |
||
| 726 | mc->real_vram_size = 0xE0000000; |
||
| 727 | mc->mc_vram_size = 0xE0000000; |
||
| 728 | } |
||
| 729 | if (rdev->flags & RADEON_IS_AGP) { |
||
| 730 | size_bf = mc->gtt_start; |
||
| 2997 | Serge | 731 | size_af = 0xFFFFFFFF - mc->gtt_end; |
| 1963 | serge | 732 | if (size_bf > size_af) { |
| 733 | if (mc->mc_vram_size > size_bf) { |
||
| 734 | dev_warn(rdev->dev, "limiting VRAM\n"); |
||
| 735 | mc->real_vram_size = size_bf; |
||
| 736 | mc->mc_vram_size = size_bf; |
||
| 737 | } |
||
| 738 | mc->vram_start = mc->gtt_start - mc->mc_vram_size; |
||
| 739 | } else { |
||
| 740 | if (mc->mc_vram_size > size_af) { |
||
| 741 | dev_warn(rdev->dev, "limiting VRAM\n"); |
||
| 742 | mc->real_vram_size = size_af; |
||
| 743 | mc->mc_vram_size = size_af; |
||
| 744 | } |
||
| 2997 | Serge | 745 | mc->vram_start = mc->gtt_end + 1; |
| 1963 | serge | 746 | } |
| 747 | mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; |
||
| 748 | dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n", |
||
| 749 | mc->mc_vram_size >> 20, mc->vram_start, |
||
| 750 | mc->vram_end, mc->real_vram_size >> 20); |
||
| 751 | } else { |
||
| 752 | radeon_vram_location(rdev, &rdev->mc, 0); |
||
| 753 | rdev->mc.gtt_base_align = 0; |
||
| 754 | radeon_gtt_location(rdev, mc); |
||
| 755 | } |
||
| 756 | } |
||
| 757 | |||
| 2997 | Serge | 758 | static int rv770_mc_init(struct radeon_device *rdev) |
| 1246 | serge | 759 | { |
| 760 | u32 tmp; |
||
| 1268 | serge | 761 | int chansize, numchan; |
| 1246 | serge | 762 | |
| 763 | /* Get VRAM informations */ |
||
| 764 | rdev->mc.vram_is_ddr = true; |
||
| 1268 | serge | 765 | tmp = RREG32(MC_ARB_RAMCFG); |
| 766 | if (tmp & CHANSIZE_OVERRIDE) { |
||
| 767 | chansize = 16; |
||
| 768 | } else if (tmp & CHANSIZE_MASK) { |
||
| 769 | chansize = 64; |
||
| 770 | } else { |
||
| 771 | chansize = 32; |
||
| 772 | } |
||
| 773 | tmp = RREG32(MC_SHARED_CHMAP); |
||
| 774 | switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) { |
||
| 775 | case 0: |
||
| 776 | default: |
||
| 777 | numchan = 1; |
||
| 778 | break; |
||
| 779 | case 1: |
||
| 780 | numchan = 2; |
||
| 781 | break; |
||
| 782 | case 2: |
||
| 783 | numchan = 4; |
||
| 784 | break; |
||
| 785 | case 3: |
||
| 786 | numchan = 8; |
||
| 787 | break; |
||
| 788 | } |
||
| 789 | rdev->mc.vram_width = numchan * chansize; |
||
| 1246 | serge | 790 | /* Could aper size report 0 ? */ |
| 1963 | serge | 791 | rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); |
| 792 | rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); |
||
| 1246 | serge | 793 | /* Setup GPU memory space */ |
| 794 | rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE); |
||
| 795 | rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); |
||
| 1430 | serge | 796 | rdev->mc.visible_vram_size = rdev->mc.aper_size; |
| 1963 | serge | 797 | r700_vram_gtt_location(rdev, &rdev->mc); |
| 798 | radeon_update_bandwidth_info(rdev); |
||
| 799 | |||
| 1246 | serge | 800 | return 0; |
| 801 | } |
||
| 1430 | serge | 802 | |
| 1246 | serge | 803 | static int rv770_startup(struct radeon_device *rdev) |
| 804 | { |
||
| 2997 | Serge | 805 | struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; |
| 1246 | serge | 806 | int r; |
| 807 | |||
| 1963 | serge | 808 | /* enable pcie gen2 link */ |
| 809 | rv770_pcie_gen2_enable(rdev); |
||
| 810 | |||
| 1413 | serge | 811 | if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) { |
| 812 | r = r600_init_microcode(rdev); |
||
| 813 | if (r) { |
||
| 814 | DRM_ERROR("Failed to load firmware!\n"); |
||
| 815 | return r; |
||
| 816 | } |
||
| 817 | } |
||
| 818 | |||
| 2997 | Serge | 819 | r = r600_vram_scratch_init(rdev); |
| 820 | if (r) |
||
| 821 | return r; |
||
| 822 | |||
| 1246 | serge | 823 | rv770_mc_program(rdev); |
| 824 | if (rdev->flags & RADEON_IS_AGP) { |
||
| 825 | rv770_agp_enable(rdev); |
||
| 826 | } else { |
||
| 827 | r = rv770_pcie_gart_enable(rdev); |
||
| 828 | if (r) |
||
| 829 | return r; |
||
| 830 | } |
||
| 2997 | Serge | 831 | |
| 1246 | serge | 832 | rv770_gpu_init(rdev); |
| 2005 | serge | 833 | r = r600_blit_init(rdev); |
| 834 | if (r) { |
||
| 2997 | Serge | 835 | r600_blit_fini(rdev); |
| 836 | rdev->asic->copy.copy = NULL; |
||
| 2005 | serge | 837 | dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r); |
| 838 | } |
||
| 839 | |||
| 2997 | Serge | 840 | // r = r600_video_init(rdev); |
| 841 | // if (r) { |
||
| 2175 | serge | 842 | // r600_video_fini(rdev); |
| 843 | // rdev->asic->copy = NULL; |
||
| 2997 | Serge | 844 | // dev_warn(rdev->dev, "failed video blitter (%d) falling back to memcpy\n", r); |
| 845 | // } |
||
| 2175 | serge | 846 | |
| 2004 | serge | 847 | /* allocate wb buffer */ |
| 848 | r = radeon_wb_init(rdev); |
||
| 849 | if (r) |
||
| 850 | return r; |
||
| 851 | |||
| 852 | /* Enable IRQ */ |
||
| 853 | r = r600_irq_init(rdev); |
||
| 854 | if (r) { |
||
| 855 | DRM_ERROR("radeon: IH init failed (%d).\n", r); |
||
| 856 | // radeon_irq_kms_fini(rdev); |
||
| 857 | return r; |
||
| 858 | } |
||
| 859 | r600_irq_set(rdev); |
||
| 860 | |||
| 2997 | Serge | 861 | r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET, |
| 862 | R600_CP_RB_RPTR, R600_CP_RB_WPTR, |
||
| 863 | 0, 0xfffff, RADEON_CP_PACKET2); |
||
| 1413 | serge | 864 | if (r) |
| 865 | return r; |
||
| 866 | r = rv770_cp_load_microcode(rdev); |
||
| 867 | if (r) |
||
| 868 | return r; |
||
| 869 | r = r600_cp_resume(rdev); |
||
| 870 | if (r) |
||
| 871 | return r; |
||
| 1963 | serge | 872 | |
| 2997 | Serge | 873 | r = radeon_ib_pool_init(rdev); |
| 874 | if (r) { |
||
| 875 | dev_err(rdev->dev, "IB initialization failed (%d).\n", r); |
||
| 876 | return r; |
||
| 877 | } |
||
| 878 | |||
| 879 | |||
| 1246 | serge | 880 | return 0; |
| 881 | } |
||
| 882 | |||
| 883 | |||
| 1413 | serge | 884 | |
| 885 | |||
| 886 | |||
| 887 | |||
| 888 | |||
| 1246 | serge | 889 | /* Plan is to move initialization in that function and use |
| 890 | * helper function so that radeon_device_init pretty much |
||
| 891 | * do nothing more than calling asic specific function. This |
||
| 892 | * should also allow to remove a bunch of callback function |
||
| 893 | * like vram_info. |
||
| 894 | */ |
||
| 895 | int rv770_init(struct radeon_device *rdev) |
||
| 896 | { |
||
| 897 | int r; |
||
| 898 | |||
| 899 | /* Read BIOS */ |
||
| 900 | if (!radeon_get_bios(rdev)) { |
||
| 901 | if (ASIC_IS_AVIVO(rdev)) |
||
| 902 | return -EINVAL; |
||
| 903 | } |
||
| 904 | /* Must be an ATOMBIOS */ |
||
| 905 | if (!rdev->is_atom_bios) { |
||
| 906 | dev_err(rdev->dev, "Expecting atombios for R600 GPU\n"); |
||
| 907 | return -EINVAL; |
||
| 908 | } |
||
| 909 | r = radeon_atombios_init(rdev); |
||
| 910 | if (r) |
||
| 911 | return r; |
||
| 912 | /* Post card if necessary */ |
||
| 1963 | serge | 913 | if (!radeon_card_posted(rdev)) { |
| 1403 | serge | 914 | if (!rdev->bios) { |
| 915 | dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); |
||
| 916 | return -EINVAL; |
||
| 917 | } |
||
| 1246 | serge | 918 | DRM_INFO("GPU not posted. posting now...\n"); |
| 919 | atom_asic_init(rdev->mode_info.atom_context); |
||
| 920 | } |
||
| 921 | /* Initialize scratch registers */ |
||
| 922 | r600_scratch_init(rdev); |
||
| 923 | /* Initialize surface registers */ |
||
| 924 | radeon_surface_init(rdev); |
||
| 1268 | serge | 925 | /* Initialize clocks */ |
| 1246 | serge | 926 | radeon_get_clock_info(rdev->ddev); |
| 927 | /* Fence driver */ |
||
| 2004 | serge | 928 | r = radeon_fence_driver_init(rdev); |
| 929 | if (r) |
||
| 930 | return r; |
||
| 1430 | serge | 931 | /* initialize AGP */ |
| 1403 | serge | 932 | if (rdev->flags & RADEON_IS_AGP) { |
| 933 | r = radeon_agp_init(rdev); |
||
| 934 | if (r) |
||
| 935 | radeon_agp_disable(rdev); |
||
| 936 | } |
||
| 1246 | serge | 937 | r = rv770_mc_init(rdev); |
| 938 | if (r) |
||
| 939 | return r; |
||
| 940 | /* Memory manager */ |
||
| 1403 | serge | 941 | r = radeon_bo_init(rdev); |
| 1246 | serge | 942 | if (r) |
| 943 | return r; |
||
| 944 | |||
| 2004 | serge | 945 | r = radeon_irq_kms_init(rdev); |
| 946 | if (r) |
||
| 947 | return r; |
||
| 1246 | serge | 948 | |
| 2997 | Serge | 949 | rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL; |
| 950 | r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024); |
||
| 1413 | serge | 951 | |
| 2004 | serge | 952 | rdev->ih.ring_obj = NULL; |
| 953 | r600_ih_ring_init(rdev, 64 * 1024); |
||
| 1413 | serge | 954 | |
| 1246 | serge | 955 | r = r600_pcie_gart_init(rdev); |
| 956 | if (r) |
||
| 957 | return r; |
||
| 958 | |||
| 959 | rdev->accel_working = true; |
||
| 960 | r = rv770_startup(rdev); |
||
| 961 | if (r) { |
||
| 1413 | serge | 962 | dev_err(rdev->dev, "disabling GPU acceleration\n"); |
| 1246 | serge | 963 | rv770_pcie_gart_fini(rdev); |
| 964 | rdev->accel_working = false; |
||
| 965 | } |
||
| 1963 | serge | 966 | |
| 1246 | serge | 967 | return 0; |
| 968 | } |
||
| 969 | |||
| 1963 | serge | 970 | static void rv770_pcie_gen2_enable(struct radeon_device *rdev) |
| 971 | { |
||
| 972 | u32 link_width_cntl, lanes, speed_cntl, tmp; |
||
| 973 | u16 link_cntl2; |
||
| 2997 | Serge | 974 | u32 mask; |
| 975 | int ret; |
||
| 1963 | serge | 976 | |
| 977 | if (radeon_pcie_gen2 == 0) |
||
| 978 | return; |
||
| 979 | |||
| 980 | if (rdev->flags & RADEON_IS_IGP) |
||
| 981 | return; |
||
| 982 | |||
| 983 | if (!(rdev->flags & RADEON_IS_PCIE)) |
||
| 984 | return; |
||
| 985 | |||
| 986 | /* x2 cards have a special sequence */ |
||
| 987 | if (ASIC_IS_X2(rdev)) |
||
| 988 | return; |
||
| 989 | |||
| 2997 | Serge | 990 | ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask); |
| 991 | if (ret != 0) |
||
| 992 | return; |
||
| 993 | |||
| 994 | if (!(mask & DRM_PCIE_SPEED_50)) |
||
| 995 | return; |
||
| 996 | |||
| 997 | DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n"); |
||
| 998 | |||
| 1963 | serge | 999 | /* advertise upconfig capability */ |
| 1000 | link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL); |
||
| 1001 | link_width_cntl &= ~LC_UPCONFIGURE_DIS; |
||
| 1002 | WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); |
||
| 1003 | link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL); |
||
| 1004 | if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) { |
||
| 1005 | lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT; |
||
| 1006 | link_width_cntl &= ~(LC_LINK_WIDTH_MASK | |
||
| 1007 | LC_RECONFIG_ARC_MISSING_ESCAPE); |
||
| 1008 | link_width_cntl |= lanes | LC_RECONFIG_NOW | |
||
| 1009 | LC_RENEGOTIATE_EN | LC_UPCONFIGURE_SUPPORT; |
||
| 1010 | WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); |
||
| 1011 | } else { |
||
| 1012 | link_width_cntl |= LC_UPCONFIGURE_DIS; |
||
| 1013 | WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); |
||
| 1014 | } |
||
| 1015 | |||
| 1016 | speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); |
||
| 1017 | if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) && |
||
| 1018 | (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) { |
||
| 1019 | |||
| 1020 | tmp = RREG32(0x541c); |
||
| 1021 | WREG32(0x541c, tmp | 0x8); |
||
| 1022 | WREG32(MM_CFGREGS_CNTL, MM_WR_TO_CFG_EN); |
||
| 1023 | link_cntl2 = RREG16(0x4088); |
||
| 1024 | link_cntl2 &= ~TARGET_LINK_SPEED_MASK; |
||
| 1025 | link_cntl2 |= 0x2; |
||
| 1026 | WREG16(0x4088, link_cntl2); |
||
| 1027 | WREG32(MM_CFGREGS_CNTL, 0); |
||
| 1028 | |||
| 1029 | speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); |
||
| 1030 | speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN; |
||
| 1031 | WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); |
||
| 1032 | |||
| 1033 | speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); |
||
| 1034 | speed_cntl |= LC_CLR_FAILED_SPD_CHANGE_CNT; |
||
| 1035 | WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); |
||
| 1036 | |||
| 1037 | speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); |
||
| 1038 | speed_cntl &= ~LC_CLR_FAILED_SPD_CHANGE_CNT; |
||
| 1039 | WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); |
||
| 1040 | |||
| 1041 | speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); |
||
| 1042 | speed_cntl |= LC_GEN2_EN_STRAP; |
||
| 1043 | WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); |
||
| 1044 | |||
| 1045 | } else { |
||
| 1046 | link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL); |
||
| 1047 | /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */ |
||
| 1048 | if (1) |
||
| 1049 | link_width_cntl |= LC_UPCONFIGURE_DIS; |
||
| 1050 | else |
||
| 1051 | link_width_cntl &= ~LC_UPCONFIGURE_DIS; |
||
| 1052 | WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); |
||
| 1053 | } |
||
| 1054 | } |