Rev 1430 | Rev 2004 | Go to most recent revision | Details | Compare with Previous | Last modification | View Log | RSS feed
| Rev | Author | Line No. | Line |
|---|---|---|---|
| 1246 | serge | 1 | /* |
| 2 | * Copyright 2008 Advanced Micro Devices, Inc. |
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| 3 | * Copyright 2008 Red Hat Inc. |
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| 4 | * Copyright 2009 Jerome Glisse. |
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| 5 | * |
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| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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| 7 | * copy of this software and associated documentation files (the "Software"), |
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| 8 | * to deal in the Software without restriction, including without limitation |
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| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
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| 11 | * Software is furnished to do so, subject to the following conditions: |
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| 12 | * |
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| 13 | * The above copyright notice and this permission notice shall be included in |
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| 14 | * all copies or substantial portions of the Software. |
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| 15 | * |
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| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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| 19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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| 20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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| 21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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| 22 | * OTHER DEALINGS IN THE SOFTWARE. |
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| 23 | * |
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| 24 | * Authors: Dave Airlie |
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| 25 | * Alex Deucher |
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| 26 | * Jerome Glisse |
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| 27 | */ |
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| 1413 | serge | 28 | #include |
| 1246 | serge | 29 | //#include |
| 1963 | serge | 30 | #include |
| 1246 | serge | 31 | #include "drmP.h" |
| 32 | #include "radeon.h" |
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| 1963 | serge | 33 | #include "radeon_asic.h" |
| 1246 | serge | 34 | #include "radeon_drm.h" |
| 35 | #include "rv770d.h" |
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| 36 | #include "atom.h" |
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| 37 | #include "avivod.h" |
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| 38 | |||
| 39 | #define R700_PFP_UCODE_SIZE 848 |
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| 40 | #define R700_PM4_UCODE_SIZE 1360 |
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| 41 | |||
| 42 | static void rv770_gpu_init(struct radeon_device *rdev); |
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| 43 | void rv770_fini(struct radeon_device *rdev); |
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| 1963 | serge | 44 | static void rv770_pcie_gen2_enable(struct radeon_device *rdev); |
| 1246 | serge | 45 | |
| 46 | |||
| 47 | /* |
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| 48 | * GART |
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| 49 | */ |
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| 50 | int rv770_pcie_gart_enable(struct radeon_device *rdev) |
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| 51 | { |
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| 52 | u32 tmp; |
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| 53 | int r, i; |
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| 54 | |||
| 55 | if (rdev->gart.table.vram.robj == NULL) { |
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| 56 | dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); |
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| 57 | return -EINVAL; |
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| 58 | } |
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| 59 | r = radeon_gart_table_vram_pin(rdev); |
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| 60 | if (r) |
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| 61 | return r; |
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| 1430 | serge | 62 | radeon_gart_restore(rdev); |
| 1246 | serge | 63 | /* Setup L2 cache */ |
| 64 | WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | |
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| 65 | ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | |
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| 66 | EFFECTIVE_L2_QUEUE_SIZE(7)); |
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| 67 | WREG32(VM_L2_CNTL2, 0); |
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| 68 | WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); |
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| 69 | /* Setup TLB control */ |
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| 70 | tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | |
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| 71 | SYSTEM_ACCESS_MODE_NOT_IN_SYS | |
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| 72 | SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU | |
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| 73 | EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5); |
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| 74 | WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp); |
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| 75 | WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp); |
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| 76 | WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp); |
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| 77 | WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp); |
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| 78 | WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); |
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| 79 | WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp); |
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| 80 | WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp); |
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| 81 | WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); |
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| 82 | WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12); |
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| 83 | WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); |
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| 84 | WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | |
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| 85 | RANGE_PROTECTION_FAULT_ENABLE_DEFAULT); |
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| 86 | WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, |
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| 87 | (u32)(rdev->dummy_page.addr >> 12)); |
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| 88 | for (i = 1; i < 7; i++) |
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| 89 | WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); |
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| 90 | |||
| 91 | r600_pcie_gart_tlb_flush(rdev); |
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| 92 | rdev->gart.ready = true; |
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| 93 | return 0; |
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| 94 | } |
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| 95 | |||
| 96 | void rv770_pcie_gart_disable(struct radeon_device *rdev) |
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| 97 | { |
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| 98 | u32 tmp; |
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| 1403 | serge | 99 | int i, r; |
| 1246 | serge | 100 | |
| 101 | /* Disable all tables */ |
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| 102 | for (i = 0; i < 7; i++) |
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| 103 | WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); |
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| 104 | |||
| 105 | /* Setup L2 cache */ |
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| 106 | WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING | |
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| 107 | EFFECTIVE_L2_QUEUE_SIZE(7)); |
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| 108 | WREG32(VM_L2_CNTL2, 0); |
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| 109 | WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); |
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| 110 | /* Setup TLB control */ |
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| 111 | tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5); |
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| 112 | WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp); |
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| 113 | WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp); |
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| 114 | WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp); |
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| 115 | WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp); |
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| 116 | WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); |
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| 117 | WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp); |
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| 118 | WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp); |
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| 119 | if (rdev->gart.table.vram.robj) { |
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| 1404 | serge | 120 | r = radeon_bo_reserve(rdev->gart.table.vram.robj, false); |
| 121 | if (likely(r == 0)) { |
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| 122 | radeon_bo_kunmap(rdev->gart.table.vram.robj); |
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| 123 | radeon_bo_unpin(rdev->gart.table.vram.robj); |
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| 124 | radeon_bo_unreserve(rdev->gart.table.vram.robj); |
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| 125 | } |
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| 1246 | serge | 126 | } |
| 127 | } |
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| 128 | |||
| 129 | void rv770_pcie_gart_fini(struct radeon_device *rdev) |
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| 130 | { |
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| 1963 | serge | 131 | radeon_gart_fini(rdev); |
| 1246 | serge | 132 | rv770_pcie_gart_disable(rdev); |
| 1404 | serge | 133 | radeon_gart_table_vram_free(rdev); |
| 1246 | serge | 134 | } |
| 135 | |||
| 136 | |||
| 137 | void rv770_agp_enable(struct radeon_device *rdev) |
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| 138 | { |
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| 139 | u32 tmp; |
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| 140 | int i; |
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| 141 | |||
| 142 | /* Setup L2 cache */ |
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| 143 | WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | |
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| 144 | ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | |
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| 145 | EFFECTIVE_L2_QUEUE_SIZE(7)); |
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| 146 | WREG32(VM_L2_CNTL2, 0); |
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| 147 | WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); |
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| 148 | /* Setup TLB control */ |
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| 149 | tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | |
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| 150 | SYSTEM_ACCESS_MODE_NOT_IN_SYS | |
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| 151 | SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU | |
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| 152 | EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5); |
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| 153 | WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp); |
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| 154 | WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp); |
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| 155 | WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp); |
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| 156 | WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp); |
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| 157 | WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); |
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| 158 | WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp); |
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| 159 | WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp); |
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| 160 | for (i = 0; i < 7; i++) |
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| 161 | WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); |
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| 162 | } |
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| 163 | |||
| 164 | static void rv770_mc_program(struct radeon_device *rdev) |
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| 165 | { |
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| 166 | struct rv515_mc_save save; |
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| 167 | u32 tmp; |
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| 168 | int i, j; |
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| 169 | |||
| 170 | /* Initialize HDP */ |
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| 171 | for (i = 0, j = 0; i < 32; i++, j += 0x18) { |
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| 172 | WREG32((0x2c14 + j), 0x00000000); |
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| 173 | WREG32((0x2c18 + j), 0x00000000); |
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| 174 | WREG32((0x2c1c + j), 0x00000000); |
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| 175 | WREG32((0x2c20 + j), 0x00000000); |
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| 176 | WREG32((0x2c24 + j), 0x00000000); |
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| 177 | } |
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| 1963 | serge | 178 | /* r7xx hw bug. Read from HDP_DEBUG1 rather |
| 179 | * than writing to HDP_REG_COHERENCY_FLUSH_CNTL |
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| 180 | */ |
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| 181 | tmp = RREG32(HDP_DEBUG1); |
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| 1246 | serge | 182 | |
| 183 | rv515_mc_stop(rdev, &save); |
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| 184 | if (r600_mc_wait_for_idle(rdev)) { |
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| 185 | dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); |
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| 186 | } |
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| 187 | /* Lockout access through VGA aperture*/ |
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| 188 | WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE); |
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| 189 | /* Update configuration */ |
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| 190 | if (rdev->flags & RADEON_IS_AGP) { |
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| 191 | if (rdev->mc.vram_start < rdev->mc.gtt_start) { |
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| 192 | /* VRAM before AGP */ |
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| 193 | WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, |
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| 194 | rdev->mc.vram_start >> 12); |
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| 195 | WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, |
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| 196 | rdev->mc.gtt_end >> 12); |
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| 197 | } else { |
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| 198 | /* VRAM after AGP */ |
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| 199 | WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, |
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| 200 | rdev->mc.gtt_start >> 12); |
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| 201 | WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, |
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| 202 | rdev->mc.vram_end >> 12); |
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| 203 | } |
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| 204 | } else { |
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| 205 | WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, |
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| 206 | rdev->mc.vram_start >> 12); |
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| 207 | WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, |
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| 208 | rdev->mc.vram_end >> 12); |
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| 209 | } |
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| 210 | WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0); |
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| 211 | tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16; |
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| 212 | tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF); |
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| 213 | WREG32(MC_VM_FB_LOCATION, tmp); |
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| 214 | WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8)); |
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| 215 | WREG32(HDP_NONSURFACE_INFO, (2 << 7)); |
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| 1963 | serge | 216 | WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF); |
| 1246 | serge | 217 | if (rdev->flags & RADEON_IS_AGP) { |
| 218 | WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16); |
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| 219 | WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16); |
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| 220 | WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22); |
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| 221 | } else { |
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| 222 | WREG32(MC_VM_AGP_BASE, 0); |
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| 223 | WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF); |
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| 224 | WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF); |
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| 225 | } |
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| 226 | if (r600_mc_wait_for_idle(rdev)) { |
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| 227 | dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); |
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| 228 | } |
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| 229 | rv515_mc_resume(rdev, &save); |
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| 230 | /* we need to own VRAM, so turn off the VGA renderer here |
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| 231 | * to stop it overwriting our objects */ |
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| 232 | rv515_vga_render_disable(rdev); |
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| 233 | } |
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| 234 | |||
| 235 | |||
| 236 | /* |
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| 237 | * CP. |
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| 238 | */ |
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| 239 | void r700_cp_stop(struct radeon_device *rdev) |
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| 240 | { |
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| 1963 | serge | 241 | // radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); |
| 1246 | serge | 242 | WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT)); |
| 1963 | serge | 243 | WREG32(SCRATCH_UMSK, 0); |
| 1246 | serge | 244 | } |
| 245 | |||
| 246 | static int rv770_cp_load_microcode(struct radeon_device *rdev) |
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| 247 | { |
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| 248 | const __be32 *fw_data; |
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| 249 | int i; |
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| 250 | |||
| 251 | if (!rdev->me_fw || !rdev->pfp_fw) |
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| 252 | return -EINVAL; |
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| 253 | |||
| 254 | r700_cp_stop(rdev); |
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| 1963 | serge | 255 | WREG32(CP_RB_CNTL, |
| 256 | #ifdef __BIG_ENDIAN |
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| 257 | BUF_SWAP_32BIT | |
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| 258 | #endif |
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| 259 | RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3)); |
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| 1246 | serge | 260 | |
| 261 | /* Reset cp */ |
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| 262 | WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP); |
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| 263 | RREG32(GRBM_SOFT_RESET); |
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| 264 | mdelay(15); |
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| 265 | WREG32(GRBM_SOFT_RESET, 0); |
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| 266 | |||
| 267 | fw_data = (const __be32 *)rdev->pfp_fw->data; |
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| 268 | WREG32(CP_PFP_UCODE_ADDR, 0); |
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| 269 | for (i = 0; i < R700_PFP_UCODE_SIZE; i++) |
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| 270 | WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++)); |
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| 271 | WREG32(CP_PFP_UCODE_ADDR, 0); |
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| 272 | |||
| 273 | fw_data = (const __be32 *)rdev->me_fw->data; |
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| 274 | WREG32(CP_ME_RAM_WADDR, 0); |
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| 275 | for (i = 0; i < R700_PM4_UCODE_SIZE; i++) |
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| 276 | WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++)); |
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| 277 | |||
| 278 | WREG32(CP_PFP_UCODE_ADDR, 0); |
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| 279 | WREG32(CP_ME_RAM_WADDR, 0); |
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| 280 | WREG32(CP_ME_RAM_RADDR, 0); |
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| 281 | return 0; |
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| 282 | } |
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| 283 | |||
| 284 | |||
| 285 | /* |
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| 286 | * Core functions |
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| 287 | */ |
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| 1430 | serge | 288 | static u32 r700_get_tile_pipe_to_backend_map(struct radeon_device *rdev, |
| 289 | u32 num_tile_pipes, |
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| 1246 | serge | 290 | u32 num_backends, |
| 291 | u32 backend_disable_mask) |
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| 292 | { |
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| 293 | u32 backend_map = 0; |
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| 294 | u32 enabled_backends_mask; |
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| 295 | u32 enabled_backends_count; |
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| 296 | u32 cur_pipe; |
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| 297 | u32 swizzle_pipe[R7XX_MAX_PIPES]; |
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| 298 | u32 cur_backend; |
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| 299 | u32 i; |
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| 1430 | serge | 300 | bool force_no_swizzle; |
| 1246 | serge | 301 | |
| 302 | if (num_tile_pipes > R7XX_MAX_PIPES) |
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| 303 | num_tile_pipes = R7XX_MAX_PIPES; |
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| 304 | if (num_tile_pipes < 1) |
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| 305 | num_tile_pipes = 1; |
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| 306 | if (num_backends > R7XX_MAX_BACKENDS) |
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| 307 | num_backends = R7XX_MAX_BACKENDS; |
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| 308 | if (num_backends < 1) |
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| 309 | num_backends = 1; |
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| 310 | |||
| 311 | enabled_backends_mask = 0; |
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| 312 | enabled_backends_count = 0; |
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| 313 | for (i = 0; i < R7XX_MAX_BACKENDS; ++i) { |
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| 314 | if (((backend_disable_mask >> i) & 1) == 0) { |
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| 315 | enabled_backends_mask |= (1 << i); |
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| 316 | ++enabled_backends_count; |
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| 317 | } |
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| 318 | if (enabled_backends_count == num_backends) |
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| 319 | break; |
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| 320 | } |
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| 321 | |||
| 322 | if (enabled_backends_count == 0) { |
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| 323 | enabled_backends_mask = 1; |
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| 324 | enabled_backends_count = 1; |
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| 325 | } |
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| 326 | |||
| 327 | if (enabled_backends_count != num_backends) |
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| 328 | num_backends = enabled_backends_count; |
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| 329 | |||
| 1430 | serge | 330 | switch (rdev->family) { |
| 331 | case CHIP_RV770: |
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| 332 | case CHIP_RV730: |
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| 333 | force_no_swizzle = false; |
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| 334 | break; |
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| 335 | case CHIP_RV710: |
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| 336 | case CHIP_RV740: |
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| 337 | default: |
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| 338 | force_no_swizzle = true; |
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| 339 | break; |
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| 340 | } |
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| 341 | |||
| 1246 | serge | 342 | memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R7XX_MAX_PIPES); |
| 343 | switch (num_tile_pipes) { |
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| 344 | case 1: |
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| 345 | swizzle_pipe[0] = 0; |
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| 346 | break; |
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| 347 | case 2: |
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| 348 | swizzle_pipe[0] = 0; |
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| 349 | swizzle_pipe[1] = 1; |
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| 350 | break; |
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| 351 | case 3: |
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| 1430 | serge | 352 | if (force_no_swizzle) { |
| 353 | swizzle_pipe[0] = 0; |
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| 354 | swizzle_pipe[1] = 1; |
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| 355 | swizzle_pipe[2] = 2; |
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| 356 | } else { |
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| 1246 | serge | 357 | swizzle_pipe[0] = 0; |
| 358 | swizzle_pipe[1] = 2; |
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| 359 | swizzle_pipe[2] = 1; |
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| 1430 | serge | 360 | } |
| 1246 | serge | 361 | break; |
| 362 | case 4: |
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| 1430 | serge | 363 | if (force_no_swizzle) { |
| 364 | swizzle_pipe[0] = 0; |
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| 365 | swizzle_pipe[1] = 1; |
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| 366 | swizzle_pipe[2] = 2; |
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| 367 | swizzle_pipe[3] = 3; |
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| 368 | } else { |
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| 1246 | serge | 369 | swizzle_pipe[0] = 0; |
| 370 | swizzle_pipe[1] = 2; |
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| 371 | swizzle_pipe[2] = 3; |
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| 372 | swizzle_pipe[3] = 1; |
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| 1430 | serge | 373 | } |
| 1246 | serge | 374 | break; |
| 375 | case 5: |
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| 1430 | serge | 376 | if (force_no_swizzle) { |
| 377 | swizzle_pipe[0] = 0; |
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| 378 | swizzle_pipe[1] = 1; |
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| 379 | swizzle_pipe[2] = 2; |
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| 380 | swizzle_pipe[3] = 3; |
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| 381 | swizzle_pipe[4] = 4; |
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| 382 | } else { |
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| 1246 | serge | 383 | swizzle_pipe[0] = 0; |
| 384 | swizzle_pipe[1] = 2; |
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| 385 | swizzle_pipe[2] = 4; |
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| 386 | swizzle_pipe[3] = 1; |
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| 387 | swizzle_pipe[4] = 3; |
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| 1430 | serge | 388 | } |
| 1246 | serge | 389 | break; |
| 390 | case 6: |
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| 1430 | serge | 391 | if (force_no_swizzle) { |
| 392 | swizzle_pipe[0] = 0; |
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| 393 | swizzle_pipe[1] = 1; |
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| 394 | swizzle_pipe[2] = 2; |
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| 395 | swizzle_pipe[3] = 3; |
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| 396 | swizzle_pipe[4] = 4; |
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| 397 | swizzle_pipe[5] = 5; |
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| 398 | } else { |
||
| 1246 | serge | 399 | swizzle_pipe[0] = 0; |
| 400 | swizzle_pipe[1] = 2; |
||
| 401 | swizzle_pipe[2] = 4; |
||
| 402 | swizzle_pipe[3] = 5; |
||
| 403 | swizzle_pipe[4] = 3; |
||
| 404 | swizzle_pipe[5] = 1; |
||
| 1430 | serge | 405 | } |
| 1246 | serge | 406 | break; |
| 407 | case 7: |
||
| 1430 | serge | 408 | if (force_no_swizzle) { |
| 409 | swizzle_pipe[0] = 0; |
||
| 410 | swizzle_pipe[1] = 1; |
||
| 411 | swizzle_pipe[2] = 2; |
||
| 412 | swizzle_pipe[3] = 3; |
||
| 413 | swizzle_pipe[4] = 4; |
||
| 414 | swizzle_pipe[5] = 5; |
||
| 415 | swizzle_pipe[6] = 6; |
||
| 416 | } else { |
||
| 1246 | serge | 417 | swizzle_pipe[0] = 0; |
| 418 | swizzle_pipe[1] = 2; |
||
| 419 | swizzle_pipe[2] = 4; |
||
| 420 | swizzle_pipe[3] = 6; |
||
| 421 | swizzle_pipe[4] = 3; |
||
| 422 | swizzle_pipe[5] = 1; |
||
| 423 | swizzle_pipe[6] = 5; |
||
| 1430 | serge | 424 | } |
| 1246 | serge | 425 | break; |
| 426 | case 8: |
||
| 1430 | serge | 427 | if (force_no_swizzle) { |
| 428 | swizzle_pipe[0] = 0; |
||
| 429 | swizzle_pipe[1] = 1; |
||
| 430 | swizzle_pipe[2] = 2; |
||
| 431 | swizzle_pipe[3] = 3; |
||
| 432 | swizzle_pipe[4] = 4; |
||
| 433 | swizzle_pipe[5] = 5; |
||
| 434 | swizzle_pipe[6] = 6; |
||
| 435 | swizzle_pipe[7] = 7; |
||
| 436 | } else { |
||
| 1246 | serge | 437 | swizzle_pipe[0] = 0; |
| 438 | swizzle_pipe[1] = 2; |
||
| 439 | swizzle_pipe[2] = 4; |
||
| 440 | swizzle_pipe[3] = 6; |
||
| 441 | swizzle_pipe[4] = 3; |
||
| 442 | swizzle_pipe[5] = 1; |
||
| 443 | swizzle_pipe[6] = 7; |
||
| 444 | swizzle_pipe[7] = 5; |
||
| 1430 | serge | 445 | } |
| 1246 | serge | 446 | break; |
| 447 | } |
||
| 448 | |||
| 449 | cur_backend = 0; |
||
| 450 | for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) { |
||
| 451 | while (((1 << cur_backend) & enabled_backends_mask) == 0) |
||
| 452 | cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS; |
||
| 453 | |||
| 454 | backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2))); |
||
| 455 | |||
| 456 | cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS; |
||
| 457 | } |
||
| 458 | |||
| 459 | return backend_map; |
||
| 460 | } |
||
| 461 | |||
| 1963 | serge | 462 | static void rv770_program_channel_remap(struct radeon_device *rdev) |
| 463 | { |
||
| 464 | u32 tcp_chan_steer, mc_shared_chremap, tmp; |
||
| 465 | bool force_no_swizzle; |
||
| 466 | |||
| 467 | switch (rdev->family) { |
||
| 468 | case CHIP_RV770: |
||
| 469 | case CHIP_RV730: |
||
| 470 | force_no_swizzle = false; |
||
| 471 | break; |
||
| 472 | case CHIP_RV710: |
||
| 473 | case CHIP_RV740: |
||
| 474 | default: |
||
| 475 | force_no_swizzle = true; |
||
| 476 | break; |
||
| 477 | } |
||
| 478 | |||
| 479 | tmp = RREG32(MC_SHARED_CHMAP); |
||
| 480 | switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) { |
||
| 481 | case 0: |
||
| 482 | case 1: |
||
| 483 | default: |
||
| 484 | /* default mapping */ |
||
| 485 | mc_shared_chremap = 0x00fac688; |
||
| 486 | break; |
||
| 487 | case 2: |
||
| 488 | case 3: |
||
| 489 | if (force_no_swizzle) |
||
| 490 | mc_shared_chremap = 0x00fac688; |
||
| 491 | else |
||
| 492 | mc_shared_chremap = 0x00bbc298; |
||
| 493 | break; |
||
| 494 | } |
||
| 495 | |||
| 496 | if (rdev->family == CHIP_RV740) |
||
| 497 | tcp_chan_steer = 0x00ef2a60; |
||
| 498 | else |
||
| 499 | tcp_chan_steer = 0x00fac688; |
||
| 500 | |||
| 501 | WREG32(TCP_CHAN_STEER, tcp_chan_steer); |
||
| 502 | WREG32(MC_SHARED_CHREMAP, mc_shared_chremap); |
||
| 503 | } |
||
| 504 | |||
| 1246 | serge | 505 | static void rv770_gpu_init(struct radeon_device *rdev) |
| 506 | { |
||
| 507 | int i, j, num_qd_pipes; |
||
| 1430 | serge | 508 | u32 ta_aux_cntl; |
| 1246 | serge | 509 | u32 sx_debug_1; |
| 510 | u32 smx_dc_ctl0; |
||
| 1430 | serge | 511 | u32 db_debug3; |
| 1246 | serge | 512 | u32 num_gs_verts_per_thread; |
| 513 | u32 vgt_gs_per_es; |
||
| 514 | u32 gs_prim_buffer_depth = 0; |
||
| 515 | u32 sq_ms_fifo_sizes; |
||
| 516 | u32 sq_config; |
||
| 517 | u32 sq_thread_resource_mgmt; |
||
| 518 | u32 hdp_host_path_cntl; |
||
| 519 | u32 sq_dyn_gpr_size_simd_ab_0; |
||
| 520 | u32 backend_map; |
||
| 521 | u32 gb_tiling_config = 0; |
||
| 522 | u32 cc_rb_backend_disable = 0; |
||
| 523 | u32 cc_gc_shader_pipe_config = 0; |
||
| 524 | u32 mc_arb_ramcfg; |
||
| 525 | u32 db_debug4; |
||
| 526 | |||
| 527 | /* setup chip specs */ |
||
| 528 | switch (rdev->family) { |
||
| 529 | case CHIP_RV770: |
||
| 530 | rdev->config.rv770.max_pipes = 4; |
||
| 531 | rdev->config.rv770.max_tile_pipes = 8; |
||
| 532 | rdev->config.rv770.max_simds = 10; |
||
| 533 | rdev->config.rv770.max_backends = 4; |
||
| 534 | rdev->config.rv770.max_gprs = 256; |
||
| 535 | rdev->config.rv770.max_threads = 248; |
||
| 536 | rdev->config.rv770.max_stack_entries = 512; |
||
| 537 | rdev->config.rv770.max_hw_contexts = 8; |
||
| 538 | rdev->config.rv770.max_gs_threads = 16 * 2; |
||
| 539 | rdev->config.rv770.sx_max_export_size = 128; |
||
| 540 | rdev->config.rv770.sx_max_export_pos_size = 16; |
||
| 541 | rdev->config.rv770.sx_max_export_smx_size = 112; |
||
| 542 | rdev->config.rv770.sq_num_cf_insts = 2; |
||
| 543 | |||
| 544 | rdev->config.rv770.sx_num_of_sets = 7; |
||
| 545 | rdev->config.rv770.sc_prim_fifo_size = 0xF9; |
||
| 546 | rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30; |
||
| 547 | rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130; |
||
| 548 | break; |
||
| 549 | case CHIP_RV730: |
||
| 550 | rdev->config.rv770.max_pipes = 2; |
||
| 551 | rdev->config.rv770.max_tile_pipes = 4; |
||
| 552 | rdev->config.rv770.max_simds = 8; |
||
| 553 | rdev->config.rv770.max_backends = 2; |
||
| 554 | rdev->config.rv770.max_gprs = 128; |
||
| 555 | rdev->config.rv770.max_threads = 248; |
||
| 556 | rdev->config.rv770.max_stack_entries = 256; |
||
| 557 | rdev->config.rv770.max_hw_contexts = 8; |
||
| 558 | rdev->config.rv770.max_gs_threads = 16 * 2; |
||
| 559 | rdev->config.rv770.sx_max_export_size = 256; |
||
| 560 | rdev->config.rv770.sx_max_export_pos_size = 32; |
||
| 561 | rdev->config.rv770.sx_max_export_smx_size = 224; |
||
| 562 | rdev->config.rv770.sq_num_cf_insts = 2; |
||
| 563 | |||
| 564 | rdev->config.rv770.sx_num_of_sets = 7; |
||
| 565 | rdev->config.rv770.sc_prim_fifo_size = 0xf9; |
||
| 566 | rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30; |
||
| 567 | rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130; |
||
| 568 | if (rdev->config.rv770.sx_max_export_pos_size > 16) { |
||
| 569 | rdev->config.rv770.sx_max_export_pos_size -= 16; |
||
| 570 | rdev->config.rv770.sx_max_export_smx_size += 16; |
||
| 571 | } |
||
| 572 | break; |
||
| 573 | case CHIP_RV710: |
||
| 574 | rdev->config.rv770.max_pipes = 2; |
||
| 575 | rdev->config.rv770.max_tile_pipes = 2; |
||
| 576 | rdev->config.rv770.max_simds = 2; |
||
| 577 | rdev->config.rv770.max_backends = 1; |
||
| 578 | rdev->config.rv770.max_gprs = 256; |
||
| 579 | rdev->config.rv770.max_threads = 192; |
||
| 580 | rdev->config.rv770.max_stack_entries = 256; |
||
| 581 | rdev->config.rv770.max_hw_contexts = 4; |
||
| 582 | rdev->config.rv770.max_gs_threads = 8 * 2; |
||
| 583 | rdev->config.rv770.sx_max_export_size = 128; |
||
| 584 | rdev->config.rv770.sx_max_export_pos_size = 16; |
||
| 585 | rdev->config.rv770.sx_max_export_smx_size = 112; |
||
| 586 | rdev->config.rv770.sq_num_cf_insts = 1; |
||
| 587 | |||
| 588 | rdev->config.rv770.sx_num_of_sets = 7; |
||
| 589 | rdev->config.rv770.sc_prim_fifo_size = 0x40; |
||
| 590 | rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30; |
||
| 591 | rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130; |
||
| 592 | break; |
||
| 593 | case CHIP_RV740: |
||
| 594 | rdev->config.rv770.max_pipes = 4; |
||
| 595 | rdev->config.rv770.max_tile_pipes = 4; |
||
| 596 | rdev->config.rv770.max_simds = 8; |
||
| 597 | rdev->config.rv770.max_backends = 4; |
||
| 598 | rdev->config.rv770.max_gprs = 256; |
||
| 599 | rdev->config.rv770.max_threads = 248; |
||
| 600 | rdev->config.rv770.max_stack_entries = 512; |
||
| 601 | rdev->config.rv770.max_hw_contexts = 8; |
||
| 602 | rdev->config.rv770.max_gs_threads = 16 * 2; |
||
| 603 | rdev->config.rv770.sx_max_export_size = 256; |
||
| 604 | rdev->config.rv770.sx_max_export_pos_size = 32; |
||
| 605 | rdev->config.rv770.sx_max_export_smx_size = 224; |
||
| 606 | rdev->config.rv770.sq_num_cf_insts = 2; |
||
| 607 | |||
| 608 | rdev->config.rv770.sx_num_of_sets = 7; |
||
| 609 | rdev->config.rv770.sc_prim_fifo_size = 0x100; |
||
| 610 | rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30; |
||
| 611 | rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130; |
||
| 612 | |||
| 613 | if (rdev->config.rv770.sx_max_export_pos_size > 16) { |
||
| 614 | rdev->config.rv770.sx_max_export_pos_size -= 16; |
||
| 615 | rdev->config.rv770.sx_max_export_smx_size += 16; |
||
| 616 | } |
||
| 617 | break; |
||
| 618 | default: |
||
| 619 | break; |
||
| 620 | } |
||
| 621 | |||
| 622 | /* Initialize HDP */ |
||
| 623 | j = 0; |
||
| 624 | for (i = 0; i < 32; i++) { |
||
| 625 | WREG32((0x2c14 + j), 0x00000000); |
||
| 626 | WREG32((0x2c18 + j), 0x00000000); |
||
| 627 | WREG32((0x2c1c + j), 0x00000000); |
||
| 628 | WREG32((0x2c20 + j), 0x00000000); |
||
| 629 | WREG32((0x2c24 + j), 0x00000000); |
||
| 630 | j += 0x18; |
||
| 631 | } |
||
| 632 | |||
| 633 | WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); |
||
| 634 | |||
| 635 | /* setup tiling, simd, pipe config */ |
||
| 636 | mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG); |
||
| 637 | |||
| 638 | switch (rdev->config.rv770.max_tile_pipes) { |
||
| 639 | case 1: |
||
| 1430 | serge | 640 | default: |
| 1246 | serge | 641 | gb_tiling_config |= PIPE_TILING(0); |
| 642 | break; |
||
| 643 | case 2: |
||
| 644 | gb_tiling_config |= PIPE_TILING(1); |
||
| 645 | break; |
||
| 646 | case 4: |
||
| 647 | gb_tiling_config |= PIPE_TILING(2); |
||
| 648 | break; |
||
| 649 | case 8: |
||
| 650 | gb_tiling_config |= PIPE_TILING(3); |
||
| 651 | break; |
||
| 652 | } |
||
| 1430 | serge | 653 | rdev->config.rv770.tiling_npipes = rdev->config.rv770.max_tile_pipes; |
| 1246 | serge | 654 | |
| 655 | if (rdev->family == CHIP_RV770) |
||
| 656 | gb_tiling_config |= BANK_TILING(1); |
||
| 657 | else |
||
| 1268 | serge | 658 | gb_tiling_config |= BANK_TILING((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT); |
| 1430 | serge | 659 | rdev->config.rv770.tiling_nbanks = 4 << ((gb_tiling_config >> 4) & 0x3); |
| 1963 | serge | 660 | gb_tiling_config |= GROUP_SIZE((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT); |
| 661 | if ((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT) |
||
| 662 | rdev->config.rv770.tiling_group_size = 512; |
||
| 663 | else |
||
| 1430 | serge | 664 | rdev->config.rv770.tiling_group_size = 256; |
| 1268 | serge | 665 | if (((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT) > 3) { |
| 1246 | serge | 666 | gb_tiling_config |= ROW_TILING(3); |
| 667 | gb_tiling_config |= SAMPLE_SPLIT(3); |
||
| 668 | } else { |
||
| 669 | gb_tiling_config |= |
||
| 670 | ROW_TILING(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT)); |
||
| 671 | gb_tiling_config |= |
||
| 672 | SAMPLE_SPLIT(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT)); |
||
| 673 | } |
||
| 674 | |||
| 675 | gb_tiling_config |= BANK_SWAPS(1); |
||
| 676 | |||
| 1430 | serge | 677 | cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000; |
| 678 | cc_rb_backend_disable |= |
||
| 679 | BACKEND_DISABLE((R7XX_MAX_BACKENDS_MASK << rdev->config.rv770.max_backends) & R7XX_MAX_BACKENDS_MASK); |
||
| 1246 | serge | 680 | |
| 1430 | serge | 681 | cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00; |
| 682 | cc_gc_shader_pipe_config |= |
||
| 1246 | serge | 683 | INACTIVE_QD_PIPES((R7XX_MAX_PIPES_MASK << rdev->config.rv770.max_pipes) & R7XX_MAX_PIPES_MASK); |
| 684 | cc_gc_shader_pipe_config |= |
||
| 685 | INACTIVE_SIMDS((R7XX_MAX_SIMDS_MASK << rdev->config.rv770.max_simds) & R7XX_MAX_SIMDS_MASK); |
||
| 686 | |||
| 1430 | serge | 687 | if (rdev->family == CHIP_RV740) |
| 688 | backend_map = 0x28; |
||
| 689 | else |
||
| 690 | backend_map = r700_get_tile_pipe_to_backend_map(rdev, |
||
| 691 | rdev->config.rv770.max_tile_pipes, |
||
| 692 | (R7XX_MAX_BACKENDS - |
||
| 693 | r600_count_pipe_bits((cc_rb_backend_disable & |
||
| 694 | R7XX_MAX_BACKENDS_MASK) >> 16)), |
||
| 695 | (cc_rb_backend_disable >> 16)); |
||
| 1963 | serge | 696 | |
| 697 | rdev->config.rv770.tile_config = gb_tiling_config; |
||
| 1430 | serge | 698 | gb_tiling_config |= BACKEND_MAP(backend_map); |
| 1246 | serge | 699 | |
| 700 | WREG32(GB_TILING_CONFIG, gb_tiling_config); |
||
| 701 | WREG32(DCP_TILING_CONFIG, (gb_tiling_config & 0xffff)); |
||
| 702 | WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff)); |
||
| 703 | |||
| 1963 | serge | 704 | rv770_program_channel_remap(rdev); |
| 705 | |||
| 1246 | serge | 706 | WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable); |
| 707 | WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); |
||
| 1963 | serge | 708 | WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); |
| 1430 | serge | 709 | WREG32(CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable); |
| 1246 | serge | 710 | |
| 711 | WREG32(CGTS_SYS_TCC_DISABLE, 0); |
||
| 712 | WREG32(CGTS_TCC_DISABLE, 0); |
||
| 1963 | serge | 713 | WREG32(CGTS_USER_SYS_TCC_DISABLE, 0); |
| 714 | WREG32(CGTS_USER_TCC_DISABLE, 0); |
||
| 1246 | serge | 715 | |
| 716 | num_qd_pipes = |
||
| 1430 | serge | 717 | R7XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8); |
| 1246 | serge | 718 | WREG32(VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & DEALLOC_DIST_MASK); |
| 719 | WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & VTX_REUSE_DEPTH_MASK); |
||
| 720 | |||
| 721 | /* set HW defaults for 3D engine */ |
||
| 722 | WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | |
||
| 723 | ROQ_IB2_START(0x2b))); |
||
| 724 | |||
| 725 | WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30)); |
||
| 726 | |||
| 1430 | serge | 727 | ta_aux_cntl = RREG32(TA_CNTL_AUX); |
| 728 | WREG32(TA_CNTL_AUX, ta_aux_cntl | DISABLE_CUBE_ANISO); |
||
| 1246 | serge | 729 | |
| 730 | sx_debug_1 = RREG32(SX_DEBUG_1); |
||
| 731 | sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS; |
||
| 732 | WREG32(SX_DEBUG_1, sx_debug_1); |
||
| 733 | |||
| 734 | smx_dc_ctl0 = RREG32(SMX_DC_CTL0); |
||
| 735 | smx_dc_ctl0 &= ~CACHE_DEPTH(0x1ff); |
||
| 736 | smx_dc_ctl0 |= CACHE_DEPTH((rdev->config.rv770.sx_num_of_sets * 64) - 1); |
||
| 737 | WREG32(SMX_DC_CTL0, smx_dc_ctl0); |
||
| 738 | |||
| 1430 | serge | 739 | if (rdev->family != CHIP_RV740) |
| 1246 | serge | 740 | WREG32(SMX_EVENT_CTL, (ES_FLUSH_CTL(4) | |
| 741 | GS_FLUSH_CTL(4) | |
||
| 742 | ACK_FLUSH_CTL(3) | |
||
| 743 | SYNC_FLUSH_CTL)); |
||
| 744 | |||
| 1430 | serge | 745 | db_debug3 = RREG32(DB_DEBUG3); |
| 746 | db_debug3 &= ~DB_CLK_OFF_DELAY(0x1f); |
||
| 747 | switch (rdev->family) { |
||
| 748 | case CHIP_RV770: |
||
| 749 | case CHIP_RV740: |
||
| 750 | db_debug3 |= DB_CLK_OFF_DELAY(0x1f); |
||
| 751 | break; |
||
| 752 | case CHIP_RV710: |
||
| 753 | case CHIP_RV730: |
||
| 754 | default: |
||
| 755 | db_debug3 |= DB_CLK_OFF_DELAY(2); |
||
| 756 | break; |
||
| 757 | } |
||
| 758 | WREG32(DB_DEBUG3, db_debug3); |
||
| 759 | |||
| 760 | if (rdev->family != CHIP_RV770) { |
||
| 1246 | serge | 761 | db_debug4 = RREG32(DB_DEBUG4); |
| 762 | db_debug4 |= DISABLE_TILE_COVERED_FOR_PS_ITER; |
||
| 763 | WREG32(DB_DEBUG4, db_debug4); |
||
| 764 | } |
||
| 765 | |||
| 766 | WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.rv770.sx_max_export_size / 4) - 1) | |
||
| 767 | POSITION_BUFFER_SIZE((rdev->config.rv770.sx_max_export_pos_size / 4) - 1) | |
||
| 768 | SMX_BUFFER_SIZE((rdev->config.rv770.sx_max_export_smx_size / 4) - 1))); |
||
| 769 | |||
| 770 | WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.rv770.sc_prim_fifo_size) | |
||
| 771 | SC_HIZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_hiz_tile_fifo_size) | |
||
| 772 | SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_earlyz_tile_fifo_fize))); |
||
| 773 | |||
| 774 | WREG32(PA_SC_MULTI_CHIP_CNTL, 0); |
||
| 775 | |||
| 776 | WREG32(VGT_NUM_INSTANCES, 1); |
||
| 777 | |||
| 778 | WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0)); |
||
| 779 | |||
| 780 | WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4)); |
||
| 781 | |||
| 782 | WREG32(CP_PERFMON_CNTL, 0); |
||
| 783 | |||
| 784 | sq_ms_fifo_sizes = (CACHE_FIFO_SIZE(16 * rdev->config.rv770.sq_num_cf_insts) | |
||
| 785 | DONE_FIFO_HIWATER(0xe0) | |
||
| 786 | ALU_UPDATE_FIFO_HIWATER(0x8)); |
||
| 787 | switch (rdev->family) { |
||
| 788 | case CHIP_RV770: |
||
| 1430 | serge | 789 | case CHIP_RV730: |
| 790 | case CHIP_RV710: |
||
| 1246 | serge | 791 | sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x1); |
| 792 | break; |
||
| 793 | case CHIP_RV740: |
||
| 794 | default: |
||
| 795 | sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x4); |
||
| 796 | break; |
||
| 797 | } |
||
| 798 | WREG32(SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes); |
||
| 799 | |||
| 800 | /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT |
||
| 801 | * should be adjusted as needed by the 2D/3D drivers. This just sets default values |
||
| 802 | */ |
||
| 803 | sq_config = RREG32(SQ_CONFIG); |
||
| 804 | sq_config &= ~(PS_PRIO(3) | |
||
| 805 | VS_PRIO(3) | |
||
| 806 | GS_PRIO(3) | |
||
| 807 | ES_PRIO(3)); |
||
| 808 | sq_config |= (DX9_CONSTS | |
||
| 809 | VC_ENABLE | |
||
| 810 | EXPORT_SRC_C | |
||
| 811 | PS_PRIO(0) | |
||
| 812 | VS_PRIO(1) | |
||
| 813 | GS_PRIO(2) | |
||
| 814 | ES_PRIO(3)); |
||
| 815 | if (rdev->family == CHIP_RV710) |
||
| 816 | /* no vertex cache */ |
||
| 817 | sq_config &= ~VC_ENABLE; |
||
| 818 | |||
| 819 | WREG32(SQ_CONFIG, sq_config); |
||
| 820 | |||
| 821 | WREG32(SQ_GPR_RESOURCE_MGMT_1, (NUM_PS_GPRS((rdev->config.rv770.max_gprs * 24)/64) | |
||
| 822 | NUM_VS_GPRS((rdev->config.rv770.max_gprs * 24)/64) | |
||
| 823 | NUM_CLAUSE_TEMP_GPRS(((rdev->config.rv770.max_gprs * 24)/64)/2))); |
||
| 824 | |||
| 825 | WREG32(SQ_GPR_RESOURCE_MGMT_2, (NUM_GS_GPRS((rdev->config.rv770.max_gprs * 7)/64) | |
||
| 826 | NUM_ES_GPRS((rdev->config.rv770.max_gprs * 7)/64))); |
||
| 827 | |||
| 828 | sq_thread_resource_mgmt = (NUM_PS_THREADS((rdev->config.rv770.max_threads * 4)/8) | |
||
| 829 | NUM_VS_THREADS((rdev->config.rv770.max_threads * 2)/8) | |
||
| 830 | NUM_ES_THREADS((rdev->config.rv770.max_threads * 1)/8)); |
||
| 831 | if (((rdev->config.rv770.max_threads * 1) / 8) > rdev->config.rv770.max_gs_threads) |
||
| 832 | sq_thread_resource_mgmt |= NUM_GS_THREADS(rdev->config.rv770.max_gs_threads); |
||
| 833 | else |
||
| 834 | sq_thread_resource_mgmt |= NUM_GS_THREADS((rdev->config.rv770.max_gs_threads * 1)/8); |
||
| 835 | WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt); |
||
| 836 | |||
| 837 | WREG32(SQ_STACK_RESOURCE_MGMT_1, (NUM_PS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) | |
||
| 838 | NUM_VS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4))); |
||
| 839 | |||
| 840 | WREG32(SQ_STACK_RESOURCE_MGMT_2, (NUM_GS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) | |
||
| 841 | NUM_ES_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4))); |
||
| 842 | |||
| 843 | sq_dyn_gpr_size_simd_ab_0 = (SIMDA_RING0((rdev->config.rv770.max_gprs * 38)/64) | |
||
| 844 | SIMDA_RING1((rdev->config.rv770.max_gprs * 38)/64) | |
||
| 845 | SIMDB_RING0((rdev->config.rv770.max_gprs * 38)/64) | |
||
| 846 | SIMDB_RING1((rdev->config.rv770.max_gprs * 38)/64)); |
||
| 847 | |||
| 848 | WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_0, sq_dyn_gpr_size_simd_ab_0); |
||
| 849 | WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_1, sq_dyn_gpr_size_simd_ab_0); |
||
| 850 | WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_2, sq_dyn_gpr_size_simd_ab_0); |
||
| 851 | WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_3, sq_dyn_gpr_size_simd_ab_0); |
||
| 852 | WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_4, sq_dyn_gpr_size_simd_ab_0); |
||
| 853 | WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_5, sq_dyn_gpr_size_simd_ab_0); |
||
| 854 | WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_6, sq_dyn_gpr_size_simd_ab_0); |
||
| 855 | WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_7, sq_dyn_gpr_size_simd_ab_0); |
||
| 856 | |||
| 857 | WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) | |
||
| 858 | FORCE_EOV_MAX_REZ_CNT(255))); |
||
| 859 | |||
| 860 | if (rdev->family == CHIP_RV710) |
||
| 861 | WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(TC_ONLY) | |
||
| 862 | AUTO_INVLD_EN(ES_AND_GS_AUTO))); |
||
| 863 | else |
||
| 864 | WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(VC_AND_TC) | |
||
| 865 | AUTO_INVLD_EN(ES_AND_GS_AUTO))); |
||
| 866 | |||
| 867 | switch (rdev->family) { |
||
| 868 | case CHIP_RV770: |
||
| 869 | case CHIP_RV730: |
||
| 870 | case CHIP_RV740: |
||
| 871 | gs_prim_buffer_depth = 384; |
||
| 872 | break; |
||
| 873 | case CHIP_RV710: |
||
| 874 | gs_prim_buffer_depth = 128; |
||
| 875 | break; |
||
| 876 | default: |
||
| 877 | break; |
||
| 878 | } |
||
| 879 | |||
| 880 | num_gs_verts_per_thread = rdev->config.rv770.max_pipes * 16; |
||
| 881 | vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread; |
||
| 882 | /* Max value for this is 256 */ |
||
| 883 | if (vgt_gs_per_es > 256) |
||
| 884 | vgt_gs_per_es = 256; |
||
| 885 | |||
| 886 | WREG32(VGT_ES_PER_GS, 128); |
||
| 887 | WREG32(VGT_GS_PER_ES, vgt_gs_per_es); |
||
| 888 | WREG32(VGT_GS_PER_VS, 2); |
||
| 889 | |||
| 890 | /* more default values. 2D/3D driver should adjust as needed */ |
||
| 891 | WREG32(VGT_GS_VERTEX_REUSE, 16); |
||
| 892 | WREG32(PA_SC_LINE_STIPPLE_STATE, 0); |
||
| 893 | WREG32(VGT_STRMOUT_EN, 0); |
||
| 894 | WREG32(SX_MISC, 0); |
||
| 895 | WREG32(PA_SC_MODE_CNTL, 0); |
||
| 896 | WREG32(PA_SC_EDGERULE, 0xaaaaaaaa); |
||
| 897 | WREG32(PA_SC_AA_CONFIG, 0); |
||
| 898 | WREG32(PA_SC_CLIPRECT_RULE, 0xffff); |
||
| 899 | WREG32(PA_SC_LINE_STIPPLE, 0); |
||
| 900 | WREG32(SPI_INPUT_Z, 0); |
||
| 901 | WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2)); |
||
| 902 | WREG32(CB_COLOR7_FRAG, 0); |
||
| 903 | |||
| 904 | /* clear render buffer base addresses */ |
||
| 905 | WREG32(CB_COLOR0_BASE, 0); |
||
| 906 | WREG32(CB_COLOR1_BASE, 0); |
||
| 907 | WREG32(CB_COLOR2_BASE, 0); |
||
| 908 | WREG32(CB_COLOR3_BASE, 0); |
||
| 909 | WREG32(CB_COLOR4_BASE, 0); |
||
| 910 | WREG32(CB_COLOR5_BASE, 0); |
||
| 911 | WREG32(CB_COLOR6_BASE, 0); |
||
| 912 | WREG32(CB_COLOR7_BASE, 0); |
||
| 913 | |||
| 914 | WREG32(TCP_CNTL, 0); |
||
| 915 | |||
| 916 | hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL); |
||
| 917 | WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl); |
||
| 918 | |||
| 919 | WREG32(PA_SC_MULTI_CHIP_CNTL, 0); |
||
| 920 | |||
| 921 | WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA | |
||
| 922 | NUM_CLIP_SEQ(3))); |
||
| 923 | |||
| 924 | } |
||
| 925 | |||
| 1963 | serge | 926 | static int rv770_vram_scratch_init(struct radeon_device *rdev) |
| 927 | { |
||
| 928 | int r; |
||
| 929 | u64 gpu_addr; |
||
| 930 | |||
| 931 | if (rdev->vram_scratch.robj == NULL) { |
||
| 932 | r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, |
||
| 933 | PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM, |
||
| 934 | &rdev->vram_scratch.robj); |
||
| 935 | if (r) { |
||
| 936 | return r; |
||
| 937 | } |
||
| 938 | } |
||
| 939 | |||
| 940 | r = radeon_bo_reserve(rdev->vram_scratch.robj, false); |
||
| 941 | if (unlikely(r != 0)) |
||
| 942 | return r; |
||
| 943 | r = radeon_bo_pin(rdev->vram_scratch.robj, |
||
| 944 | RADEON_GEM_DOMAIN_VRAM, &gpu_addr); |
||
| 945 | if (r) { |
||
| 946 | radeon_bo_unreserve(rdev->vram_scratch.robj); |
||
| 947 | return r; |
||
| 948 | } |
||
| 949 | r = radeon_bo_kmap(rdev->vram_scratch.robj, |
||
| 950 | (void **)&rdev->vram_scratch.ptr); |
||
| 951 | if (r) |
||
| 952 | radeon_bo_unpin(rdev->vram_scratch.robj); |
||
| 953 | radeon_bo_unreserve(rdev->vram_scratch.robj); |
||
| 954 | |||
| 955 | return r; |
||
| 956 | } |
||
| 957 | |||
| 958 | static void rv770_vram_scratch_fini(struct radeon_device *rdev) |
||
| 959 | { |
||
| 960 | int r; |
||
| 961 | |||
| 962 | if (rdev->vram_scratch.robj == NULL) { |
||
| 963 | return; |
||
| 964 | } |
||
| 965 | r = radeon_bo_reserve(rdev->vram_scratch.robj, false); |
||
| 966 | if (likely(r == 0)) { |
||
| 967 | radeon_bo_kunmap(rdev->vram_scratch.robj); |
||
| 968 | radeon_bo_unpin(rdev->vram_scratch.robj); |
||
| 969 | radeon_bo_unreserve(rdev->vram_scratch.robj); |
||
| 970 | } |
||
| 971 | radeon_bo_unref(&rdev->vram_scratch.robj); |
||
| 972 | } |
||
| 973 | |||
| 974 | void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc) |
||
| 975 | { |
||
| 976 | u64 size_bf, size_af; |
||
| 977 | |||
| 978 | if (mc->mc_vram_size > 0xE0000000) { |
||
| 979 | /* leave room for at least 512M GTT */ |
||
| 980 | dev_warn(rdev->dev, "limiting VRAM\n"); |
||
| 981 | mc->real_vram_size = 0xE0000000; |
||
| 982 | mc->mc_vram_size = 0xE0000000; |
||
| 983 | } |
||
| 984 | if (rdev->flags & RADEON_IS_AGP) { |
||
| 985 | size_bf = mc->gtt_start; |
||
| 986 | size_af = 0xFFFFFFFF - mc->gtt_end + 1; |
||
| 987 | if (size_bf > size_af) { |
||
| 988 | if (mc->mc_vram_size > size_bf) { |
||
| 989 | dev_warn(rdev->dev, "limiting VRAM\n"); |
||
| 990 | mc->real_vram_size = size_bf; |
||
| 991 | mc->mc_vram_size = size_bf; |
||
| 992 | } |
||
| 993 | mc->vram_start = mc->gtt_start - mc->mc_vram_size; |
||
| 994 | } else { |
||
| 995 | if (mc->mc_vram_size > size_af) { |
||
| 996 | dev_warn(rdev->dev, "limiting VRAM\n"); |
||
| 997 | mc->real_vram_size = size_af; |
||
| 998 | mc->mc_vram_size = size_af; |
||
| 999 | } |
||
| 1000 | mc->vram_start = mc->gtt_end; |
||
| 1001 | } |
||
| 1002 | mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; |
||
| 1003 | dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n", |
||
| 1004 | mc->mc_vram_size >> 20, mc->vram_start, |
||
| 1005 | mc->vram_end, mc->real_vram_size >> 20); |
||
| 1006 | } else { |
||
| 1007 | radeon_vram_location(rdev, &rdev->mc, 0); |
||
| 1008 | rdev->mc.gtt_base_align = 0; |
||
| 1009 | radeon_gtt_location(rdev, mc); |
||
| 1010 | } |
||
| 1011 | } |
||
| 1012 | |||
| 1246 | serge | 1013 | int rv770_mc_init(struct radeon_device *rdev) |
| 1014 | { |
||
| 1015 | u32 tmp; |
||
| 1268 | serge | 1016 | int chansize, numchan; |
| 1246 | serge | 1017 | |
| 1018 | /* Get VRAM informations */ |
||
| 1019 | rdev->mc.vram_is_ddr = true; |
||
| 1268 | serge | 1020 | tmp = RREG32(MC_ARB_RAMCFG); |
| 1021 | if (tmp & CHANSIZE_OVERRIDE) { |
||
| 1022 | chansize = 16; |
||
| 1023 | } else if (tmp & CHANSIZE_MASK) { |
||
| 1024 | chansize = 64; |
||
| 1025 | } else { |
||
| 1026 | chansize = 32; |
||
| 1027 | } |
||
| 1028 | tmp = RREG32(MC_SHARED_CHMAP); |
||
| 1029 | switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) { |
||
| 1030 | case 0: |
||
| 1031 | default: |
||
| 1032 | numchan = 1; |
||
| 1033 | break; |
||
| 1034 | case 1: |
||
| 1035 | numchan = 2; |
||
| 1036 | break; |
||
| 1037 | case 2: |
||
| 1038 | numchan = 4; |
||
| 1039 | break; |
||
| 1040 | case 3: |
||
| 1041 | numchan = 8; |
||
| 1042 | break; |
||
| 1043 | } |
||
| 1044 | rdev->mc.vram_width = numchan * chansize; |
||
| 1246 | serge | 1045 | /* Could aper size report 0 ? */ |
| 1963 | serge | 1046 | rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); |
| 1047 | rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); |
||
| 1246 | serge | 1048 | /* Setup GPU memory space */ |
| 1049 | rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE); |
||
| 1050 | rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); |
||
| 1430 | serge | 1051 | rdev->mc.visible_vram_size = rdev->mc.aper_size; |
| 1963 | serge | 1052 | r700_vram_gtt_location(rdev, &rdev->mc); |
| 1053 | radeon_update_bandwidth_info(rdev); |
||
| 1054 | |||
| 1246 | serge | 1055 | return 0; |
| 1056 | } |
||
| 1430 | serge | 1057 | |
| 1246 | serge | 1058 | static int rv770_startup(struct radeon_device *rdev) |
| 1059 | { |
||
| 1060 | int r; |
||
| 1061 | |||
| 1963 | serge | 1062 | /* enable pcie gen2 link */ |
| 1063 | rv770_pcie_gen2_enable(rdev); |
||
| 1064 | |||
| 1413 | serge | 1065 | if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) { |
| 1066 | r = r600_init_microcode(rdev); |
||
| 1067 | if (r) { |
||
| 1068 | DRM_ERROR("Failed to load firmware!\n"); |
||
| 1069 | return r; |
||
| 1070 | } |
||
| 1071 | } |
||
| 1072 | |||
| 1246 | serge | 1073 | rv770_mc_program(rdev); |
| 1074 | if (rdev->flags & RADEON_IS_AGP) { |
||
| 1075 | rv770_agp_enable(rdev); |
||
| 1076 | } else { |
||
| 1077 | r = rv770_pcie_gart_enable(rdev); |
||
| 1078 | if (r) |
||
| 1079 | return r; |
||
| 1080 | } |
||
| 1963 | serge | 1081 | r = rv770_vram_scratch_init(rdev); |
| 1082 | if (r) |
||
| 1083 | return r; |
||
| 1246 | serge | 1084 | rv770_gpu_init(rdev); |
| 1413 | serge | 1085 | r = radeon_ring_init(rdev, rdev->cp.ring_size); |
| 1086 | if (r) |
||
| 1087 | return r; |
||
| 1088 | r = rv770_cp_load_microcode(rdev); |
||
| 1089 | if (r) |
||
| 1090 | return r; |
||
| 1091 | r = r600_cp_resume(rdev); |
||
| 1092 | if (r) |
||
| 1093 | return r; |
||
| 1963 | serge | 1094 | |
| 1246 | serge | 1095 | return 0; |
| 1096 | } |
||
| 1097 | |||
| 1098 | |||
| 1413 | serge | 1099 | |
| 1100 | |||
| 1101 | |||
| 1102 | |||
| 1103 | |||
| 1246 | serge | 1104 | /* Plan is to move initialization in that function and use |
| 1105 | * helper function so that radeon_device_init pretty much |
||
| 1106 | * do nothing more than calling asic specific function. This |
||
| 1107 | * should also allow to remove a bunch of callback function |
||
| 1108 | * like vram_info. |
||
| 1109 | */ |
||
| 1110 | int rv770_init(struct radeon_device *rdev) |
||
| 1111 | { |
||
| 1112 | int r; |
||
| 1113 | |||
| 1114 | /* Read BIOS */ |
||
| 1115 | if (!radeon_get_bios(rdev)) { |
||
| 1116 | if (ASIC_IS_AVIVO(rdev)) |
||
| 1117 | return -EINVAL; |
||
| 1118 | } |
||
| 1119 | /* Must be an ATOMBIOS */ |
||
| 1120 | if (!rdev->is_atom_bios) { |
||
| 1121 | dev_err(rdev->dev, "Expecting atombios for R600 GPU\n"); |
||
| 1122 | return -EINVAL; |
||
| 1123 | } |
||
| 1124 | r = radeon_atombios_init(rdev); |
||
| 1125 | if (r) |
||
| 1126 | return r; |
||
| 1127 | /* Post card if necessary */ |
||
| 1963 | serge | 1128 | if (!radeon_card_posted(rdev)) { |
| 1403 | serge | 1129 | if (!rdev->bios) { |
| 1130 | dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); |
||
| 1131 | return -EINVAL; |
||
| 1132 | } |
||
| 1246 | serge | 1133 | DRM_INFO("GPU not posted. posting now...\n"); |
| 1134 | atom_asic_init(rdev->mode_info.atom_context); |
||
| 1135 | } |
||
| 1136 | /* Initialize scratch registers */ |
||
| 1137 | r600_scratch_init(rdev); |
||
| 1138 | /* Initialize surface registers */ |
||
| 1139 | radeon_surface_init(rdev); |
||
| 1268 | serge | 1140 | /* Initialize clocks */ |
| 1246 | serge | 1141 | radeon_get_clock_info(rdev->ddev); |
| 1142 | /* Fence driver */ |
||
| 1963 | serge | 1143 | // r = radeon_fence_driver_init(rdev); |
| 1144 | // if (r) |
||
| 1145 | // return r; |
||
| 1430 | serge | 1146 | /* initialize AGP */ |
| 1403 | serge | 1147 | if (rdev->flags & RADEON_IS_AGP) { |
| 1148 | r = radeon_agp_init(rdev); |
||
| 1149 | if (r) |
||
| 1150 | radeon_agp_disable(rdev); |
||
| 1151 | } |
||
| 1246 | serge | 1152 | r = rv770_mc_init(rdev); |
| 1153 | if (r) |
||
| 1154 | return r; |
||
| 1155 | /* Memory manager */ |
||
| 1403 | serge | 1156 | r = radeon_bo_init(rdev); |
| 1246 | serge | 1157 | if (r) |
| 1158 | return r; |
||
| 1159 | |||
| 1160 | |||
| 1413 | serge | 1161 | rdev->cp.ring_obj = NULL; |
| 1162 | r600_ring_init(rdev, 1024 * 1024); |
||
| 1163 | |||
| 1164 | |||
| 1246 | serge | 1165 | r = r600_pcie_gart_init(rdev); |
| 1166 | if (r) |
||
| 1167 | return r; |
||
| 1168 | |||
| 1169 | rdev->accel_working = true; |
||
| 1170 | r = rv770_startup(rdev); |
||
| 1171 | if (r) { |
||
| 1413 | serge | 1172 | dev_err(rdev->dev, "disabling GPU acceleration\n"); |
| 1173 | |||
| 1246 | serge | 1174 | rv770_pcie_gart_fini(rdev); |
| 1175 | rdev->accel_working = false; |
||
| 1176 | } |
||
| 1177 | if (rdev->accel_working) { |
||
| 1430 | serge | 1178 | // r = radeon_ib_pool_init(rdev); |
| 1179 | // if (r) { |
||
| 1180 | // dev_err(rdev->dev, "IB initialization failed (%d).\n", r); |
||
| 1181 | // rdev->accel_working = false; |
||
| 1182 | // } else { |
||
| 1183 | // r = r600_ib_test(rdev); |
||
| 1184 | // if (r) { |
||
| 1185 | // dev_err(rdev->dev, "IB test failed (%d).\n", r); |
||
| 1186 | // rdev->accel_working = false; |
||
| 1187 | // } |
||
| 1188 | // } |
||
| 1246 | serge | 1189 | } |
| 1963 | serge | 1190 | |
| 1246 | serge | 1191 | return 0; |
| 1192 | } |
||
| 1193 | |||
| 1963 | serge | 1194 | static void rv770_pcie_gen2_enable(struct radeon_device *rdev) |
| 1195 | { |
||
| 1196 | u32 link_width_cntl, lanes, speed_cntl, tmp; |
||
| 1197 | u16 link_cntl2; |
||
| 1198 | |||
| 1199 | if (radeon_pcie_gen2 == 0) |
||
| 1200 | return; |
||
| 1201 | |||
| 1202 | if (rdev->flags & RADEON_IS_IGP) |
||
| 1203 | return; |
||
| 1204 | |||
| 1205 | if (!(rdev->flags & RADEON_IS_PCIE)) |
||
| 1206 | return; |
||
| 1207 | |||
| 1208 | /* x2 cards have a special sequence */ |
||
| 1209 | if (ASIC_IS_X2(rdev)) |
||
| 1210 | return; |
||
| 1211 | |||
| 1212 | /* advertise upconfig capability */ |
||
| 1213 | link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL); |
||
| 1214 | link_width_cntl &= ~LC_UPCONFIGURE_DIS; |
||
| 1215 | WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); |
||
| 1216 | link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL); |
||
| 1217 | if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) { |
||
| 1218 | lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT; |
||
| 1219 | link_width_cntl &= ~(LC_LINK_WIDTH_MASK | |
||
| 1220 | LC_RECONFIG_ARC_MISSING_ESCAPE); |
||
| 1221 | link_width_cntl |= lanes | LC_RECONFIG_NOW | |
||
| 1222 | LC_RENEGOTIATE_EN | LC_UPCONFIGURE_SUPPORT; |
||
| 1223 | WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); |
||
| 1224 | } else { |
||
| 1225 | link_width_cntl |= LC_UPCONFIGURE_DIS; |
||
| 1226 | WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); |
||
| 1227 | } |
||
| 1228 | |||
| 1229 | speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); |
||
| 1230 | if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) && |
||
| 1231 | (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) { |
||
| 1232 | |||
| 1233 | tmp = RREG32(0x541c); |
||
| 1234 | WREG32(0x541c, tmp | 0x8); |
||
| 1235 | WREG32(MM_CFGREGS_CNTL, MM_WR_TO_CFG_EN); |
||
| 1236 | link_cntl2 = RREG16(0x4088); |
||
| 1237 | link_cntl2 &= ~TARGET_LINK_SPEED_MASK; |
||
| 1238 | link_cntl2 |= 0x2; |
||
| 1239 | WREG16(0x4088, link_cntl2); |
||
| 1240 | WREG32(MM_CFGREGS_CNTL, 0); |
||
| 1241 | |||
| 1242 | speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); |
||
| 1243 | speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN; |
||
| 1244 | WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); |
||
| 1245 | |||
| 1246 | speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); |
||
| 1247 | speed_cntl |= LC_CLR_FAILED_SPD_CHANGE_CNT; |
||
| 1248 | WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); |
||
| 1249 | |||
| 1250 | speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); |
||
| 1251 | speed_cntl &= ~LC_CLR_FAILED_SPD_CHANGE_CNT; |
||
| 1252 | WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); |
||
| 1253 | |||
| 1254 | speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); |
||
| 1255 | speed_cntl |= LC_GEN2_EN_STRAP; |
||
| 1256 | WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); |
||
| 1257 | |||
| 1258 | } else { |
||
| 1259 | link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL); |
||
| 1260 | /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */ |
||
| 1261 | if (1) |
||
| 1262 | link_width_cntl |= LC_UPCONFIGURE_DIS; |
||
| 1263 | else |
||
| 1264 | link_width_cntl &= ~LC_UPCONFIGURE_DIS; |
||
| 1265 | WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); |
||
| 1266 | } |
||
| 1267 | } |