WebSVN – Kolibri OS – Blame – /drivers/video/drm/radeon/rv770.c

Rev	Author	Line No.	Line
1246	serge	1	/*
		2	* Copyright 2008 Advanced Micro Devices, Inc.
		3	* Copyright 2008 Red Hat Inc.
		4	* Copyright 2009 Jerome Glisse.
		5	*
		6	* Permission is hereby granted, free of charge, to any person obtaining a
		7	* copy of this software and associated documentation files (the "Software"),
		8	* to deal in the Software without restriction, including without limitation
		9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		10	* and/or sell copies of the Software, and to permit persons to whom the
		11	* Software is furnished to do so, subject to the following conditions:
		12	*
		13	* The above copyright notice and this permission notice shall be included in
		14	* all copies or substantial portions of the Software.
		15	*
		16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
		20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
		21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
		22	* OTHER DEALINGS IN THE SOFTWARE.
		23	*
		24	* Authors: Dave Airlie
		25	* Alex Deucher
		26	* Jerome Glisse
		27	*/
		28	//#include
		29	#include "drmP.h"
		30	#include "radeon.h"
		31	#include "radeon_drm.h"
		32	#include "rv770d.h"
		33	#include "atom.h"
		34	#include "avivod.h"
		35
		36	#include
		37
		38
		39	#define R700_PFP_UCODE_SIZE 848
		40	#define R700_PM4_UCODE_SIZE 1360
		41
		42	static void rv770_gpu_init(struct radeon_device *rdev);
		43	void rv770_fini(struct radeon_device *rdev);
		44
		45
		46	/*
		47	* GART
		48	*/
		49	int rv770_pcie_gart_enable(struct radeon_device *rdev)
		50	{
		51	u32 tmp;
		52	int r, i;
		53
		54	if (rdev->gart.table.vram.robj == NULL) {
		55	dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
		56	return -EINVAL;
		57	}
		58	r = radeon_gart_table_vram_pin(rdev);
		59	if (r)
		60	return r;
		61	/* Setup L2 cache */
		62	WREG32(VM_L2_CNTL, ENABLE_L2_CACHE \| ENABLE_L2_FRAGMENT_PROCESSING \|
		63	ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE \|
		64	EFFECTIVE_L2_QUEUE_SIZE(7));
		65	WREG32(VM_L2_CNTL2, 0);
		66	WREG32(VM_L2_CNTL3, BANK_SELECT(0) \| CACHE_UPDATE_MODE(2));
		67	/* Setup TLB control */
		68	tmp = ENABLE_L1_TLB \| ENABLE_L1_FRAGMENT_PROCESSING \|
		69	SYSTEM_ACCESS_MODE_NOT_IN_SYS \|
		70	SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU \|
		71	EFFECTIVE_L1_TLB_SIZE(5) \| EFFECTIVE_L1_QUEUE_SIZE(5);
		72	WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
		73	WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
		74	WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
		75	WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
		76	WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
		77	WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
		78	WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
		79	WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
		80	WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
		81	WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
		82	WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT \| PAGE_TABLE_DEPTH(0) \|
		83	RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
		84	WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
		85	(u32)(rdev->dummy_page.addr >> 12));
		86	for (i = 1; i < 7; i++)
		87	WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
		88
		89	r600_pcie_gart_tlb_flush(rdev);
		90	rdev->gart.ready = true;
		91	return 0;
		92	}
		93
		94	void rv770_pcie_gart_disable(struct radeon_device *rdev)
		95	{
		96	u32 tmp;
		97	int i;
		98
		99	/* Disable all tables */
		100	for (i = 0; i < 7; i++)
		101	WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
		102
		103	/* Setup L2 cache */
		104	WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING \|
		105	EFFECTIVE_L2_QUEUE_SIZE(7));
		106	WREG32(VM_L2_CNTL2, 0);
		107	WREG32(VM_L2_CNTL3, BANK_SELECT(0) \| CACHE_UPDATE_MODE(2));
		108	/* Setup TLB control */
		109	tmp = EFFECTIVE_L1_TLB_SIZE(5) \| EFFECTIVE_L1_QUEUE_SIZE(5);
		110	WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
		111	WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
		112	WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
		113	WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
		114	WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
		115	WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
		116	WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
		117	if (rdev->gart.table.vram.robj) {
		118	// radeon_object_kunmap(rdev->gart.table.vram.robj);
		119	// radeon_object_unpin(rdev->gart.table.vram.robj);
		120	}
		121	}
		122
		123	void rv770_pcie_gart_fini(struct radeon_device *rdev)
		124	{
		125	rv770_pcie_gart_disable(rdev);
		126	// radeon_gart_table_vram_free(rdev);
		127	radeon_gart_fini(rdev);
		128	}
		129
		130
		131	void rv770_agp_enable(struct radeon_device *rdev)
		132	{
		133	u32 tmp;
		134	int i;
		135
		136	/* Setup L2 cache */
		137	WREG32(VM_L2_CNTL, ENABLE_L2_CACHE \| ENABLE_L2_FRAGMENT_PROCESSING \|
		138	ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE \|
		139	EFFECTIVE_L2_QUEUE_SIZE(7));
		140	WREG32(VM_L2_CNTL2, 0);
		141	WREG32(VM_L2_CNTL3, BANK_SELECT(0) \| CACHE_UPDATE_MODE(2));
		142	/* Setup TLB control */
		143	tmp = ENABLE_L1_TLB \| ENABLE_L1_FRAGMENT_PROCESSING \|
		144	SYSTEM_ACCESS_MODE_NOT_IN_SYS \|
		145	SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU \|
		146	EFFECTIVE_L1_TLB_SIZE(5) \| EFFECTIVE_L1_QUEUE_SIZE(5);
		147	WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
		148	WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
		149	WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
		150	WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
		151	WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
		152	WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
		153	WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
		154	for (i = 0; i < 7; i++)
		155	WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
		156	}
		157
		158	static void rv770_mc_program(struct radeon_device *rdev)
		159	{
		160	struct rv515_mc_save save;
		161	u32 tmp;
		162	int i, j;
		163
		164	/* Initialize HDP */
		165	for (i = 0, j = 0; i < 32; i++, j += 0x18) {
		166	WREG32((0x2c14 + j), 0x00000000);
		167	WREG32((0x2c18 + j), 0x00000000);
		168	WREG32((0x2c1c + j), 0x00000000);
		169	WREG32((0x2c20 + j), 0x00000000);
		170	WREG32((0x2c24 + j), 0x00000000);
		171	}
		172	WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
		173
		174	rv515_mc_stop(rdev, &save);
		175	if (r600_mc_wait_for_idle(rdev)) {
		176	dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
		177	}
		178	/* Lockout access through VGA aperture*/
		179	WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
		180	/* Update configuration */
		181	if (rdev->flags & RADEON_IS_AGP) {
		182	if (rdev->mc.vram_start < rdev->mc.gtt_start) {
		183	/* VRAM before AGP */
		184	WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
		185	rdev->mc.vram_start >> 12);
		186	WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
		187	rdev->mc.gtt_end >> 12);
		188	} else {
		189	/* VRAM after AGP */
		190	WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
		191	rdev->mc.gtt_start >> 12);
		192	WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
		193	rdev->mc.vram_end >> 12);
		194	}
		195	} else {
		196	WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
		197	rdev->mc.vram_start >> 12);
		198	WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
		199	rdev->mc.vram_end >> 12);
		200	}
		201	WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
		202	tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
		203	tmp \|= ((rdev->mc.vram_start >> 24) & 0xFFFF);
		204	WREG32(MC_VM_FB_LOCATION, tmp);
		205	WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
		206	WREG32(HDP_NONSURFACE_INFO, (2 << 7));
		207	WREG32(HDP_NONSURFACE_SIZE, (rdev->mc.mc_vram_size - 1) \| 0x3FF);
		208	if (rdev->flags & RADEON_IS_AGP) {
		209	WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);
		210	WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
		211	WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
		212	} else {
		213	WREG32(MC_VM_AGP_BASE, 0);
		214	WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
		215	WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
		216	}
		217	if (r600_mc_wait_for_idle(rdev)) {
		218	dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
		219	}
		220	rv515_mc_resume(rdev, &save);
		221	/* we need to own VRAM, so turn off the VGA renderer here
		222	* to stop it overwriting our objects */
		223	rv515_vga_render_disable(rdev);
		224	}
		225
		226
		227	/*
		228	* CP.
		229	*/
		230	void r700_cp_stop(struct radeon_device *rdev)
		231	{
		232	WREG32(CP_ME_CNTL, (CP_ME_HALT \| CP_PFP_HALT));
		233	}
		234
		235
		236	static int rv770_cp_load_microcode(struct radeon_device *rdev)
		237	{
		238	const __be32 *fw_data;
		239	int i;
		240
		241	if (!rdev->me_fw \|\| !rdev->pfp_fw)
		242	return -EINVAL;
		243
		244	r700_cp_stop(rdev);
		245	WREG32(CP_RB_CNTL, RB_NO_UPDATE \| (15 << 8) \| (3 << 0));
		246
		247	/* Reset cp */
		248	WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
		249	RREG32(GRBM_SOFT_RESET);
		250	mdelay(15);
		251	WREG32(GRBM_SOFT_RESET, 0);
		252
		253	fw_data = (const __be32 *)rdev->pfp_fw->data;
		254	WREG32(CP_PFP_UCODE_ADDR, 0);
		255	for (i = 0; i < R700_PFP_UCODE_SIZE; i++)
		256	WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
		257	WREG32(CP_PFP_UCODE_ADDR, 0);
		258
		259	fw_data = (const __be32 *)rdev->me_fw->data;
		260	WREG32(CP_ME_RAM_WADDR, 0);
		261	for (i = 0; i < R700_PM4_UCODE_SIZE; i++)
		262	WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
		263
		264	WREG32(CP_PFP_UCODE_ADDR, 0);
		265	WREG32(CP_ME_RAM_WADDR, 0);
		266	WREG32(CP_ME_RAM_RADDR, 0);
		267	return 0;
		268	}
		269
		270
		271	/*
		272	* Core functions
		273	*/
		274	static u32 r700_get_tile_pipe_to_backend_map(u32 num_tile_pipes,
		275	u32 num_backends,
		276	u32 backend_disable_mask)
		277	{
		278	u32 backend_map = 0;
		279	u32 enabled_backends_mask;
		280	u32 enabled_backends_count;
		281	u32 cur_pipe;
		282	u32 swizzle_pipe[R7XX_MAX_PIPES];
		283	u32 cur_backend;
		284	u32 i;
		285
		286	if (num_tile_pipes > R7XX_MAX_PIPES)
		287	num_tile_pipes = R7XX_MAX_PIPES;
		288	if (num_tile_pipes < 1)
		289	num_tile_pipes = 1;
		290	if (num_backends > R7XX_MAX_BACKENDS)
		291	num_backends = R7XX_MAX_BACKENDS;
		292	if (num_backends < 1)
		293	num_backends = 1;
		294
		295	enabled_backends_mask = 0;
		296	enabled_backends_count = 0;
		297	for (i = 0; i < R7XX_MAX_BACKENDS; ++i) {
		298	if (((backend_disable_mask >> i) & 1) == 0) {
		299	enabled_backends_mask \|= (1 << i);
		300	++enabled_backends_count;
		301	}
		302	if (enabled_backends_count == num_backends)
		303	break;
		304	}
		305
		306	if (enabled_backends_count == 0) {
		307	enabled_backends_mask = 1;
		308	enabled_backends_count = 1;
		309	}
		310
		311	if (enabled_backends_count != num_backends)
		312	num_backends = enabled_backends_count;
		313
		314	memset((uint8_t )&swizzle_pipe[0], 0, sizeof(u32) R7XX_MAX_PIPES);
		315	switch (num_tile_pipes) {
		316	case 1:
		317	swizzle_pipe[0] = 0;
		318	break;
		319	case 2:
		320	swizzle_pipe[0] = 0;
		321	swizzle_pipe[1] = 1;
		322	break;
		323	case 3:
		324	swizzle_pipe[0] = 0;
		325	swizzle_pipe[1] = 2;
		326	swizzle_pipe[2] = 1;
		327	break;
		328	case 4:
		329	swizzle_pipe[0] = 0;
		330	swizzle_pipe[1] = 2;
		331	swizzle_pipe[2] = 3;
		332	swizzle_pipe[3] = 1;
		333	break;
		334	case 5:
		335	swizzle_pipe[0] = 0;
		336	swizzle_pipe[1] = 2;
		337	swizzle_pipe[2] = 4;
		338	swizzle_pipe[3] = 1;
		339	swizzle_pipe[4] = 3;
		340	break;
		341	case 6:
		342	swizzle_pipe[0] = 0;
		343	swizzle_pipe[1] = 2;
		344	swizzle_pipe[2] = 4;
		345	swizzle_pipe[3] = 5;
		346	swizzle_pipe[4] = 3;
		347	swizzle_pipe[5] = 1;
		348	break;
		349	case 7:
		350	swizzle_pipe[0] = 0;
		351	swizzle_pipe[1] = 2;
		352	swizzle_pipe[2] = 4;
		353	swizzle_pipe[3] = 6;
		354	swizzle_pipe[4] = 3;
		355	swizzle_pipe[5] = 1;
		356	swizzle_pipe[6] = 5;
		357	break;
		358	case 8:
		359	swizzle_pipe[0] = 0;
		360	swizzle_pipe[1] = 2;
		361	swizzle_pipe[2] = 4;
		362	swizzle_pipe[3] = 6;
		363	swizzle_pipe[4] = 3;
		364	swizzle_pipe[5] = 1;
		365	swizzle_pipe[6] = 7;
		366	swizzle_pipe[7] = 5;
		367	break;
		368	}
		369
		370	cur_backend = 0;
		371	for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
		372	while (((1 << cur_backend) & enabled_backends_mask) == 0)
		373	cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;
		374
		375	backend_map \|= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
		376
		377	cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;
		378	}
		379
		380	return backend_map;
		381	}
		382
		383	static void rv770_gpu_init(struct radeon_device *rdev)
		384	{
		385	int i, j, num_qd_pipes;
		386	u32 sx_debug_1;
		387	u32 smx_dc_ctl0;
		388	u32 num_gs_verts_per_thread;
		389	u32 vgt_gs_per_es;
		390	u32 gs_prim_buffer_depth = 0;
		391	u32 sq_ms_fifo_sizes;
		392	u32 sq_config;
		393	u32 sq_thread_resource_mgmt;
		394	u32 hdp_host_path_cntl;
		395	u32 sq_dyn_gpr_size_simd_ab_0;
		396	u32 backend_map;
		397	u32 gb_tiling_config = 0;
		398	u32 cc_rb_backend_disable = 0;
		399	u32 cc_gc_shader_pipe_config = 0;
		400	u32 mc_arb_ramcfg;
		401	u32 db_debug4;
		402
		403	/* setup chip specs */
		404	switch (rdev->family) {
		405	case CHIP_RV770:
		406	rdev->config.rv770.max_pipes = 4;
		407	rdev->config.rv770.max_tile_pipes = 8;
		408	rdev->config.rv770.max_simds = 10;
		409	rdev->config.rv770.max_backends = 4;
		410	rdev->config.rv770.max_gprs = 256;
		411	rdev->config.rv770.max_threads = 248;
		412	rdev->config.rv770.max_stack_entries = 512;
		413	rdev->config.rv770.max_hw_contexts = 8;
		414	rdev->config.rv770.max_gs_threads = 16 * 2;
		415	rdev->config.rv770.sx_max_export_size = 128;
		416	rdev->config.rv770.sx_max_export_pos_size = 16;
		417	rdev->config.rv770.sx_max_export_smx_size = 112;
		418	rdev->config.rv770.sq_num_cf_insts = 2;
		419
		420	rdev->config.rv770.sx_num_of_sets = 7;
		421	rdev->config.rv770.sc_prim_fifo_size = 0xF9;
		422	rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
		423	rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
		424	break;
		425	case CHIP_RV730:
		426	rdev->config.rv770.max_pipes = 2;
		427	rdev->config.rv770.max_tile_pipes = 4;
		428	rdev->config.rv770.max_simds = 8;
		429	rdev->config.rv770.max_backends = 2;
		430	rdev->config.rv770.max_gprs = 128;
		431	rdev->config.rv770.max_threads = 248;
		432	rdev->config.rv770.max_stack_entries = 256;
		433	rdev->config.rv770.max_hw_contexts = 8;
		434	rdev->config.rv770.max_gs_threads = 16 * 2;
		435	rdev->config.rv770.sx_max_export_size = 256;
		436	rdev->config.rv770.sx_max_export_pos_size = 32;
		437	rdev->config.rv770.sx_max_export_smx_size = 224;
		438	rdev->config.rv770.sq_num_cf_insts = 2;
		439
		440	rdev->config.rv770.sx_num_of_sets = 7;
		441	rdev->config.rv770.sc_prim_fifo_size = 0xf9;
		442	rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
		443	rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
		444	if (rdev->config.rv770.sx_max_export_pos_size > 16) {
		445	rdev->config.rv770.sx_max_export_pos_size -= 16;
		446	rdev->config.rv770.sx_max_export_smx_size += 16;
		447	}
		448	break;
		449	case CHIP_RV710:
		450	rdev->config.rv770.max_pipes = 2;
		451	rdev->config.rv770.max_tile_pipes = 2;
		452	rdev->config.rv770.max_simds = 2;
		453	rdev->config.rv770.max_backends = 1;
		454	rdev->config.rv770.max_gprs = 256;
		455	rdev->config.rv770.max_threads = 192;
		456	rdev->config.rv770.max_stack_entries = 256;
		457	rdev->config.rv770.max_hw_contexts = 4;
		458	rdev->config.rv770.max_gs_threads = 8 * 2;
		459	rdev->config.rv770.sx_max_export_size = 128;
		460	rdev->config.rv770.sx_max_export_pos_size = 16;
		461	rdev->config.rv770.sx_max_export_smx_size = 112;
		462	rdev->config.rv770.sq_num_cf_insts = 1;
		463
		464	rdev->config.rv770.sx_num_of_sets = 7;
		465	rdev->config.rv770.sc_prim_fifo_size = 0x40;
		466	rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
		467	rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
		468	break;
		469	case CHIP_RV740:
		470	rdev->config.rv770.max_pipes = 4;
		471	rdev->config.rv770.max_tile_pipes = 4;
		472	rdev->config.rv770.max_simds = 8;
		473	rdev->config.rv770.max_backends = 4;
		474	rdev->config.rv770.max_gprs = 256;
		475	rdev->config.rv770.max_threads = 248;
		476	rdev->config.rv770.max_stack_entries = 512;
		477	rdev->config.rv770.max_hw_contexts = 8;
		478	rdev->config.rv770.max_gs_threads = 16 * 2;
		479	rdev->config.rv770.sx_max_export_size = 256;
		480	rdev->config.rv770.sx_max_export_pos_size = 32;
		481	rdev->config.rv770.sx_max_export_smx_size = 224;
		482	rdev->config.rv770.sq_num_cf_insts = 2;
		483
		484	rdev->config.rv770.sx_num_of_sets = 7;
		485	rdev->config.rv770.sc_prim_fifo_size = 0x100;
		486	rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
		487	rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
		488
		489	if (rdev->config.rv770.sx_max_export_pos_size > 16) {
		490	rdev->config.rv770.sx_max_export_pos_size -= 16;
		491	rdev->config.rv770.sx_max_export_smx_size += 16;
		492	}
		493	break;
		494	default:
		495	break;
		496	}
		497
		498	/* Initialize HDP */
		499	j = 0;
		500	for (i = 0; i < 32; i++) {
		501	WREG32((0x2c14 + j), 0x00000000);
		502	WREG32((0x2c18 + j), 0x00000000);
		503	WREG32((0x2c1c + j), 0x00000000);
		504	WREG32((0x2c20 + j), 0x00000000);
		505	WREG32((0x2c24 + j), 0x00000000);
		506	j += 0x18;
		507	}
		508
		509	WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
		510
		511	/* setup tiling, simd, pipe config */
		512	mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
		513
		514	switch (rdev->config.rv770.max_tile_pipes) {
		515	case 1:
		516	gb_tiling_config \|= PIPE_TILING(0);
		517	break;
		518	case 2:
		519	gb_tiling_config \|= PIPE_TILING(1);
		520	break;
		521	case 4:
		522	gb_tiling_config \|= PIPE_TILING(2);
		523	break;
		524	case 8:
		525	gb_tiling_config \|= PIPE_TILING(3);
		526	break;
		527	default:
		528	break;
		529	}
		530
		531	if (rdev->family == CHIP_RV770)
		532	gb_tiling_config \|= BANK_TILING(1);
		533	else
1268	serge	534	gb_tiling_config \|= BANK_TILING((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
1246	serge	535
		536	gb_tiling_config \|= GROUP_SIZE(0);
		537
1268	serge	538	if (((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT) > 3) {
1246	serge	539	gb_tiling_config \|= ROW_TILING(3);
		540	gb_tiling_config \|= SAMPLE_SPLIT(3);
		541	} else {
		542	gb_tiling_config \|=
		543	ROW_TILING(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT));
		544	gb_tiling_config \|=
		545	SAMPLE_SPLIT(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT));
		546	}
		547
		548	gb_tiling_config \|= BANK_SWAPS(1);
		549
		550	backend_map = r700_get_tile_pipe_to_backend_map(rdev->config.rv770.max_tile_pipes,
		551	rdev->config.rv770.max_backends,
		552	(0xff << rdev->config.rv770.max_backends) & 0xff);
		553	gb_tiling_config \|= BACKEND_MAP(backend_map);
		554
		555	cc_gc_shader_pipe_config =
		556	INACTIVE_QD_PIPES((R7XX_MAX_PIPES_MASK << rdev->config.rv770.max_pipes) & R7XX_MAX_PIPES_MASK);
		557	cc_gc_shader_pipe_config \|=
		558	INACTIVE_SIMDS((R7XX_MAX_SIMDS_MASK << rdev->config.rv770.max_simds) & R7XX_MAX_SIMDS_MASK);
		559
		560	cc_rb_backend_disable =
		561	BACKEND_DISABLE((R7XX_MAX_BACKENDS_MASK << rdev->config.rv770.max_backends) & R7XX_MAX_BACKENDS_MASK);
		562
		563	WREG32(GB_TILING_CONFIG, gb_tiling_config);
		564	WREG32(DCP_TILING_CONFIG, (gb_tiling_config & 0xffff));
		565	WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff));
		566
		567	WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
		568	WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
		569	WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
		570
		571	WREG32(CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable);
		572	WREG32(CGTS_SYS_TCC_DISABLE, 0);
		573	WREG32(CGTS_TCC_DISABLE, 0);
		574	WREG32(CGTS_USER_SYS_TCC_DISABLE, 0);
		575	WREG32(CGTS_USER_TCC_DISABLE, 0);
		576
		577	num_qd_pipes =
		578	R7XX_MAX_BACKENDS - r600_count_pipe_bits(cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK);
		579	WREG32(VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & DEALLOC_DIST_MASK);
		580	WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & VTX_REUSE_DEPTH_MASK);
		581
		582	/* set HW defaults for 3D engine */
		583	WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) \|
		584	ROQ_IB2_START(0x2b)));
		585
		586	WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30));
		587
		588	WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO \|
		589	SYNC_GRADIENT \|
		590	SYNC_WALKER \|
		591	SYNC_ALIGNER));
		592
		593	sx_debug_1 = RREG32(SX_DEBUG_1);
		594	sx_debug_1 \|= ENABLE_NEW_SMX_ADDRESS;
		595	WREG32(SX_DEBUG_1, sx_debug_1);
		596
		597	smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
		598	smx_dc_ctl0 &= ~CACHE_DEPTH(0x1ff);
		599	smx_dc_ctl0 \|= CACHE_DEPTH((rdev->config.rv770.sx_num_of_sets * 64) - 1);
		600	WREG32(SMX_DC_CTL0, smx_dc_ctl0);
		601
		602	WREG32(SMX_EVENT_CTL, (ES_FLUSH_CTL(4) \|
		603	GS_FLUSH_CTL(4) \|
		604	ACK_FLUSH_CTL(3) \|
		605	SYNC_FLUSH_CTL));
		606
		607	if (rdev->family == CHIP_RV770)
		608	WREG32(DB_DEBUG3, DB_CLK_OFF_DELAY(0x1f));
		609	else {
		610	db_debug4 = RREG32(DB_DEBUG4);
		611	db_debug4 \|= DISABLE_TILE_COVERED_FOR_PS_ITER;
		612	WREG32(DB_DEBUG4, db_debug4);
		613	}
		614
		615	WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.rv770.sx_max_export_size / 4) - 1) \|
		616	POSITION_BUFFER_SIZE((rdev->config.rv770.sx_max_export_pos_size / 4) - 1) \|
		617	SMX_BUFFER_SIZE((rdev->config.rv770.sx_max_export_smx_size / 4) - 1)));
		618
		619	WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.rv770.sc_prim_fifo_size) \|
		620	SC_HIZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_hiz_tile_fifo_size) \|
		621	SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_earlyz_tile_fifo_fize)));
		622
		623	WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
		624
		625	WREG32(VGT_NUM_INSTANCES, 1);
		626
		627	WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
		628
		629	WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
		630
		631	WREG32(CP_PERFMON_CNTL, 0);
		632
		633	sq_ms_fifo_sizes = (CACHE_FIFO_SIZE(16 * rdev->config.rv770.sq_num_cf_insts) \|
		634	DONE_FIFO_HIWATER(0xe0) \|
		635	ALU_UPDATE_FIFO_HIWATER(0x8));
		636	switch (rdev->family) {
		637	case CHIP_RV770:
		638	sq_ms_fifo_sizes \|= FETCH_FIFO_HIWATER(0x1);
		639	break;
		640	case CHIP_RV730:
		641	case CHIP_RV710:
		642	case CHIP_RV740:
		643	default:
		644	sq_ms_fifo_sizes \|= FETCH_FIFO_HIWATER(0x4);
		645	break;
		646	}
		647	WREG32(SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes);
		648
		649	/* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
		650	* should be adjusted as needed by the 2D/3D drivers. This just sets default values
		651	*/
		652	sq_config = RREG32(SQ_CONFIG);
		653	sq_config &= ~(PS_PRIO(3) \|
		654	VS_PRIO(3) \|
		655	GS_PRIO(3) \|
		656	ES_PRIO(3));
		657	sq_config \|= (DX9_CONSTS \|
		658	VC_ENABLE \|
		659	EXPORT_SRC_C \|
		660	PS_PRIO(0) \|
		661	VS_PRIO(1) \|
		662	GS_PRIO(2) \|
		663	ES_PRIO(3));
		664	if (rdev->family == CHIP_RV710)
		665	/* no vertex cache */
		666	sq_config &= ~VC_ENABLE;
		667
		668	WREG32(SQ_CONFIG, sq_config);
		669
		670	WREG32(SQ_GPR_RESOURCE_MGMT_1, (NUM_PS_GPRS((rdev->config.rv770.max_gprs * 24)/64) \|
		671	NUM_VS_GPRS((rdev->config.rv770.max_gprs * 24)/64) \|
		672	NUM_CLAUSE_TEMP_GPRS(((rdev->config.rv770.max_gprs * 24)/64)/2)));
		673
		674	WREG32(SQ_GPR_RESOURCE_MGMT_2, (NUM_GS_GPRS((rdev->config.rv770.max_gprs * 7)/64) \|
		675	NUM_ES_GPRS((rdev->config.rv770.max_gprs * 7)/64)));
		676
		677	sq_thread_resource_mgmt = (NUM_PS_THREADS((rdev->config.rv770.max_threads * 4)/8) \|
		678	NUM_VS_THREADS((rdev->config.rv770.max_threads * 2)/8) \|
		679	NUM_ES_THREADS((rdev->config.rv770.max_threads * 1)/8));
		680	if (((rdev->config.rv770.max_threads * 1) / 8) > rdev->config.rv770.max_gs_threads)
		681	sq_thread_resource_mgmt \|= NUM_GS_THREADS(rdev->config.rv770.max_gs_threads);
		682	else
		683	sq_thread_resource_mgmt \|= NUM_GS_THREADS((rdev->config.rv770.max_gs_threads * 1)/8);
		684	WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
		685
		686	WREG32(SQ_STACK_RESOURCE_MGMT_1, (NUM_PS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) \|
		687	NUM_VS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4)));
		688
		689	WREG32(SQ_STACK_RESOURCE_MGMT_2, (NUM_GS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) \|
		690	NUM_ES_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4)));
		691
		692	sq_dyn_gpr_size_simd_ab_0 = (SIMDA_RING0((rdev->config.rv770.max_gprs * 38)/64) \|
		693	SIMDA_RING1((rdev->config.rv770.max_gprs * 38)/64) \|
		694	SIMDB_RING0((rdev->config.rv770.max_gprs * 38)/64) \|
		695	SIMDB_RING1((rdev->config.rv770.max_gprs * 38)/64));
		696
		697	WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_0, sq_dyn_gpr_size_simd_ab_0);
		698	WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_1, sq_dyn_gpr_size_simd_ab_0);
		699	WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_2, sq_dyn_gpr_size_simd_ab_0);
		700	WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_3, sq_dyn_gpr_size_simd_ab_0);
		701	WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_4, sq_dyn_gpr_size_simd_ab_0);
		702	WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_5, sq_dyn_gpr_size_simd_ab_0);
		703	WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_6, sq_dyn_gpr_size_simd_ab_0);
		704	WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_7, sq_dyn_gpr_size_simd_ab_0);
		705
		706	WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) \|
		707	FORCE_EOV_MAX_REZ_CNT(255)));
		708
		709	if (rdev->family == CHIP_RV710)
		710	WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(TC_ONLY) \|
		711	AUTO_INVLD_EN(ES_AND_GS_AUTO)));
		712	else
		713	WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(VC_AND_TC) \|
		714	AUTO_INVLD_EN(ES_AND_GS_AUTO)));
		715
		716	switch (rdev->family) {
		717	case CHIP_RV770:
		718	case CHIP_RV730:
		719	case CHIP_RV740:
		720	gs_prim_buffer_depth = 384;
		721	break;
		722	case CHIP_RV710:
		723	gs_prim_buffer_depth = 128;
		724	break;
		725	default:
		726	break;
		727	}
		728
		729	num_gs_verts_per_thread = rdev->config.rv770.max_pipes * 16;
		730	vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread;
		731	/* Max value for this is 256 */
		732	if (vgt_gs_per_es > 256)
		733	vgt_gs_per_es = 256;
		734
		735	WREG32(VGT_ES_PER_GS, 128);
		736	WREG32(VGT_GS_PER_ES, vgt_gs_per_es);
		737	WREG32(VGT_GS_PER_VS, 2);
		738
		739	/* more default values. 2D/3D driver should adjust as needed */
		740	WREG32(VGT_GS_VERTEX_REUSE, 16);
		741	WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
		742	WREG32(VGT_STRMOUT_EN, 0);
		743	WREG32(SX_MISC, 0);
		744	WREG32(PA_SC_MODE_CNTL, 0);
		745	WREG32(PA_SC_EDGERULE, 0xaaaaaaaa);
		746	WREG32(PA_SC_AA_CONFIG, 0);
		747	WREG32(PA_SC_CLIPRECT_RULE, 0xffff);
		748	WREG32(PA_SC_LINE_STIPPLE, 0);
		749	WREG32(SPI_INPUT_Z, 0);
		750	WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
		751	WREG32(CB_COLOR7_FRAG, 0);
		752
		753	/* clear render buffer base addresses */
		754	WREG32(CB_COLOR0_BASE, 0);
		755	WREG32(CB_COLOR1_BASE, 0);
		756	WREG32(CB_COLOR2_BASE, 0);
		757	WREG32(CB_COLOR3_BASE, 0);
		758	WREG32(CB_COLOR4_BASE, 0);
		759	WREG32(CB_COLOR5_BASE, 0);
		760	WREG32(CB_COLOR6_BASE, 0);
		761	WREG32(CB_COLOR7_BASE, 0);
		762
		763	WREG32(TCP_CNTL, 0);
		764
		765	hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
		766	WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
		767
		768	WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
		769
		770	WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA \|
		771	NUM_CLIP_SEQ(3)));
		772
		773	}
		774
		775	int rv770_mc_init(struct radeon_device *rdev)
		776	{
		777	fixed20_12 a;
		778	u32 tmp;
1268	serge	779	int chansize, numchan;
1246	serge	780	int r;
		781
		782	/* Get VRAM informations */
		783	rdev->mc.vram_is_ddr = true;
1268	serge	784	tmp = RREG32(MC_ARB_RAMCFG);
		785	if (tmp & CHANSIZE_OVERRIDE) {
		786	chansize = 16;
		787	} else if (tmp & CHANSIZE_MASK) {
		788	chansize = 64;
		789	} else {
		790	chansize = 32;
		791	}
		792	tmp = RREG32(MC_SHARED_CHMAP);
		793	switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
		794	case 0:
		795	default:
		796	numchan = 1;
		797	break;
		798	case 1:
		799	numchan = 2;
		800	break;
		801	case 2:
		802	numchan = 4;
		803	break;
		804	case 3:
		805	numchan = 8;
		806	break;
		807	}
		808	rdev->mc.vram_width = numchan * chansize;
1246	serge	809	/* Could aper size report 0 ? */
		810	rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
		811	rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
		812	/* Setup GPU memory space */
		813	rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
		814	rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
		815
		816	if (rdev->mc.mc_vram_size > rdev->mc.aper_size)
		817	rdev->mc.mc_vram_size = rdev->mc.aper_size;
		818
		819	if (rdev->mc.real_vram_size > rdev->mc.aper_size)
		820	rdev->mc.real_vram_size = rdev->mc.aper_size;
		821
		822	if (rdev->flags & RADEON_IS_AGP) {
		823	r = radeon_agp_init(rdev);
		824	if (r)
		825	return r;
		826	/* gtt_size is setup by radeon_agp_init */
		827	rdev->mc.gtt_location = rdev->mc.agp_base;
		828	tmp = 0xFFFFFFFFUL - rdev->mc.agp_base - rdev->mc.gtt_size;
		829	/* Try to put vram before or after AGP because we
		830	* we want SYSTEM_APERTURE to cover both VRAM and
		831	* AGP so that GPU can catch out of VRAM/AGP access
		832	*/
		833	if (rdev->mc.gtt_location > rdev->mc.mc_vram_size) {
1313	serge	834	/* Enough place before */
1246	serge	835	rdev->mc.vram_location = rdev->mc.gtt_location -
		836	rdev->mc.mc_vram_size;
		837	} else if (tmp > rdev->mc.mc_vram_size) {
1313	serge	838	/* Enough place after */
1246	serge	839	rdev->mc.vram_location = rdev->mc.gtt_location +
		840	rdev->mc.gtt_size;
		841	} else {
		842	/* Try to setup VRAM then AGP might not
		843	* not work on some card
		844	*/
		845	rdev->mc.vram_location = 0x00000000UL;
		846	rdev->mc.gtt_location = rdev->mc.mc_vram_size;
		847	}
		848	} else {
		849	rdev->mc.vram_location = 0x00000000UL;
		850	rdev->mc.gtt_location = rdev->mc.mc_vram_size;
		851	rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
		852	}
		853	rdev->mc.vram_start = rdev->mc.vram_location;
		854	rdev->mc.vram_end = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1;
		855	rdev->mc.gtt_start = rdev->mc.gtt_location;
		856	rdev->mc.gtt_end = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
		857	/* FIXME: we should enforce default clock in case GPU is not in
		858	* default setup
		859	*/
		860	a.full = rfixed_const(100);
		861	rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk);
		862	rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a);
		863	return 0;
		864	}
		865	int rv770_gpu_reset(struct radeon_device *rdev)
		866	{
		867	/* FIXME: implement any rv770 specific bits */
		868	return r600_gpu_reset(rdev);
		869	}
		870
		871	static int rv770_startup(struct radeon_device *rdev)
		872	{
		873	int r;
		874
		875	rv770_mc_program(rdev);
		876	if (rdev->flags & RADEON_IS_AGP) {
		877	rv770_agp_enable(rdev);
		878	} else {
		879	r = rv770_pcie_gart_enable(rdev);
		880	if (r)
		881	return r;
		882	}
		883	rv770_gpu_init(rdev);
		884
		885	// r = radeon_object_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
		886	// &rdev->r600_blit.shader_gpu_addr);
		887	// if (r) {
		888	// DRM_ERROR("failed to pin blit object %d\n", r);
		889	// return r;
		890	// }
		891
		892	// r = radeon_ring_init(rdev, rdev->cp.ring_size);
		893	// if (r)
		894	// return r;
		895	// r = rv770_cp_load_microcode(rdev);
		896	// if (r)
		897	// return r;
		898	// r = r600_cp_resume(rdev);
		899	// if (r)
		900	// return r;
		901	/* write back buffer are not vital so don't worry about failure */
		902	// r600_wb_enable(rdev);
		903	return 0;
		904	}
		905
		906
		907	/* Plan is to move initialization in that function and use
		908	* helper function so that radeon_device_init pretty much
		909	* do nothing more than calling asic specific function. This
		910	* should also allow to remove a bunch of callback function
		911	* like vram_info.
		912	*/
		913	int rv770_init(struct radeon_device *rdev)
		914	{
		915	int r;
		916
		917	r = radeon_dummy_page_init(rdev);
		918	if (r)
		919	return r;
		920	/* This don't do much */
		921	r = radeon_gem_init(rdev);
		922	if (r)
		923	return r;
		924	/* Read BIOS */
		925	if (!radeon_get_bios(rdev)) {
		926	if (ASIC_IS_AVIVO(rdev))
		927	return -EINVAL;
		928	}
		929	/* Must be an ATOMBIOS */
		930	if (!rdev->is_atom_bios) {
		931	dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
		932	return -EINVAL;
		933	}
		934	r = radeon_atombios_init(rdev);
		935	if (r)
		936	return r;
		937	/* Post card if necessary */
		938	if (!r600_card_posted(rdev) && rdev->bios) {
		939	DRM_INFO("GPU not posted. posting now...\n");
		940	atom_asic_init(rdev->mode_info.atom_context);
		941	}
		942	/* Initialize scratch registers */
		943	r600_scratch_init(rdev);
		944	/* Initialize surface registers */
		945	radeon_surface_init(rdev);
1268	serge	946	/* Initialize clocks */
1246	serge	947	radeon_get_clock_info(rdev->ddev);
		948	r = radeon_clocks_init(rdev);
		949	if (r)
		950	return r;
1268	serge	951	/* Initialize power management */
		952	radeon_pm_init(rdev);
1246	serge	953	/* Fence driver */
		954	// r = radeon_fence_driver_init(rdev);
		955	// if (r)
		956	// return r;
		957	r = rv770_mc_init(rdev);
		958	if (r)
		959	return r;
		960	/* Memory manager */
		961	r = radeon_object_init(rdev);
		962	if (r)
		963	return r;
		964	// rdev->cp.ring_obj = NULL;
		965	// r600_ring_init(rdev, 1024 * 1024);
		966
		967	// if (!rdev->me_fw \|\| !rdev->pfp_fw) {
		968	// r = r600_cp_init_microcode(rdev);
		969	// if (r) {
		970	// DRM_ERROR("Failed to load firmware!\n");
		971	// return r;
		972	// }
		973	// }
		974
		975	r = r600_pcie_gart_init(rdev);
		976	if (r)
		977	return r;
		978
		979	rdev->accel_working = true;
		980	// r = r600_blit_init(rdev);
		981	// if (r) {
		982	// DRM_ERROR("radeon: failled blitter (%d).\n", r);
		983	// rdev->accel_working = false;
		984	// }
		985
		986	r = rv770_startup(rdev);
		987	if (r) {
		988	// rv770_suspend(rdev);
		989	// r600_wb_fini(rdev);
		990	// radeon_ring_fini(rdev);
		991	rv770_pcie_gart_fini(rdev);
		992	rdev->accel_working = false;
		993	}
		994	if (rdev->accel_working) {
		995	// r = radeon_ib_pool_init(rdev);
		996	// if (r) {
		997	// DRM_ERROR("radeon: failled initializing IB pool (%d).\n", r);
		998	// rdev->accel_working = false;
		999	// }
		1000	// r = r600_ib_test(rdev);
		1001	// if (r) {
		1002	// DRM_ERROR("radeon: failled testing IB (%d).\n", r);
		1003	// rdev->accel_working = false;
		1004	// }
		1005	}
		1006	return 0;
		1007	}
		1008

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(root)/drivers/video/drm/radeon/rv770.c – Rev 1313