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| Rev | Author | Line No. | Line |
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| 5078 | serge | 1 | /* |
| 2 | * Copyright 2011 Advanced Micro Devices, Inc. |
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| 3 | * |
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| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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| 5 | * copy of this software and associated documentation files (the "Software"), |
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| 6 | * to deal in the Software without restriction, including without limitation |
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| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
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| 9 | * Software is furnished to do so, subject to the following conditions: |
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| 10 | * |
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| 11 | * The above copyright notice and this permission notice shall be included in |
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| 12 | * all copies or substantial portions of the Software. |
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| 13 | * |
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| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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| 20 | * OTHER DEALINGS IN THE SOFTWARE. |
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| 21 | * |
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| 22 | */ |
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| 23 | #ifndef RV730_H |
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| 24 | #define RV730_H |
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| 25 | |||
| 26 | #define CG_SPLL_FUNC_CNTL 0x600 |
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| 27 | #define SPLL_RESET (1 << 0) |
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| 28 | #define SPLL_SLEEP (1 << 1) |
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| 29 | #define SPLL_DIVEN (1 << 2) |
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| 30 | #define SPLL_BYPASS_EN (1 << 3) |
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| 31 | #define SPLL_REF_DIV(x) ((x) << 4) |
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| 32 | #define SPLL_REF_DIV_MASK (0x3f << 4) |
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| 33 | #define SPLL_HILEN(x) ((x) << 12) |
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| 34 | #define SPLL_HILEN_MASK (0xf << 12) |
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| 35 | #define SPLL_LOLEN(x) ((x) << 16) |
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| 36 | #define SPLL_LOLEN_MASK (0xf << 16) |
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| 37 | #define CG_SPLL_FUNC_CNTL_2 0x604 |
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| 38 | #define SCLK_MUX_SEL(x) ((x) << 0) |
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| 39 | #define SCLK_MUX_SEL_MASK (0x1ff << 0) |
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| 40 | #define CG_SPLL_FUNC_CNTL_3 0x608 |
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| 41 | #define SPLL_FB_DIV(x) ((x) << 0) |
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| 42 | #define SPLL_FB_DIV_MASK (0x3ffffff << 0) |
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| 43 | #define SPLL_DITHEN (1 << 28) |
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| 44 | |||
| 45 | #define CG_MPLL_FUNC_CNTL 0x624 |
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| 46 | #define MPLL_RESET (1 << 0) |
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| 47 | #define MPLL_SLEEP (1 << 1) |
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| 48 | #define MPLL_DIVEN (1 << 2) |
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| 49 | #define MPLL_BYPASS_EN (1 << 3) |
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| 50 | #define MPLL_REF_DIV(x) ((x) << 4) |
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| 51 | #define MPLL_REF_DIV_MASK (0x3f << 4) |
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| 52 | #define MPLL_HILEN(x) ((x) << 12) |
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| 53 | #define MPLL_HILEN_MASK (0xf << 12) |
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| 54 | #define MPLL_LOLEN(x) ((x) << 16) |
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| 55 | #define MPLL_LOLEN_MASK (0xf << 16) |
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| 56 | #define CG_MPLL_FUNC_CNTL_2 0x628 |
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| 57 | #define MCLK_MUX_SEL(x) ((x) << 0) |
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| 58 | #define MCLK_MUX_SEL_MASK (0x1ff << 0) |
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| 59 | #define CG_MPLL_FUNC_CNTL_3 0x62c |
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| 60 | #define MPLL_FB_DIV(x) ((x) << 0) |
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| 61 | #define MPLL_FB_DIV_MASK (0x3ffffff << 0) |
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| 62 | #define MPLL_DITHEN (1 << 28) |
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| 63 | |||
| 64 | #define CG_TCI_MPLL_SPREAD_SPECTRUM 0x634 |
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| 65 | #define CG_TCI_MPLL_SPREAD_SPECTRUM_2 0x638 |
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| 66 | #define GENERAL_PWRMGT 0x63c |
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| 67 | # define GLOBAL_PWRMGT_EN (1 << 0) |
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| 68 | # define STATIC_PM_EN (1 << 1) |
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| 69 | # define THERMAL_PROTECTION_DIS (1 << 2) |
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| 70 | # define THERMAL_PROTECTION_TYPE (1 << 3) |
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| 71 | # define ENABLE_GEN2PCIE (1 << 4) |
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| 72 | # define ENABLE_GEN2XSP (1 << 5) |
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| 73 | # define SW_SMIO_INDEX(x) ((x) << 6) |
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| 74 | # define SW_SMIO_INDEX_MASK (3 << 6) |
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| 75 | # define LOW_VOLT_D2_ACPI (1 << 8) |
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| 76 | # define LOW_VOLT_D3_ACPI (1 << 9) |
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| 77 | # define VOLT_PWRMGT_EN (1 << 10) |
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| 78 | # define BACKBIAS_PAD_EN (1 << 18) |
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| 79 | # define BACKBIAS_VALUE (1 << 19) |
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| 80 | # define DYN_SPREAD_SPECTRUM_EN (1 << 23) |
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| 81 | # define AC_DC_SW (1 << 24) |
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| 82 | |||
| 83 | #define SCLK_PWRMGT_CNTL 0x644 |
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| 84 | # define SCLK_PWRMGT_OFF (1 << 0) |
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| 85 | # define SCLK_LOW_D1 (1 << 1) |
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| 86 | # define FIR_RESET (1 << 4) |
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| 87 | # define FIR_FORCE_TREND_SEL (1 << 5) |
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| 88 | # define FIR_TREND_MODE (1 << 6) |
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| 89 | # define DYN_GFX_CLK_OFF_EN (1 << 7) |
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| 90 | # define GFX_CLK_FORCE_ON (1 << 8) |
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| 91 | # define GFX_CLK_REQUEST_OFF (1 << 9) |
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| 92 | # define GFX_CLK_FORCE_OFF (1 << 10) |
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| 93 | # define GFX_CLK_OFF_ACPI_D1 (1 << 11) |
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| 94 | # define GFX_CLK_OFF_ACPI_D2 (1 << 12) |
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| 95 | # define GFX_CLK_OFF_ACPI_D3 (1 << 13) |
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| 96 | |||
| 97 | #define TCI_MCLK_PWRMGT_CNTL 0x648 |
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| 98 | # define MPLL_PWRMGT_OFF (1 << 5) |
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| 99 | # define DLL_READY (1 << 6) |
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| 100 | # define MC_INT_CNTL (1 << 7) |
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| 101 | # define MRDCKA_SLEEP (1 << 8) |
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| 102 | # define MRDCKB_SLEEP (1 << 9) |
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| 103 | # define MRDCKC_SLEEP (1 << 10) |
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| 104 | # define MRDCKD_SLEEP (1 << 11) |
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| 105 | # define MRDCKE_SLEEP (1 << 12) |
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| 106 | # define MRDCKF_SLEEP (1 << 13) |
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| 107 | # define MRDCKG_SLEEP (1 << 14) |
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| 108 | # define MRDCKH_SLEEP (1 << 15) |
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| 109 | # define MRDCKA_RESET (1 << 16) |
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| 110 | # define MRDCKB_RESET (1 << 17) |
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| 111 | # define MRDCKC_RESET (1 << 18) |
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| 112 | # define MRDCKD_RESET (1 << 19) |
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| 113 | # define MRDCKE_RESET (1 << 20) |
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| 114 | # define MRDCKF_RESET (1 << 21) |
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| 115 | # define MRDCKG_RESET (1 << 22) |
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| 116 | # define MRDCKH_RESET (1 << 23) |
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| 117 | # define DLL_READY_READ (1 << 24) |
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| 118 | # define USE_DISPLAY_GAP (1 << 25) |
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| 119 | # define USE_DISPLAY_URGENT_NORMAL (1 << 26) |
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| 120 | # define MPLL_TURNOFF_D2 (1 << 28) |
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| 121 | #define TCI_DLL_CNTL 0x64c |
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| 122 | |||
| 123 | #define CG_PG_CNTL 0x858 |
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| 124 | # define PWRGATE_ENABLE (1 << 0) |
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| 125 | |||
| 126 | #define CG_AT 0x6d4 |
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| 127 | #define CG_R(x) ((x) << 0) |
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| 128 | #define CG_R_MASK (0xffff << 0) |
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| 129 | #define CG_L(x) ((x) << 16) |
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| 130 | #define CG_L_MASK (0xffff << 16) |
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| 131 | |||
| 132 | #define CG_SPLL_SPREAD_SPECTRUM 0x790 |
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| 133 | #define SSEN (1 << 0) |
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| 134 | #define CLK_S(x) ((x) << 4) |
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| 135 | #define CLK_S_MASK (0xfff << 4) |
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| 136 | #define CG_SPLL_SPREAD_SPECTRUM_2 0x794 |
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| 137 | #define CLK_V(x) ((x) << 0) |
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| 138 | #define CLK_V_MASK (0x3ffffff << 0) |
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| 139 | |||
| 140 | #define MC_ARB_DRAM_TIMING 0x2774 |
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| 141 | #define MC_ARB_DRAM_TIMING2 0x2778 |
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| 142 | |||
| 143 | #define MC_ARB_RFSH_RATE 0x27b0 |
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| 144 | #define POWERMODE0(x) ((x) << 0) |
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| 145 | #define POWERMODE0_MASK (0xff << 0) |
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| 146 | #define POWERMODE1(x) ((x) << 8) |
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| 147 | #define POWERMODE1_MASK (0xff << 8) |
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| 148 | #define POWERMODE2(x) ((x) << 16) |
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| 149 | #define POWERMODE2_MASK (0xff << 16) |
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| 150 | #define POWERMODE3(x) ((x) << 24) |
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| 151 | #define POWERMODE3_MASK (0xff << 24) |
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| 152 | |||
| 153 | #define MC_ARB_DRAM_TIMING_1 0x27f0 |
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| 154 | #define MC_ARB_DRAM_TIMING_2 0x27f4 |
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| 155 | #define MC_ARB_DRAM_TIMING_3 0x27f8 |
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| 156 | #define MC_ARB_DRAM_TIMING2_1 0x27fc |
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| 157 | #define MC_ARB_DRAM_TIMING2_2 0x2800 |
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| 158 | #define MC_ARB_DRAM_TIMING2_3 0x2804 |
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| 159 | |||
| 160 | #define MC4_IO_DQ_PAD_CNTL_D0_I0 0x2978 |
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| 161 | #define MC4_IO_DQ_PAD_CNTL_D0_I1 0x297c |
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| 162 | #define MC4_IO_QS_PAD_CNTL_D0_I0 0x2980 |
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| 163 | #define MC4_IO_QS_PAD_CNTL_D0_I1 0x2984 |
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| 164 | |||
| 165 | #endif |