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5078 | serge | 1 | /* |
2 | * Copyright 2011 Advanced Micro Devices, Inc. |
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3 | * |
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4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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5 | * copy of this software and associated documentation files (the "Software"), |
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6 | * to deal in the Software without restriction, including without limitation |
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7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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8 | * and/or sell copies of the Software, and to permit persons to whom the |
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9 | * Software is furnished to do so, subject to the following conditions: |
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10 | * |
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11 | * The above copyright notice and this permission notice shall be included in |
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12 | * all copies or substantial portions of the Software. |
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13 | * |
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14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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20 | * OTHER DEALINGS IN THE SOFTWARE. |
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21 | * |
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22 | * Authors: Alex Deucher |
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23 | */ |
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24 | |||
25 | #include "drmP.h" |
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26 | #include "radeon.h" |
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27 | #include "rv730d.h" |
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28 | #include "r600_dpm.h" |
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29 | #include "rv770_dpm.h" |
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30 | #include "atom.h" |
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31 | |||
32 | #define MC_CG_ARB_FREQ_F0 0x0a |
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33 | #define MC_CG_ARB_FREQ_F1 0x0b |
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34 | #define MC_CG_ARB_FREQ_F2 0x0c |
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35 | #define MC_CG_ARB_FREQ_F3 0x0d |
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36 | |||
37 | struct rv7xx_ps *rv770_get_ps(struct radeon_ps *rps); |
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38 | struct rv7xx_power_info *rv770_get_pi(struct radeon_device *rdev); |
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39 | |||
40 | int rv730_populate_sclk_value(struct radeon_device *rdev, |
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41 | u32 engine_clock, |
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42 | RV770_SMC_SCLK_VALUE *sclk) |
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43 | { |
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44 | struct rv7xx_power_info *pi = rv770_get_pi(rdev); |
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45 | struct atom_clock_dividers dividers; |
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46 | u32 spll_func_cntl = pi->clk_regs.rv730.cg_spll_func_cntl; |
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47 | u32 spll_func_cntl_2 = pi->clk_regs.rv730.cg_spll_func_cntl_2; |
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48 | u32 spll_func_cntl_3 = pi->clk_regs.rv730.cg_spll_func_cntl_3; |
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49 | u32 cg_spll_spread_spectrum = pi->clk_regs.rv730.cg_spll_spread_spectrum; |
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50 | u32 cg_spll_spread_spectrum_2 = pi->clk_regs.rv730.cg_spll_spread_spectrum_2; |
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51 | u64 tmp; |
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52 | u32 reference_clock = rdev->clock.spll.reference_freq; |
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53 | u32 reference_divider, post_divider; |
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54 | u32 fbdiv; |
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55 | int ret; |
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56 | |||
57 | ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, |
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58 | engine_clock, false, ÷rs); |
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59 | if (ret) |
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60 | return ret; |
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61 | |||
62 | reference_divider = 1 + dividers.ref_div; |
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63 | |||
64 | if (dividers.enable_post_div) |
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65 | post_divider = ((dividers.post_div >> 4) & 0xf) + |
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66 | (dividers.post_div & 0xf) + 2; |
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67 | else |
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68 | post_divider = 1; |
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69 | |||
70 | tmp = (u64) engine_clock * reference_divider * post_divider * 16384; |
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71 | do_div(tmp, reference_clock); |
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72 | fbdiv = (u32) tmp; |
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73 | |||
74 | /* set up registers */ |
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75 | if (dividers.enable_post_div) |
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76 | spll_func_cntl |= SPLL_DIVEN; |
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77 | else |
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78 | spll_func_cntl &= ~SPLL_DIVEN; |
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79 | spll_func_cntl &= ~(SPLL_HILEN_MASK | SPLL_LOLEN_MASK | SPLL_REF_DIV_MASK); |
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80 | spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div); |
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81 | spll_func_cntl |= SPLL_HILEN((dividers.post_div >> 4) & 0xf); |
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82 | spll_func_cntl |= SPLL_LOLEN(dividers.post_div & 0xf); |
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83 | |||
84 | spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; |
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85 | spll_func_cntl_2 |= SCLK_MUX_SEL(2); |
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86 | |||
87 | spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK; |
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88 | spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv); |
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89 | spll_func_cntl_3 |= SPLL_DITHEN; |
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90 | |||
91 | if (pi->sclk_ss) { |
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92 | struct radeon_atom_ss ss; |
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93 | u32 vco_freq = engine_clock * post_divider; |
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94 | |||
95 | if (radeon_atombios_get_asic_ss_info(rdev, &ss, |
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96 | ASIC_INTERNAL_ENGINE_SS, vco_freq)) { |
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97 | u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); |
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98 | u32 clk_v = ss.percentage * fbdiv / (clk_s * 10000); |
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99 | |||
100 | cg_spll_spread_spectrum &= ~CLK_S_MASK; |
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101 | cg_spll_spread_spectrum |= CLK_S(clk_s); |
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102 | cg_spll_spread_spectrum |= SSEN; |
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103 | |||
104 | cg_spll_spread_spectrum_2 &= ~CLK_V_MASK; |
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105 | cg_spll_spread_spectrum_2 |= CLK_V(clk_v); |
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106 | } |
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107 | } |
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108 | |||
109 | sclk->sclk_value = cpu_to_be32(engine_clock); |
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110 | sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl); |
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111 | sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2); |
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112 | sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3); |
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113 | sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(cg_spll_spread_spectrum); |
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114 | sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(cg_spll_spread_spectrum_2); |
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115 | |||
116 | return 0; |
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117 | } |
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118 | |||
119 | int rv730_populate_mclk_value(struct radeon_device *rdev, |
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120 | u32 engine_clock, u32 memory_clock, |
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121 | LPRV7XX_SMC_MCLK_VALUE mclk) |
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122 | { |
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123 | struct rv7xx_power_info *pi = rv770_get_pi(rdev); |
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124 | u32 mclk_pwrmgt_cntl = pi->clk_regs.rv730.mclk_pwrmgt_cntl; |
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125 | u32 dll_cntl = pi->clk_regs.rv730.dll_cntl; |
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126 | u32 mpll_func_cntl = pi->clk_regs.rv730.mpll_func_cntl; |
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127 | u32 mpll_func_cntl_2 = pi->clk_regs.rv730.mpll_func_cntl2; |
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128 | u32 mpll_func_cntl_3 = pi->clk_regs.rv730.mpll_func_cntl3; |
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129 | u32 mpll_ss = pi->clk_regs.rv730.mpll_ss; |
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130 | u32 mpll_ss2 = pi->clk_regs.rv730.mpll_ss2; |
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131 | struct atom_clock_dividers dividers; |
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132 | u32 post_divider, reference_divider; |
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133 | int ret; |
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134 | |||
135 | ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_MEMORY_PLL_PARAM, |
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136 | memory_clock, false, ÷rs); |
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137 | if (ret) |
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138 | return ret; |
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139 | |||
140 | reference_divider = dividers.ref_div + 1; |
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141 | |||
142 | if (dividers.enable_post_div) |
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143 | post_divider = ((dividers.post_div >> 4) & 0xf) + |
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144 | (dividers.post_div & 0xf) + 2; |
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145 | else |
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146 | post_divider = 1; |
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147 | |||
148 | /* setup the registers */ |
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149 | if (dividers.enable_post_div) |
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150 | mpll_func_cntl |= MPLL_DIVEN; |
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151 | else |
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152 | mpll_func_cntl &= ~MPLL_DIVEN; |
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153 | |||
154 | mpll_func_cntl &= ~(MPLL_REF_DIV_MASK | MPLL_HILEN_MASK | MPLL_LOLEN_MASK); |
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155 | mpll_func_cntl |= MPLL_REF_DIV(dividers.ref_div); |
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156 | mpll_func_cntl |= MPLL_HILEN((dividers.post_div >> 4) & 0xf); |
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157 | mpll_func_cntl |= MPLL_LOLEN(dividers.post_div & 0xf); |
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158 | |||
159 | mpll_func_cntl_3 &= ~MPLL_FB_DIV_MASK; |
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160 | mpll_func_cntl_3 |= MPLL_FB_DIV(dividers.fb_div); |
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161 | if (dividers.enable_dithen) |
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162 | mpll_func_cntl_3 |= MPLL_DITHEN; |
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163 | else |
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164 | mpll_func_cntl_3 &= ~MPLL_DITHEN; |
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165 | |||
166 | if (pi->mclk_ss) { |
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167 | struct radeon_atom_ss ss; |
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168 | u32 vco_freq = memory_clock * post_divider; |
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169 | |||
170 | if (radeon_atombios_get_asic_ss_info(rdev, &ss, |
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171 | ASIC_INTERNAL_MEMORY_SS, vco_freq)) { |
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172 | u32 reference_clock = rdev->clock.mpll.reference_freq; |
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173 | u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); |
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174 | u32 clk_v = ss.percentage * dividers.fb_div / (clk_s * 10000); |
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175 | |||
176 | mpll_ss &= ~CLK_S_MASK; |
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177 | mpll_ss |= CLK_S(clk_s); |
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178 | mpll_ss |= SSEN; |
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179 | |||
180 | mpll_ss2 &= ~CLK_V_MASK; |
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181 | mpll_ss |= CLK_V(clk_v); |
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182 | } |
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183 | } |
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184 | |||
185 | |||
186 | mclk->mclk730.vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl); |
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187 | mclk->mclk730.vDLL_CNTL = cpu_to_be32(dll_cntl); |
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188 | mclk->mclk730.mclk_value = cpu_to_be32(memory_clock); |
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189 | mclk->mclk730.vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl); |
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190 | mclk->mclk730.vMPLL_FUNC_CNTL2 = cpu_to_be32(mpll_func_cntl_2); |
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191 | mclk->mclk730.vMPLL_FUNC_CNTL3 = cpu_to_be32(mpll_func_cntl_3); |
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192 | mclk->mclk730.vMPLL_SS = cpu_to_be32(mpll_ss); |
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193 | mclk->mclk730.vMPLL_SS2 = cpu_to_be32(mpll_ss2); |
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194 | |||
195 | return 0; |
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196 | } |
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197 | |||
198 | void rv730_read_clock_registers(struct radeon_device *rdev) |
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199 | { |
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200 | struct rv7xx_power_info *pi = rv770_get_pi(rdev); |
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201 | |||
202 | pi->clk_regs.rv730.cg_spll_func_cntl = |
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203 | RREG32(CG_SPLL_FUNC_CNTL); |
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204 | pi->clk_regs.rv730.cg_spll_func_cntl_2 = |
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205 | RREG32(CG_SPLL_FUNC_CNTL_2); |
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206 | pi->clk_regs.rv730.cg_spll_func_cntl_3 = |
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207 | RREG32(CG_SPLL_FUNC_CNTL_3); |
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208 | pi->clk_regs.rv730.cg_spll_spread_spectrum = |
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209 | RREG32(CG_SPLL_SPREAD_SPECTRUM); |
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210 | pi->clk_regs.rv730.cg_spll_spread_spectrum_2 = |
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211 | RREG32(CG_SPLL_SPREAD_SPECTRUM_2); |
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212 | |||
213 | pi->clk_regs.rv730.mclk_pwrmgt_cntl = |
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214 | RREG32(TCI_MCLK_PWRMGT_CNTL); |
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215 | pi->clk_regs.rv730.dll_cntl = |
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216 | RREG32(TCI_DLL_CNTL); |
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217 | pi->clk_regs.rv730.mpll_func_cntl = |
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218 | RREG32(CG_MPLL_FUNC_CNTL); |
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219 | pi->clk_regs.rv730.mpll_func_cntl2 = |
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220 | RREG32(CG_MPLL_FUNC_CNTL_2); |
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221 | pi->clk_regs.rv730.mpll_func_cntl3 = |
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222 | RREG32(CG_MPLL_FUNC_CNTL_3); |
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223 | pi->clk_regs.rv730.mpll_ss = |
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224 | RREG32(CG_TCI_MPLL_SPREAD_SPECTRUM); |
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225 | pi->clk_regs.rv730.mpll_ss2 = |
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226 | RREG32(CG_TCI_MPLL_SPREAD_SPECTRUM_2); |
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227 | } |
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228 | |||
229 | int rv730_populate_smc_acpi_state(struct radeon_device *rdev, |
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230 | RV770_SMC_STATETABLE *table) |
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231 | { |
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232 | struct rv7xx_power_info *pi = rv770_get_pi(rdev); |
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233 | u32 mpll_func_cntl = 0; |
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234 | u32 mpll_func_cntl_2 = 0 ; |
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235 | u32 mpll_func_cntl_3 = 0; |
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236 | u32 mclk_pwrmgt_cntl; |
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237 | u32 dll_cntl; |
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238 | u32 spll_func_cntl; |
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239 | u32 spll_func_cntl_2; |
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240 | u32 spll_func_cntl_3; |
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241 | |||
242 | table->ACPIState = table->initialState; |
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243 | table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC; |
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244 | |||
245 | if (pi->acpi_vddc) { |
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246 | rv770_populate_vddc_value(rdev, pi->acpi_vddc, |
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247 | &table->ACPIState.levels[0].vddc); |
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248 | table->ACPIState.levels[0].gen2PCIE = pi->pcie_gen2 ? |
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249 | pi->acpi_pcie_gen2 : 0; |
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250 | table->ACPIState.levels[0].gen2XSP = |
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251 | pi->acpi_pcie_gen2; |
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252 | } else { |
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253 | rv770_populate_vddc_value(rdev, pi->min_vddc_in_table, |
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254 | &table->ACPIState.levels[0].vddc); |
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255 | table->ACPIState.levels[0].gen2PCIE = 0; |
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256 | } |
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257 | |||
258 | mpll_func_cntl = pi->clk_regs.rv730.mpll_func_cntl; |
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259 | mpll_func_cntl_2 = pi->clk_regs.rv730.mpll_func_cntl2; |
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260 | mpll_func_cntl_3 = pi->clk_regs.rv730.mpll_func_cntl3; |
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261 | |||
262 | mpll_func_cntl |= MPLL_RESET | MPLL_BYPASS_EN; |
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263 | mpll_func_cntl &= ~MPLL_SLEEP; |
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264 | |||
265 | mpll_func_cntl_2 &= ~MCLK_MUX_SEL_MASK; |
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266 | mpll_func_cntl_2 |= MCLK_MUX_SEL(1); |
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267 | |||
268 | mclk_pwrmgt_cntl = (MRDCKA_RESET | |
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269 | MRDCKB_RESET | |
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270 | MRDCKC_RESET | |
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271 | MRDCKD_RESET | |
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272 | MRDCKE_RESET | |
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273 | MRDCKF_RESET | |
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274 | MRDCKG_RESET | |
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275 | MRDCKH_RESET | |
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276 | MRDCKA_SLEEP | |
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277 | MRDCKB_SLEEP | |
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278 | MRDCKC_SLEEP | |
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279 | MRDCKD_SLEEP | |
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280 | MRDCKE_SLEEP | |
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281 | MRDCKF_SLEEP | |
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282 | MRDCKG_SLEEP | |
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283 | MRDCKH_SLEEP); |
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284 | |||
285 | dll_cntl = 0xff000000; |
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286 | |||
287 | spll_func_cntl = pi->clk_regs.rv730.cg_spll_func_cntl; |
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288 | spll_func_cntl_2 = pi->clk_regs.rv730.cg_spll_func_cntl_2; |
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289 | spll_func_cntl_3 = pi->clk_regs.rv730.cg_spll_func_cntl_3; |
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290 | |||
291 | spll_func_cntl |= SPLL_RESET | SPLL_BYPASS_EN; |
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292 | spll_func_cntl &= ~SPLL_SLEEP; |
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293 | |||
294 | spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; |
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295 | spll_func_cntl_2 |= SCLK_MUX_SEL(4); |
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296 | |||
297 | table->ACPIState.levels[0].mclk.mclk730.vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl); |
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298 | table->ACPIState.levels[0].mclk.mclk730.vMPLL_FUNC_CNTL2 = cpu_to_be32(mpll_func_cntl_2); |
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299 | table->ACPIState.levels[0].mclk.mclk730.vMPLL_FUNC_CNTL3 = cpu_to_be32(mpll_func_cntl_3); |
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300 | table->ACPIState.levels[0].mclk.mclk730.vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl); |
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301 | table->ACPIState.levels[0].mclk.mclk730.vDLL_CNTL = cpu_to_be32(dll_cntl); |
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302 | |||
303 | table->ACPIState.levels[0].mclk.mclk730.mclk_value = 0; |
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304 | |||
305 | table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl); |
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306 | table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2); |
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307 | table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3); |
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308 | |||
309 | table->ACPIState.levels[0].sclk.sclk_value = 0; |
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310 | |||
311 | rv770_populate_mvdd_value(rdev, 0, &table->ACPIState.levels[0].mvdd); |
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312 | |||
313 | table->ACPIState.levels[1] = table->ACPIState.levels[0]; |
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314 | table->ACPIState.levels[2] = table->ACPIState.levels[0]; |
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315 | |||
316 | return 0; |
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317 | } |
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318 | |||
319 | int rv730_populate_smc_initial_state(struct radeon_device *rdev, |
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320 | struct radeon_ps *radeon_state, |
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321 | RV770_SMC_STATETABLE *table) |
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322 | { |
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323 | struct rv7xx_ps *initial_state = rv770_get_ps(radeon_state); |
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324 | struct rv7xx_power_info *pi = rv770_get_pi(rdev); |
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325 | u32 a_t; |
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326 | |||
327 | table->initialState.levels[0].mclk.mclk730.vMPLL_FUNC_CNTL = |
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328 | cpu_to_be32(pi->clk_regs.rv730.mpll_func_cntl); |
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329 | table->initialState.levels[0].mclk.mclk730.vMPLL_FUNC_CNTL2 = |
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330 | cpu_to_be32(pi->clk_regs.rv730.mpll_func_cntl2); |
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331 | table->initialState.levels[0].mclk.mclk730.vMPLL_FUNC_CNTL3 = |
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332 | cpu_to_be32(pi->clk_regs.rv730.mpll_func_cntl3); |
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333 | table->initialState.levels[0].mclk.mclk730.vMCLK_PWRMGT_CNTL = |
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334 | cpu_to_be32(pi->clk_regs.rv730.mclk_pwrmgt_cntl); |
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335 | table->initialState.levels[0].mclk.mclk730.vDLL_CNTL = |
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336 | cpu_to_be32(pi->clk_regs.rv730.dll_cntl); |
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337 | table->initialState.levels[0].mclk.mclk730.vMPLL_SS = |
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338 | cpu_to_be32(pi->clk_regs.rv730.mpll_ss); |
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339 | table->initialState.levels[0].mclk.mclk730.vMPLL_SS2 = |
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340 | cpu_to_be32(pi->clk_regs.rv730.mpll_ss2); |
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341 | |||
342 | table->initialState.levels[0].mclk.mclk730.mclk_value = |
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343 | cpu_to_be32(initial_state->low.mclk); |
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344 | |||
345 | table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = |
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346 | cpu_to_be32(pi->clk_regs.rv730.cg_spll_func_cntl); |
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347 | table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = |
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348 | cpu_to_be32(pi->clk_regs.rv730.cg_spll_func_cntl_2); |
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349 | table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = |
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350 | cpu_to_be32(pi->clk_regs.rv730.cg_spll_func_cntl_3); |
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351 | table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM = |
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352 | cpu_to_be32(pi->clk_regs.rv730.cg_spll_spread_spectrum); |
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353 | table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2 = |
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354 | cpu_to_be32(pi->clk_regs.rv730.cg_spll_spread_spectrum_2); |
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355 | |||
356 | table->initialState.levels[0].sclk.sclk_value = |
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357 | cpu_to_be32(initial_state->low.sclk); |
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358 | |||
359 | table->initialState.levels[0].arbValue = MC_CG_ARB_FREQ_F0; |
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360 | |||
361 | table->initialState.levels[0].seqValue = |
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362 | rv770_get_seq_value(rdev, &initial_state->low); |
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363 | |||
364 | rv770_populate_vddc_value(rdev, |
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365 | initial_state->low.vddc, |
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366 | &table->initialState.levels[0].vddc); |
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367 | rv770_populate_initial_mvdd_value(rdev, |
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368 | &table->initialState.levels[0].mvdd); |
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369 | |||
370 | a_t = CG_R(0xffff) | CG_L(0); |
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371 | |||
372 | table->initialState.levels[0].aT = cpu_to_be32(a_t); |
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373 | |||
374 | table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp); |
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375 | |||
376 | if (pi->boot_in_gen2) |
||
377 | table->initialState.levels[0].gen2PCIE = 1; |
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378 | else |
||
379 | table->initialState.levels[0].gen2PCIE = 0; |
||
380 | if (initial_state->low.flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2) |
||
381 | table->initialState.levels[0].gen2XSP = 1; |
||
382 | else |
||
383 | table->initialState.levels[0].gen2XSP = 0; |
||
384 | |||
385 | table->initialState.levels[1] = table->initialState.levels[0]; |
||
386 | table->initialState.levels[2] = table->initialState.levels[0]; |
||
387 | |||
388 | table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC; |
||
389 | |||
390 | return 0; |
||
391 | } |
||
392 | |||
393 | void rv730_program_memory_timing_parameters(struct radeon_device *rdev, |
||
394 | struct radeon_ps *radeon_state) |
||
395 | { |
||
396 | struct rv7xx_ps *state = rv770_get_ps(radeon_state); |
||
397 | u32 arb_refresh_rate = 0; |
||
398 | u32 dram_timing = 0; |
||
399 | u32 dram_timing2 = 0; |
||
400 | u32 old_dram_timing = 0; |
||
401 | u32 old_dram_timing2 = 0; |
||
402 | |||
403 | arb_refresh_rate = RREG32(MC_ARB_RFSH_RATE) & |
||
404 | ~(POWERMODE1_MASK | POWERMODE2_MASK | POWERMODE3_MASK); |
||
405 | arb_refresh_rate |= |
||
406 | (POWERMODE1(rv770_calculate_memory_refresh_rate(rdev, state->low.sclk)) | |
||
407 | POWERMODE2(rv770_calculate_memory_refresh_rate(rdev, state->medium.sclk)) | |
||
408 | POWERMODE3(rv770_calculate_memory_refresh_rate(rdev, state->high.sclk))); |
||
409 | WREG32(MC_ARB_RFSH_RATE, arb_refresh_rate); |
||
410 | |||
411 | /* save the boot dram timings */ |
||
412 | old_dram_timing = RREG32(MC_ARB_DRAM_TIMING); |
||
413 | old_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2); |
||
414 | |||
415 | radeon_atom_set_engine_dram_timings(rdev, |
||
416 | state->high.sclk, |
||
417 | state->high.mclk); |
||
418 | |||
419 | dram_timing = RREG32(MC_ARB_DRAM_TIMING); |
||
420 | dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2); |
||
421 | |||
422 | WREG32(MC_ARB_DRAM_TIMING_3, dram_timing); |
||
423 | WREG32(MC_ARB_DRAM_TIMING2_3, dram_timing2); |
||
424 | |||
425 | radeon_atom_set_engine_dram_timings(rdev, |
||
426 | state->medium.sclk, |
||
427 | state->medium.mclk); |
||
428 | |||
429 | dram_timing = RREG32(MC_ARB_DRAM_TIMING); |
||
430 | dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2); |
||
431 | |||
432 | WREG32(MC_ARB_DRAM_TIMING_2, dram_timing); |
||
433 | WREG32(MC_ARB_DRAM_TIMING2_2, dram_timing2); |
||
434 | |||
435 | radeon_atom_set_engine_dram_timings(rdev, |
||
436 | state->low.sclk, |
||
437 | state->low.mclk); |
||
438 | |||
439 | dram_timing = RREG32(MC_ARB_DRAM_TIMING); |
||
440 | dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2); |
||
441 | |||
442 | WREG32(MC_ARB_DRAM_TIMING_1, dram_timing); |
||
443 | WREG32(MC_ARB_DRAM_TIMING2_1, dram_timing2); |
||
444 | |||
445 | /* restore the boot dram timings */ |
||
446 | WREG32(MC_ARB_DRAM_TIMING, old_dram_timing); |
||
447 | WREG32(MC_ARB_DRAM_TIMING2, old_dram_timing2); |
||
448 | |||
449 | } |
||
450 | |||
451 | void rv730_start_dpm(struct radeon_device *rdev) |
||
452 | { |
||
453 | WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF); |
||
454 | |||
455 | WREG32_P(TCI_MCLK_PWRMGT_CNTL, 0, ~MPLL_PWRMGT_OFF); |
||
456 | |||
457 | WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN); |
||
458 | } |
||
459 | |||
460 | void rv730_stop_dpm(struct radeon_device *rdev) |
||
461 | { |
||
462 | PPSMC_Result result; |
||
463 | |||
464 | result = rv770_send_msg_to_smc(rdev, PPSMC_MSG_TwoLevelsDisabled); |
||
465 | |||
466 | if (result != PPSMC_Result_OK) |
||
6104 | serge | 467 | DRM_DEBUG("Could not force DPM to low\n"); |
5078 | serge | 468 | |
469 | WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN); |
||
470 | |||
471 | WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF); |
||
472 | |||
473 | WREG32_P(TCI_MCLK_PWRMGT_CNTL, MPLL_PWRMGT_OFF, ~MPLL_PWRMGT_OFF); |
||
474 | } |
||
475 | |||
476 | void rv730_program_dcodt(struct radeon_device *rdev, bool use_dcodt) |
||
477 | { |
||
478 | struct rv7xx_power_info *pi = rv770_get_pi(rdev); |
||
479 | u32 i = use_dcodt ? 0 : 1; |
||
480 | u32 mc4_io_pad_cntl; |
||
481 | |||
482 | mc4_io_pad_cntl = RREG32(MC4_IO_DQ_PAD_CNTL_D0_I0); |
||
483 | mc4_io_pad_cntl &= 0xFFFFFF00; |
||
484 | mc4_io_pad_cntl |= pi->odt_value_0[i]; |
||
485 | WREG32(MC4_IO_DQ_PAD_CNTL_D0_I0, mc4_io_pad_cntl); |
||
486 | WREG32(MC4_IO_DQ_PAD_CNTL_D0_I1, mc4_io_pad_cntl); |
||
487 | |||
488 | mc4_io_pad_cntl = RREG32(MC4_IO_QS_PAD_CNTL_D0_I0); |
||
489 | mc4_io_pad_cntl &= 0xFFFFFF00; |
||
490 | mc4_io_pad_cntl |= pi->odt_value_1[i]; |
||
491 | WREG32(MC4_IO_QS_PAD_CNTL_D0_I0, mc4_io_pad_cntl); |
||
492 | WREG32(MC4_IO_QS_PAD_CNTL_D0_I1, mc4_io_pad_cntl); |
||
493 | } |
||
494 | |||
495 | void rv730_get_odt_values(struct radeon_device *rdev) |
||
496 | { |
||
497 | struct rv7xx_power_info *pi = rv770_get_pi(rdev); |
||
498 | u32 mc4_io_pad_cntl; |
||
499 | |||
500 | pi->odt_value_0[0] = (u8)0; |
||
501 | pi->odt_value_1[0] = (u8)0x80; |
||
502 | |||
503 | mc4_io_pad_cntl = RREG32(MC4_IO_DQ_PAD_CNTL_D0_I0); |
||
504 | pi->odt_value_0[1] = (u8)(mc4_io_pad_cntl & 0xff); |
||
505 | |||
506 | mc4_io_pad_cntl = RREG32(MC4_IO_QS_PAD_CNTL_D0_I0); |
||
507 | pi->odt_value_1[1] = (u8)(mc4_io_pad_cntl & 0xff); |
||
508 | } |