Rev 1963 | Details | Compare with Previous | Last modification | View Log | RSS feed
| Rev | Author | Line No. | Line |
|---|---|---|---|
| 3764 | Serge | 1 | /* |
| 2 | * Copyright 2008 Advanced Micro Devices, Inc. |
||
| 3 | * Copyright 2008 Red Hat Inc. |
||
| 4 | * Copyright 2009 Jerome Glisse. |
||
| 5 | * |
||
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
||
| 7 | * copy of this software and associated documentation files (the "Software"), |
||
| 8 | * to deal in the Software without restriction, including without limitation |
||
| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
||
| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
||
| 11 | * Software is furnished to do so, subject to the following conditions: |
||
| 12 | * |
||
| 13 | * The above copyright notice and this permission notice shall be included in |
||
| 14 | * all copies or substantial portions of the Software. |
||
| 15 | * |
||
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
||
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
||
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
||
| 19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
||
| 20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
||
| 21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
||
| 22 | * OTHER DEALINGS IN THE SOFTWARE. |
||
| 23 | * |
||
| 24 | * Authors: Dave Airlie |
||
| 25 | * Alex Deucher |
||
| 26 | * Jerome Glisse |
||
| 27 | */ |
||
| 28 | #ifndef __RV515D_H__ |
||
| 29 | #define __RV515D_H__ |
||
| 30 | |||
| 31 | /* |
||
| 32 | * RV515 registers |
||
| 33 | */ |
||
| 34 | #define PCIE_INDEX 0x0030 |
||
| 35 | #define PCIE_DATA 0x0034 |
||
| 36 | #define MC_IND_INDEX 0x0070 |
||
| 37 | #define MC_IND_WR_EN (1 << 24) |
||
| 38 | #define MC_IND_DATA 0x0074 |
||
| 39 | #define RBBM_SOFT_RESET 0x00F0 |
||
| 40 | #define CONFIG_MEMSIZE 0x00F8 |
||
| 41 | #define HDP_FB_LOCATION 0x0134 |
||
| 42 | #define CP_CSQ_CNTL 0x0740 |
||
| 43 | #define CP_CSQ_MODE 0x0744 |
||
| 44 | #define CP_CSQ_ADDR 0x07F0 |
||
| 45 | #define CP_CSQ_DATA 0x07F4 |
||
| 46 | #define CP_CSQ_STAT 0x07F8 |
||
| 47 | #define CP_CSQ2_STAT 0x07FC |
||
| 48 | #define RBBM_STATUS 0x0E40 |
||
| 49 | #define DST_PIPE_CONFIG 0x170C |
||
| 50 | #define WAIT_UNTIL 0x1720 |
||
| 51 | #define WAIT_2D_IDLE (1 << 14) |
||
| 52 | #define WAIT_3D_IDLE (1 << 15) |
||
| 53 | #define WAIT_2D_IDLECLEAN (1 << 16) |
||
| 54 | #define WAIT_3D_IDLECLEAN (1 << 17) |
||
| 55 | #define ISYNC_CNTL 0x1724 |
||
| 56 | #define ISYNC_ANY2D_IDLE3D (1 << 0) |
||
| 57 | #define ISYNC_ANY3D_IDLE2D (1 << 1) |
||
| 58 | #define ISYNC_TRIG2D_IDLE3D (1 << 2) |
||
| 59 | #define ISYNC_TRIG3D_IDLE2D (1 << 3) |
||
| 60 | #define ISYNC_WAIT_IDLEGUI (1 << 4) |
||
| 61 | #define ISYNC_CPSCRATCH_IDLEGUI (1 << 5) |
||
| 62 | #define VAP_INDEX_OFFSET 0x208C |
||
| 63 | #define VAP_PVS_STATE_FLUSH_REG 0x2284 |
||
| 64 | #define GB_ENABLE 0x4008 |
||
| 65 | #define GB_MSPOS0 0x4010 |
||
| 66 | #define MS_X0_SHIFT 0 |
||
| 67 | #define MS_Y0_SHIFT 4 |
||
| 68 | #define MS_X1_SHIFT 8 |
||
| 69 | #define MS_Y1_SHIFT 12 |
||
| 70 | #define MS_X2_SHIFT 16 |
||
| 71 | #define MS_Y2_SHIFT 20 |
||
| 72 | #define MSBD0_Y_SHIFT 24 |
||
| 73 | #define MSBD0_X_SHIFT 28 |
||
| 74 | #define GB_MSPOS1 0x4014 |
||
| 75 | #define MS_X3_SHIFT 0 |
||
| 76 | #define MS_Y3_SHIFT 4 |
||
| 77 | #define MS_X4_SHIFT 8 |
||
| 78 | #define MS_Y4_SHIFT 12 |
||
| 79 | #define MS_X5_SHIFT 16 |
||
| 80 | #define MS_Y5_SHIFT 20 |
||
| 81 | #define MSBD1_SHIFT 24 |
||
| 82 | #define GB_TILE_CONFIG 0x4018 |
||
| 83 | #define ENABLE_TILING (1 << 0) |
||
| 84 | #define PIPE_COUNT_MASK 0x0000000E |
||
| 85 | #define PIPE_COUNT_SHIFT 1 |
||
| 86 | #define TILE_SIZE_8 (0 << 4) |
||
| 87 | #define TILE_SIZE_16 (1 << 4) |
||
| 88 | #define TILE_SIZE_32 (2 << 4) |
||
| 89 | #define SUBPIXEL_1_12 (0 << 16) |
||
| 90 | #define SUBPIXEL_1_16 (1 << 16) |
||
| 91 | #define GB_SELECT 0x401C |
||
| 92 | #define GB_AA_CONFIG 0x4020 |
||
| 93 | #define GB_PIPE_SELECT 0x402C |
||
| 94 | #define GA_ENHANCE 0x4274 |
||
| 95 | #define GA_DEADLOCK_CNTL (1 << 0) |
||
| 96 | #define GA_FASTSYNC_CNTL (1 << 1) |
||
| 97 | #define GA_POLY_MODE 0x4288 |
||
| 98 | #define FRONT_PTYPE_POINT (0 << 4) |
||
| 99 | #define FRONT_PTYPE_LINE (1 << 4) |
||
| 100 | #define FRONT_PTYPE_TRIANGE (2 << 4) |
||
| 101 | #define BACK_PTYPE_POINT (0 << 7) |
||
| 102 | #define BACK_PTYPE_LINE (1 << 7) |
||
| 103 | #define BACK_PTYPE_TRIANGE (2 << 7) |
||
| 104 | #define GA_ROUND_MODE 0x428C |
||
| 105 | #define GEOMETRY_ROUND_TRUNC (0 << 0) |
||
| 106 | #define GEOMETRY_ROUND_NEAREST (1 << 0) |
||
| 107 | #define COLOR_ROUND_TRUNC (0 << 2) |
||
| 108 | #define COLOR_ROUND_NEAREST (1 << 2) |
||
| 109 | #define SU_REG_DEST 0x42C8 |
||
| 110 | #define RB3D_DSTCACHE_CTLSTAT 0x4E4C |
||
| 111 | #define RB3D_DC_FLUSH (2 << 0) |
||
| 112 | #define RB3D_DC_FREE (2 << 2) |
||
| 113 | #define RB3D_DC_FINISH (1 << 4) |
||
| 114 | #define ZB_ZCACHE_CTLSTAT 0x4F18 |
||
| 115 | #define ZC_FLUSH (1 << 0) |
||
| 116 | #define ZC_FREE (1 << 1) |
||
| 117 | #define DC_LB_MEMORY_SPLIT 0x6520 |
||
| 118 | #define DC_LB_MEMORY_SPLIT_MASK 0x00000003 |
||
| 119 | #define DC_LB_MEMORY_SPLIT_SHIFT 0 |
||
| 120 | #define DC_LB_MEMORY_SPLIT_D1HALF_D2HALF 0 |
||
| 121 | #define DC_LB_MEMORY_SPLIT_D1_3Q_D2_1Q 1 |
||
| 122 | #define DC_LB_MEMORY_SPLIT_D1_ONLY 2 |
||
| 123 | #define DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q 3 |
||
| 124 | #define DC_LB_MEMORY_SPLIT_SHIFT_MODE (1 << 2) |
||
| 125 | #define DC_LB_DISP1_END_ADR_SHIFT 4 |
||
| 126 | #define DC_LB_DISP1_END_ADR_MASK 0x00007FF0 |
||
| 127 | #define D1MODE_PRIORITY_A_CNT 0x6548 |
||
| 128 | #define MODE_PRIORITY_MARK_MASK 0x00007FFF |
||
| 129 | #define MODE_PRIORITY_OFF (1 << 16) |
||
| 130 | #define MODE_PRIORITY_ALWAYS_ON (1 << 20) |
||
| 131 | #define MODE_PRIORITY_FORCE_MASK (1 << 24) |
||
| 132 | #define D1MODE_PRIORITY_B_CNT 0x654C |
||
| 133 | #define LB_MAX_REQ_OUTSTANDING 0x6D58 |
||
| 134 | #define LB_D1_MAX_REQ_OUTSTANDING_MASK 0x0000000F |
||
| 135 | #define LB_D1_MAX_REQ_OUTSTANDING_SHIFT 0 |
||
| 136 | #define LB_D2_MAX_REQ_OUTSTANDING_MASK 0x000F0000 |
||
| 137 | #define LB_D2_MAX_REQ_OUTSTANDING_SHIFT 16 |
||
| 138 | #define D2MODE_PRIORITY_A_CNT 0x6D48 |
||
| 139 | #define D2MODE_PRIORITY_B_CNT 0x6D4C |
||
| 140 | |||
| 141 | /* ix[MC] registers */ |
||
| 142 | #define MC_FB_LOCATION 0x01 |
||
| 143 | #define MC_FB_START_MASK 0x0000FFFF |
||
| 144 | #define MC_FB_START_SHIFT 0 |
||
| 145 | #define MC_FB_TOP_MASK 0xFFFF0000 |
||
| 146 | #define MC_FB_TOP_SHIFT 16 |
||
| 147 | #define MC_AGP_LOCATION 0x02 |
||
| 148 | #define MC_AGP_START_MASK 0x0000FFFF |
||
| 149 | #define MC_AGP_START_SHIFT 0 |
||
| 150 | #define MC_AGP_TOP_MASK 0xFFFF0000 |
||
| 151 | #define MC_AGP_TOP_SHIFT 16 |
||
| 152 | #define MC_AGP_BASE 0x03 |
||
| 153 | #define MC_AGP_BASE_2 0x04 |
||
| 154 | #define MC_CNTL 0x5 |
||
| 155 | #define MEM_NUM_CHANNELS_MASK 0x00000003 |
||
| 156 | #define MC_STATUS 0x08 |
||
| 157 | #define MC_STATUS_IDLE (1 << 4) |
||
| 158 | #define MC_MISC_LAT_TIMER 0x09 |
||
| 159 | #define MC_CPR_INIT_LAT_MASK 0x0000000F |
||
| 160 | #define MC_VF_INIT_LAT_MASK 0x000000F0 |
||
| 161 | #define MC_DISP0R_INIT_LAT_MASK 0x00000F00 |
||
| 162 | #define MC_DISP0R_INIT_LAT_SHIFT 8 |
||
| 163 | #define MC_DISP1R_INIT_LAT_MASK 0x0000F000 |
||
| 164 | #define MC_DISP1R_INIT_LAT_SHIFT 12 |
||
| 165 | #define MC_FIXED_INIT_LAT_MASK 0x000F0000 |
||
| 166 | #define MC_E2R_INIT_LAT_MASK 0x00F00000 |
||
| 167 | #define SAME_PAGE_PRIO_MASK 0x0F000000 |
||
| 168 | #define MC_GLOBW_INIT_LAT_MASK 0xF0000000 |
||
| 169 | |||
| 170 | |||
| 171 | /* |
||
| 172 | * PM4 packet |
||
| 173 | */ |
||
| 174 | #define CP_PACKET0 0x00000000 |
||
| 175 | #define PACKET0_BASE_INDEX_SHIFT 0 |
||
| 176 | #define PACKET0_BASE_INDEX_MASK (0x1ffff << 0) |
||
| 177 | #define PACKET0_COUNT_SHIFT 16 |
||
| 178 | #define PACKET0_COUNT_MASK (0x3fff << 16) |
||
| 179 | #define CP_PACKET1 0x40000000 |
||
| 180 | #define CP_PACKET2 0x80000000 |
||
| 181 | #define PACKET2_PAD_SHIFT 0 |
||
| 182 | #define PACKET2_PAD_MASK (0x3fffffff << 0) |
||
| 183 | #define CP_PACKET3 0xC0000000 |
||
| 184 | #define PACKET3_IT_OPCODE_SHIFT 8 |
||
| 185 | #define PACKET3_IT_OPCODE_MASK (0xff << 8) |
||
| 186 | #define PACKET3_COUNT_SHIFT 16 |
||
| 187 | #define PACKET3_COUNT_MASK (0x3fff << 16) |
||
| 188 | /* PACKET3 op code */ |
||
| 189 | #define PACKET3_NOP 0x10 |
||
| 190 | #define PACKET3_3D_DRAW_VBUF 0x28 |
||
| 191 | #define PACKET3_3D_DRAW_IMMD 0x29 |
||
| 192 | #define PACKET3_3D_DRAW_INDX 0x2A |
||
| 193 | #define PACKET3_3D_LOAD_VBPNTR 0x2F |
||
| 194 | #define PACKET3_INDX_BUFFER 0x33 |
||
| 195 | #define PACKET3_3D_DRAW_VBUF_2 0x34 |
||
| 196 | #define PACKET3_3D_DRAW_IMMD_2 0x35 |
||
| 197 | #define PACKET3_3D_DRAW_INDX_2 0x36 |
||
| 198 | #define PACKET3_BITBLT_MULTI 0x9B |
||
| 199 | |||
| 200 | #define PACKET0(reg, n) (CP_PACKET0 | \ |
||
| 201 | REG_SET(PACKET0_BASE_INDEX, (reg) >> 2) | \ |
||
| 202 | REG_SET(PACKET0_COUNT, (n))) |
||
| 203 | #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) |
||
| 204 | #define PACKET3(op, n) (CP_PACKET3 | \ |
||
| 205 | REG_SET(PACKET3_IT_OPCODE, (op)) | \ |
||
| 206 | REG_SET(PACKET3_COUNT, (n))) |
||
| 207 | |||
| 208 | /* Registers */ |
||
| 209 | #define R_0000F0_RBBM_SOFT_RESET 0x0000F0 |
||
| 210 | #define S_0000F0_SOFT_RESET_CP(x) (((x) & 0x1) << 0) |
||
| 211 | #define G_0000F0_SOFT_RESET_CP(x) (((x) >> 0) & 0x1) |
||
| 212 | #define C_0000F0_SOFT_RESET_CP 0xFFFFFFFE |
||
| 213 | #define S_0000F0_SOFT_RESET_HI(x) (((x) & 0x1) << 1) |
||
| 214 | #define G_0000F0_SOFT_RESET_HI(x) (((x) >> 1) & 0x1) |
||
| 215 | #define C_0000F0_SOFT_RESET_HI 0xFFFFFFFD |
||
| 216 | #define S_0000F0_SOFT_RESET_VAP(x) (((x) & 0x1) << 2) |
||
| 217 | #define G_0000F0_SOFT_RESET_VAP(x) (((x) >> 2) & 0x1) |
||
| 218 | #define C_0000F0_SOFT_RESET_VAP 0xFFFFFFFB |
||
| 219 | #define S_0000F0_SOFT_RESET_RE(x) (((x) & 0x1) << 3) |
||
| 220 | #define G_0000F0_SOFT_RESET_RE(x) (((x) >> 3) & 0x1) |
||
| 221 | #define C_0000F0_SOFT_RESET_RE 0xFFFFFFF7 |
||
| 222 | #define S_0000F0_SOFT_RESET_PP(x) (((x) & 0x1) << 4) |
||
| 223 | #define G_0000F0_SOFT_RESET_PP(x) (((x) >> 4) & 0x1) |
||
| 224 | #define C_0000F0_SOFT_RESET_PP 0xFFFFFFEF |
||
| 225 | #define S_0000F0_SOFT_RESET_E2(x) (((x) & 0x1) << 5) |
||
| 226 | #define G_0000F0_SOFT_RESET_E2(x) (((x) >> 5) & 0x1) |
||
| 227 | #define C_0000F0_SOFT_RESET_E2 0xFFFFFFDF |
||
| 228 | #define S_0000F0_SOFT_RESET_RB(x) (((x) & 0x1) << 6) |
||
| 229 | #define G_0000F0_SOFT_RESET_RB(x) (((x) >> 6) & 0x1) |
||
| 230 | #define C_0000F0_SOFT_RESET_RB 0xFFFFFFBF |
||
| 231 | #define S_0000F0_SOFT_RESET_HDP(x) (((x) & 0x1) << 7) |
||
| 232 | #define G_0000F0_SOFT_RESET_HDP(x) (((x) >> 7) & 0x1) |
||
| 233 | #define C_0000F0_SOFT_RESET_HDP 0xFFFFFF7F |
||
| 234 | #define S_0000F0_SOFT_RESET_MC(x) (((x) & 0x1) << 8) |
||
| 235 | #define G_0000F0_SOFT_RESET_MC(x) (((x) >> 8) & 0x1) |
||
| 236 | #define C_0000F0_SOFT_RESET_MC 0xFFFFFEFF |
||
| 237 | #define S_0000F0_SOFT_RESET_AIC(x) (((x) & 0x1) << 9) |
||
| 238 | #define G_0000F0_SOFT_RESET_AIC(x) (((x) >> 9) & 0x1) |
||
| 239 | #define C_0000F0_SOFT_RESET_AIC 0xFFFFFDFF |
||
| 240 | #define S_0000F0_SOFT_RESET_VIP(x) (((x) & 0x1) << 10) |
||
| 241 | #define G_0000F0_SOFT_RESET_VIP(x) (((x) >> 10) & 0x1) |
||
| 242 | #define C_0000F0_SOFT_RESET_VIP 0xFFFFFBFF |
||
| 243 | #define S_0000F0_SOFT_RESET_DISP(x) (((x) & 0x1) << 11) |
||
| 244 | #define G_0000F0_SOFT_RESET_DISP(x) (((x) >> 11) & 0x1) |
||
| 245 | #define C_0000F0_SOFT_RESET_DISP 0xFFFFF7FF |
||
| 246 | #define S_0000F0_SOFT_RESET_CG(x) (((x) & 0x1) << 12) |
||
| 247 | #define G_0000F0_SOFT_RESET_CG(x) (((x) >> 12) & 0x1) |
||
| 248 | #define C_0000F0_SOFT_RESET_CG 0xFFFFEFFF |
||
| 249 | #define S_0000F0_SOFT_RESET_GA(x) (((x) & 0x1) << 13) |
||
| 250 | #define G_0000F0_SOFT_RESET_GA(x) (((x) >> 13) & 0x1) |
||
| 251 | #define C_0000F0_SOFT_RESET_GA 0xFFFFDFFF |
||
| 252 | #define S_0000F0_SOFT_RESET_IDCT(x) (((x) & 0x1) << 14) |
||
| 253 | #define G_0000F0_SOFT_RESET_IDCT(x) (((x) >> 14) & 0x1) |
||
| 254 | #define C_0000F0_SOFT_RESET_IDCT 0xFFFFBFFF |
||
| 255 | #define R_0000F8_CONFIG_MEMSIZE 0x0000F8 |
||
| 256 | #define S_0000F8_CONFIG_MEMSIZE(x) (((x) & 0xFFFFFFFF) << 0) |
||
| 257 | #define G_0000F8_CONFIG_MEMSIZE(x) (((x) >> 0) & 0xFFFFFFFF) |
||
| 258 | #define C_0000F8_CONFIG_MEMSIZE 0x00000000 |
||
| 259 | #define R_000134_HDP_FB_LOCATION 0x000134 |
||
| 260 | #define S_000134_HDP_FB_START(x) (((x) & 0xFFFF) << 0) |
||
| 261 | #define G_000134_HDP_FB_START(x) (((x) >> 0) & 0xFFFF) |
||
| 262 | #define C_000134_HDP_FB_START 0xFFFF0000 |
||
| 263 | #define R_000300_VGA_RENDER_CONTROL 0x000300 |
||
| 264 | #define S_000300_VGA_BLINK_RATE(x) (((x) & 0x1F) << 0) |
||
| 265 | #define G_000300_VGA_BLINK_RATE(x) (((x) >> 0) & 0x1F) |
||
| 266 | #define C_000300_VGA_BLINK_RATE 0xFFFFFFE0 |
||
| 267 | #define S_000300_VGA_BLINK_MODE(x) (((x) & 0x3) << 5) |
||
| 268 | #define G_000300_VGA_BLINK_MODE(x) (((x) >> 5) & 0x3) |
||
| 269 | #define C_000300_VGA_BLINK_MODE 0xFFFFFF9F |
||
| 270 | #define S_000300_VGA_CURSOR_BLINK_INVERT(x) (((x) & 0x1) << 7) |
||
| 271 | #define G_000300_VGA_CURSOR_BLINK_INVERT(x) (((x) >> 7) & 0x1) |
||
| 272 | #define C_000300_VGA_CURSOR_BLINK_INVERT 0xFFFFFF7F |
||
| 273 | #define S_000300_VGA_EXTD_ADDR_COUNT_ENABLE(x) (((x) & 0x1) << 8) |
||
| 274 | #define G_000300_VGA_EXTD_ADDR_COUNT_ENABLE(x) (((x) >> 8) & 0x1) |
||
| 275 | #define C_000300_VGA_EXTD_ADDR_COUNT_ENABLE 0xFFFFFEFF |
||
| 276 | #define S_000300_VGA_VSTATUS_CNTL(x) (((x) & 0x3) << 16) |
||
| 277 | #define G_000300_VGA_VSTATUS_CNTL(x) (((x) >> 16) & 0x3) |
||
| 278 | #define C_000300_VGA_VSTATUS_CNTL 0xFFFCFFFF |
||
| 279 | #define S_000300_VGA_LOCK_8DOT(x) (((x) & 0x1) << 24) |
||
| 280 | #define G_000300_VGA_LOCK_8DOT(x) (((x) >> 24) & 0x1) |
||
| 281 | #define C_000300_VGA_LOCK_8DOT 0xFEFFFFFF |
||
| 282 | #define S_000300_VGAREG_LINECMP_COMPATIBILITY_SEL(x) (((x) & 0x1) << 25) |
||
| 283 | #define G_000300_VGAREG_LINECMP_COMPATIBILITY_SEL(x) (((x) >> 25) & 0x1) |
||
| 284 | #define C_000300_VGAREG_LINECMP_COMPATIBILITY_SEL 0xFDFFFFFF |
||
| 285 | #define R_000310_VGA_MEMORY_BASE_ADDRESS 0x000310 |
||
| 286 | #define S_000310_VGA_MEMORY_BASE_ADDRESS(x) (((x) & 0xFFFFFFFF) << 0) |
||
| 287 | #define G_000310_VGA_MEMORY_BASE_ADDRESS(x) (((x) >> 0) & 0xFFFFFFFF) |
||
| 288 | #define C_000310_VGA_MEMORY_BASE_ADDRESS 0x00000000 |
||
| 289 | #define R_000328_VGA_HDP_CONTROL 0x000328 |
||
| 290 | #define S_000328_VGA_MEM_PAGE_SELECT_EN(x) (((x) & 0x1) << 0) |
||
| 291 | #define G_000328_VGA_MEM_PAGE_SELECT_EN(x) (((x) >> 0) & 0x1) |
||
| 292 | #define C_000328_VGA_MEM_PAGE_SELECT_EN 0xFFFFFFFE |
||
| 293 | #define S_000328_VGA_RBBM_LOCK_DISABLE(x) (((x) & 0x1) << 8) |
||
| 294 | #define G_000328_VGA_RBBM_LOCK_DISABLE(x) (((x) >> 8) & 0x1) |
||
| 295 | #define C_000328_VGA_RBBM_LOCK_DISABLE 0xFFFFFEFF |
||
| 296 | #define S_000328_VGA_SOFT_RESET(x) (((x) & 0x1) << 16) |
||
| 297 | #define G_000328_VGA_SOFT_RESET(x) (((x) >> 16) & 0x1) |
||
| 298 | #define C_000328_VGA_SOFT_RESET 0xFFFEFFFF |
||
| 299 | #define S_000328_VGA_TEST_RESET_CONTROL(x) (((x) & 0x1) << 24) |
||
| 300 | #define G_000328_VGA_TEST_RESET_CONTROL(x) (((x) >> 24) & 0x1) |
||
| 301 | #define C_000328_VGA_TEST_RESET_CONTROL 0xFEFFFFFF |
||
| 302 | #define R_000330_D1VGA_CONTROL 0x000330 |
||
| 303 | #define S_000330_D1VGA_MODE_ENABLE(x) (((x) & 0x1) << 0) |
||
| 304 | #define G_000330_D1VGA_MODE_ENABLE(x) (((x) >> 0) & 0x1) |
||
| 305 | #define C_000330_D1VGA_MODE_ENABLE 0xFFFFFFFE |
||
| 306 | #define S_000330_D1VGA_TIMING_SELECT(x) (((x) & 0x1) << 8) |
||
| 307 | #define G_000330_D1VGA_TIMING_SELECT(x) (((x) >> 8) & 0x1) |
||
| 308 | #define C_000330_D1VGA_TIMING_SELECT 0xFFFFFEFF |
||
| 309 | #define S_000330_D1VGA_SYNC_POLARITY_SELECT(x) (((x) & 0x1) << 9) |
||
| 310 | #define G_000330_D1VGA_SYNC_POLARITY_SELECT(x) (((x) >> 9) & 0x1) |
||
| 311 | #define C_000330_D1VGA_SYNC_POLARITY_SELECT 0xFFFFFDFF |
||
| 312 | #define S_000330_D1VGA_OVERSCAN_TIMING_SELECT(x) (((x) & 0x1) << 10) |
||
| 313 | #define G_000330_D1VGA_OVERSCAN_TIMING_SELECT(x) (((x) >> 10) & 0x1) |
||
| 314 | #define C_000330_D1VGA_OVERSCAN_TIMING_SELECT 0xFFFFFBFF |
||
| 315 | #define S_000330_D1VGA_OVERSCAN_COLOR_EN(x) (((x) & 0x1) << 16) |
||
| 316 | #define G_000330_D1VGA_OVERSCAN_COLOR_EN(x) (((x) >> 16) & 0x1) |
||
| 317 | #define C_000330_D1VGA_OVERSCAN_COLOR_EN 0xFFFEFFFF |
||
| 318 | #define S_000330_D1VGA_ROTATE(x) (((x) & 0x3) << 24) |
||
| 319 | #define G_000330_D1VGA_ROTATE(x) (((x) >> 24) & 0x3) |
||
| 320 | #define C_000330_D1VGA_ROTATE 0xFCFFFFFF |
||
| 321 | #define R_000338_D2VGA_CONTROL 0x000338 |
||
| 322 | #define S_000338_D2VGA_MODE_ENABLE(x) (((x) & 0x1) << 0) |
||
| 323 | #define G_000338_D2VGA_MODE_ENABLE(x) (((x) >> 0) & 0x1) |
||
| 324 | #define C_000338_D2VGA_MODE_ENABLE 0xFFFFFFFE |
||
| 325 | #define S_000338_D2VGA_TIMING_SELECT(x) (((x) & 0x1) << 8) |
||
| 326 | #define G_000338_D2VGA_TIMING_SELECT(x) (((x) >> 8) & 0x1) |
||
| 327 | #define C_000338_D2VGA_TIMING_SELECT 0xFFFFFEFF |
||
| 328 | #define S_000338_D2VGA_SYNC_POLARITY_SELECT(x) (((x) & 0x1) << 9) |
||
| 329 | #define G_000338_D2VGA_SYNC_POLARITY_SELECT(x) (((x) >> 9) & 0x1) |
||
| 330 | #define C_000338_D2VGA_SYNC_POLARITY_SELECT 0xFFFFFDFF |
||
| 331 | #define S_000338_D2VGA_OVERSCAN_TIMING_SELECT(x) (((x) & 0x1) << 10) |
||
| 332 | #define G_000338_D2VGA_OVERSCAN_TIMING_SELECT(x) (((x) >> 10) & 0x1) |
||
| 333 | #define C_000338_D2VGA_OVERSCAN_TIMING_SELECT 0xFFFFFBFF |
||
| 334 | #define S_000338_D2VGA_OVERSCAN_COLOR_EN(x) (((x) & 0x1) << 16) |
||
| 335 | #define G_000338_D2VGA_OVERSCAN_COLOR_EN(x) (((x) >> 16) & 0x1) |
||
| 336 | #define C_000338_D2VGA_OVERSCAN_COLOR_EN 0xFFFEFFFF |
||
| 337 | #define S_000338_D2VGA_ROTATE(x) (((x) & 0x3) << 24) |
||
| 338 | #define G_000338_D2VGA_ROTATE(x) (((x) >> 24) & 0x3) |
||
| 339 | #define C_000338_D2VGA_ROTATE 0xFCFFFFFF |
||
| 340 | #define R_0007C0_CP_STAT 0x0007C0 |
||
| 341 | #define S_0007C0_MRU_BUSY(x) (((x) & 0x1) << 0) |
||
| 342 | #define G_0007C0_MRU_BUSY(x) (((x) >> 0) & 0x1) |
||
| 343 | #define C_0007C0_MRU_BUSY 0xFFFFFFFE |
||
| 344 | #define S_0007C0_MWU_BUSY(x) (((x) & 0x1) << 1) |
||
| 345 | #define G_0007C0_MWU_BUSY(x) (((x) >> 1) & 0x1) |
||
| 346 | #define C_0007C0_MWU_BUSY 0xFFFFFFFD |
||
| 347 | #define S_0007C0_RSIU_BUSY(x) (((x) & 0x1) << 2) |
||
| 348 | #define G_0007C0_RSIU_BUSY(x) (((x) >> 2) & 0x1) |
||
| 349 | #define C_0007C0_RSIU_BUSY 0xFFFFFFFB |
||
| 350 | #define S_0007C0_RCIU_BUSY(x) (((x) & 0x1) << 3) |
||
| 351 | #define G_0007C0_RCIU_BUSY(x) (((x) >> 3) & 0x1) |
||
| 352 | #define C_0007C0_RCIU_BUSY 0xFFFFFFF7 |
||
| 353 | #define S_0007C0_CSF_PRIMARY_BUSY(x) (((x) & 0x1) << 9) |
||
| 354 | #define G_0007C0_CSF_PRIMARY_BUSY(x) (((x) >> 9) & 0x1) |
||
| 355 | #define C_0007C0_CSF_PRIMARY_BUSY 0xFFFFFDFF |
||
| 356 | #define S_0007C0_CSF_INDIRECT_BUSY(x) (((x) & 0x1) << 10) |
||
| 357 | #define G_0007C0_CSF_INDIRECT_BUSY(x) (((x) >> 10) & 0x1) |
||
| 358 | #define C_0007C0_CSF_INDIRECT_BUSY 0xFFFFFBFF |
||
| 359 | #define S_0007C0_CSQ_PRIMARY_BUSY(x) (((x) & 0x1) << 11) |
||
| 360 | #define G_0007C0_CSQ_PRIMARY_BUSY(x) (((x) >> 11) & 0x1) |
||
| 361 | #define C_0007C0_CSQ_PRIMARY_BUSY 0xFFFFF7FF |
||
| 362 | #define S_0007C0_CSQ_INDIRECT_BUSY(x) (((x) & 0x1) << 12) |
||
| 363 | #define G_0007C0_CSQ_INDIRECT_BUSY(x) (((x) >> 12) & 0x1) |
||
| 364 | #define C_0007C0_CSQ_INDIRECT_BUSY 0xFFFFEFFF |
||
| 365 | #define S_0007C0_CSI_BUSY(x) (((x) & 0x1) << 13) |
||
| 366 | #define G_0007C0_CSI_BUSY(x) (((x) >> 13) & 0x1) |
||
| 367 | #define C_0007C0_CSI_BUSY 0xFFFFDFFF |
||
| 368 | #define S_0007C0_CSF_INDIRECT2_BUSY(x) (((x) & 0x1) << 14) |
||
| 369 | #define G_0007C0_CSF_INDIRECT2_BUSY(x) (((x) >> 14) & 0x1) |
||
| 370 | #define C_0007C0_CSF_INDIRECT2_BUSY 0xFFFFBFFF |
||
| 371 | #define S_0007C0_CSQ_INDIRECT2_BUSY(x) (((x) & 0x1) << 15) |
||
| 372 | #define G_0007C0_CSQ_INDIRECT2_BUSY(x) (((x) >> 15) & 0x1) |
||
| 373 | #define C_0007C0_CSQ_INDIRECT2_BUSY 0xFFFF7FFF |
||
| 374 | #define S_0007C0_GUIDMA_BUSY(x) (((x) & 0x1) << 28) |
||
| 375 | #define G_0007C0_GUIDMA_BUSY(x) (((x) >> 28) & 0x1) |
||
| 376 | #define C_0007C0_GUIDMA_BUSY 0xEFFFFFFF |
||
| 377 | #define S_0007C0_VIDDMA_BUSY(x) (((x) & 0x1) << 29) |
||
| 378 | #define G_0007C0_VIDDMA_BUSY(x) (((x) >> 29) & 0x1) |
||
| 379 | #define C_0007C0_VIDDMA_BUSY 0xDFFFFFFF |
||
| 380 | #define S_0007C0_CMDSTRM_BUSY(x) (((x) & 0x1) << 30) |
||
| 381 | #define G_0007C0_CMDSTRM_BUSY(x) (((x) >> 30) & 0x1) |
||
| 382 | #define C_0007C0_CMDSTRM_BUSY 0xBFFFFFFF |
||
| 383 | #define S_0007C0_CP_BUSY(x) (((x) & 0x1) << 31) |
||
| 384 | #define G_0007C0_CP_BUSY(x) (((x) >> 31) & 0x1) |
||
| 385 | #define C_0007C0_CP_BUSY 0x7FFFFFFF |
||
| 386 | #define R_000E40_RBBM_STATUS 0x000E40 |
||
| 387 | #define S_000E40_CMDFIFO_AVAIL(x) (((x) & 0x7F) << 0) |
||
| 388 | #define G_000E40_CMDFIFO_AVAIL(x) (((x) >> 0) & 0x7F) |
||
| 389 | #define C_000E40_CMDFIFO_AVAIL 0xFFFFFF80 |
||
| 390 | #define S_000E40_HIRQ_ON_RBB(x) (((x) & 0x1) << 8) |
||
| 391 | #define G_000E40_HIRQ_ON_RBB(x) (((x) >> 8) & 0x1) |
||
| 392 | #define C_000E40_HIRQ_ON_RBB 0xFFFFFEFF |
||
| 393 | #define S_000E40_CPRQ_ON_RBB(x) (((x) & 0x1) << 9) |
||
| 394 | #define G_000E40_CPRQ_ON_RBB(x) (((x) >> 9) & 0x1) |
||
| 395 | #define C_000E40_CPRQ_ON_RBB 0xFFFFFDFF |
||
| 396 | #define S_000E40_CFRQ_ON_RBB(x) (((x) & 0x1) << 10) |
||
| 397 | #define G_000E40_CFRQ_ON_RBB(x) (((x) >> 10) & 0x1) |
||
| 398 | #define C_000E40_CFRQ_ON_RBB 0xFFFFFBFF |
||
| 399 | #define S_000E40_HIRQ_IN_RTBUF(x) (((x) & 0x1) << 11) |
||
| 400 | #define G_000E40_HIRQ_IN_RTBUF(x) (((x) >> 11) & 0x1) |
||
| 401 | #define C_000E40_HIRQ_IN_RTBUF 0xFFFFF7FF |
||
| 402 | #define S_000E40_CPRQ_IN_RTBUF(x) (((x) & 0x1) << 12) |
||
| 403 | #define G_000E40_CPRQ_IN_RTBUF(x) (((x) >> 12) & 0x1) |
||
| 404 | #define C_000E40_CPRQ_IN_RTBUF 0xFFFFEFFF |
||
| 405 | #define S_000E40_CFRQ_IN_RTBUF(x) (((x) & 0x1) << 13) |
||
| 406 | #define G_000E40_CFRQ_IN_RTBUF(x) (((x) >> 13) & 0x1) |
||
| 407 | #define C_000E40_CFRQ_IN_RTBUF 0xFFFFDFFF |
||
| 408 | #define S_000E40_CF_PIPE_BUSY(x) (((x) & 0x1) << 14) |
||
| 409 | #define G_000E40_CF_PIPE_BUSY(x) (((x) >> 14) & 0x1) |
||
| 410 | #define C_000E40_CF_PIPE_BUSY 0xFFFFBFFF |
||
| 411 | #define S_000E40_ENG_EV_BUSY(x) (((x) & 0x1) << 15) |
||
| 412 | #define G_000E40_ENG_EV_BUSY(x) (((x) >> 15) & 0x1) |
||
| 413 | #define C_000E40_ENG_EV_BUSY 0xFFFF7FFF |
||
| 414 | #define S_000E40_CP_CMDSTRM_BUSY(x) (((x) & 0x1) << 16) |
||
| 415 | #define G_000E40_CP_CMDSTRM_BUSY(x) (((x) >> 16) & 0x1) |
||
| 416 | #define C_000E40_CP_CMDSTRM_BUSY 0xFFFEFFFF |
||
| 417 | #define S_000E40_E2_BUSY(x) (((x) & 0x1) << 17) |
||
| 418 | #define G_000E40_E2_BUSY(x) (((x) >> 17) & 0x1) |
||
| 419 | #define C_000E40_E2_BUSY 0xFFFDFFFF |
||
| 420 | #define S_000E40_RB2D_BUSY(x) (((x) & 0x1) << 18) |
||
| 421 | #define G_000E40_RB2D_BUSY(x) (((x) >> 18) & 0x1) |
||
| 422 | #define C_000E40_RB2D_BUSY 0xFFFBFFFF |
||
| 423 | #define S_000E40_RB3D_BUSY(x) (((x) & 0x1) << 19) |
||
| 424 | #define G_000E40_RB3D_BUSY(x) (((x) >> 19) & 0x1) |
||
| 425 | #define C_000E40_RB3D_BUSY 0xFFF7FFFF |
||
| 426 | #define S_000E40_VAP_BUSY(x) (((x) & 0x1) << 20) |
||
| 427 | #define G_000E40_VAP_BUSY(x) (((x) >> 20) & 0x1) |
||
| 428 | #define C_000E40_VAP_BUSY 0xFFEFFFFF |
||
| 429 | #define S_000E40_RE_BUSY(x) (((x) & 0x1) << 21) |
||
| 430 | #define G_000E40_RE_BUSY(x) (((x) >> 21) & 0x1) |
||
| 431 | #define C_000E40_RE_BUSY 0xFFDFFFFF |
||
| 432 | #define S_000E40_TAM_BUSY(x) (((x) & 0x1) << 22) |
||
| 433 | #define G_000E40_TAM_BUSY(x) (((x) >> 22) & 0x1) |
||
| 434 | #define C_000E40_TAM_BUSY 0xFFBFFFFF |
||
| 435 | #define S_000E40_TDM_BUSY(x) (((x) & 0x1) << 23) |
||
| 436 | #define G_000E40_TDM_BUSY(x) (((x) >> 23) & 0x1) |
||
| 437 | #define C_000E40_TDM_BUSY 0xFF7FFFFF |
||
| 438 | #define S_000E40_PB_BUSY(x) (((x) & 0x1) << 24) |
||
| 439 | #define G_000E40_PB_BUSY(x) (((x) >> 24) & 0x1) |
||
| 440 | #define C_000E40_PB_BUSY 0xFEFFFFFF |
||
| 441 | #define S_000E40_TIM_BUSY(x) (((x) & 0x1) << 25) |
||
| 442 | #define G_000E40_TIM_BUSY(x) (((x) >> 25) & 0x1) |
||
| 443 | #define C_000E40_TIM_BUSY 0xFDFFFFFF |
||
| 444 | #define S_000E40_GA_BUSY(x) (((x) & 0x1) << 26) |
||
| 445 | #define G_000E40_GA_BUSY(x) (((x) >> 26) & 0x1) |
||
| 446 | #define C_000E40_GA_BUSY 0xFBFFFFFF |
||
| 447 | #define S_000E40_CBA2D_BUSY(x) (((x) & 0x1) << 27) |
||
| 448 | #define G_000E40_CBA2D_BUSY(x) (((x) >> 27) & 0x1) |
||
| 449 | #define C_000E40_CBA2D_BUSY 0xF7FFFFFF |
||
| 450 | #define S_000E40_RBBM_HIBUSY(x) (((x) & 0x1) << 28) |
||
| 451 | #define G_000E40_RBBM_HIBUSY(x) (((x) >> 28) & 0x1) |
||
| 452 | #define C_000E40_RBBM_HIBUSY 0xEFFFFFFF |
||
| 453 | #define S_000E40_SKID_CFBUSY(x) (((x) & 0x1) << 29) |
||
| 454 | #define G_000E40_SKID_CFBUSY(x) (((x) >> 29) & 0x1) |
||
| 455 | #define C_000E40_SKID_CFBUSY 0xDFFFFFFF |
||
| 456 | #define S_000E40_VAP_VF_BUSY(x) (((x) & 0x1) << 30) |
||
| 457 | #define G_000E40_VAP_VF_BUSY(x) (((x) >> 30) & 0x1) |
||
| 458 | #define C_000E40_VAP_VF_BUSY 0xBFFFFFFF |
||
| 459 | #define S_000E40_GUI_ACTIVE(x) (((x) & 0x1) << 31) |
||
| 460 | #define G_000E40_GUI_ACTIVE(x) (((x) >> 31) & 0x1) |
||
| 461 | #define C_000E40_GUI_ACTIVE 0x7FFFFFFF |
||
| 462 | #define R_006080_D1CRTC_CONTROL 0x006080 |
||
| 463 | #define S_006080_D1CRTC_MASTER_EN(x) (((x) & 0x1) << 0) |
||
| 464 | #define G_006080_D1CRTC_MASTER_EN(x) (((x) >> 0) & 0x1) |
||
| 465 | #define C_006080_D1CRTC_MASTER_EN 0xFFFFFFFE |
||
| 466 | #define S_006080_D1CRTC_SYNC_RESET_SEL(x) (((x) & 0x1) << 4) |
||
| 467 | #define G_006080_D1CRTC_SYNC_RESET_SEL(x) (((x) >> 4) & 0x1) |
||
| 468 | #define C_006080_D1CRTC_SYNC_RESET_SEL 0xFFFFFFEF |
||
| 469 | #define S_006080_D1CRTC_DISABLE_POINT_CNTL(x) (((x) & 0x3) << 8) |
||
| 470 | #define G_006080_D1CRTC_DISABLE_POINT_CNTL(x) (((x) >> 8) & 0x3) |
||
| 471 | #define C_006080_D1CRTC_DISABLE_POINT_CNTL 0xFFFFFCFF |
||
| 472 | #define S_006080_D1CRTC_CURRENT_MASTER_EN_STATE(x) (((x) & 0x1) << 16) |
||
| 473 | #define G_006080_D1CRTC_CURRENT_MASTER_EN_STATE(x) (((x) >> 16) & 0x1) |
||
| 474 | #define C_006080_D1CRTC_CURRENT_MASTER_EN_STATE 0xFFFEFFFF |
||
| 475 | #define S_006080_D1CRTC_DISP_READ_REQUEST_DISABLE(x) (((x) & 0x1) << 24) |
||
| 476 | #define G_006080_D1CRTC_DISP_READ_REQUEST_DISABLE(x) (((x) >> 24) & 0x1) |
||
| 477 | #define C_006080_D1CRTC_DISP_READ_REQUEST_DISABLE 0xFEFFFFFF |
||
| 478 | #define R_0060E8_D1CRTC_UPDATE_LOCK 0x0060E8 |
||
| 479 | #define S_0060E8_D1CRTC_UPDATE_LOCK(x) (((x) & 0x1) << 0) |
||
| 480 | #define G_0060E8_D1CRTC_UPDATE_LOCK(x) (((x) >> 0) & 0x1) |
||
| 481 | #define C_0060E8_D1CRTC_UPDATE_LOCK 0xFFFFFFFE |
||
| 482 | #define R_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS 0x006110 |
||
| 483 | #define S_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS(x) (((x) & 0xFFFFFFFF) << 0) |
||
| 484 | #define G_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS(x) (((x) >> 0) & 0xFFFFFFFF) |
||
| 485 | #define C_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS 0x00000000 |
||
| 486 | #define R_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS 0x006118 |
||
| 487 | #define S_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS(x) (((x) & 0xFFFFFFFF) << 0) |
||
| 488 | #define G_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS(x) (((x) >> 0) & 0xFFFFFFFF) |
||
| 489 | #define C_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS 0x00000000 |
||
| 490 | #define R_006880_D2CRTC_CONTROL 0x006880 |
||
| 491 | #define S_006880_D2CRTC_MASTER_EN(x) (((x) & 0x1) << 0) |
||
| 492 | #define G_006880_D2CRTC_MASTER_EN(x) (((x) >> 0) & 0x1) |
||
| 493 | #define C_006880_D2CRTC_MASTER_EN 0xFFFFFFFE |
||
| 494 | #define S_006880_D2CRTC_SYNC_RESET_SEL(x) (((x) & 0x1) << 4) |
||
| 495 | #define G_006880_D2CRTC_SYNC_RESET_SEL(x) (((x) >> 4) & 0x1) |
||
| 496 | #define C_006880_D2CRTC_SYNC_RESET_SEL 0xFFFFFFEF |
||
| 497 | #define S_006880_D2CRTC_DISABLE_POINT_CNTL(x) (((x) & 0x3) << 8) |
||
| 498 | #define G_006880_D2CRTC_DISABLE_POINT_CNTL(x) (((x) >> 8) & 0x3) |
||
| 499 | #define C_006880_D2CRTC_DISABLE_POINT_CNTL 0xFFFFFCFF |
||
| 500 | #define S_006880_D2CRTC_CURRENT_MASTER_EN_STATE(x) (((x) & 0x1) << 16) |
||
| 501 | #define G_006880_D2CRTC_CURRENT_MASTER_EN_STATE(x) (((x) >> 16) & 0x1) |
||
| 502 | #define C_006880_D2CRTC_CURRENT_MASTER_EN_STATE 0xFFFEFFFF |
||
| 503 | #define S_006880_D2CRTC_DISP_READ_REQUEST_DISABLE(x) (((x) & 0x1) << 24) |
||
| 504 | #define G_006880_D2CRTC_DISP_READ_REQUEST_DISABLE(x) (((x) >> 24) & 0x1) |
||
| 505 | #define C_006880_D2CRTC_DISP_READ_REQUEST_DISABLE 0xFEFFFFFF |
||
| 506 | #define R_0068E8_D2CRTC_UPDATE_LOCK 0x0068E8 |
||
| 507 | #define S_0068E8_D2CRTC_UPDATE_LOCK(x) (((x) & 0x1) << 0) |
||
| 508 | #define G_0068E8_D2CRTC_UPDATE_LOCK(x) (((x) >> 0) & 0x1) |
||
| 509 | #define C_0068E8_D2CRTC_UPDATE_LOCK 0xFFFFFFFE |
||
| 510 | #define R_006910_D2GRPH_PRIMARY_SURFACE_ADDRESS 0x006910 |
||
| 511 | #define S_006910_D2GRPH_PRIMARY_SURFACE_ADDRESS(x) (((x) & 0xFFFFFFFF) << 0) |
||
| 512 | #define G_006910_D2GRPH_PRIMARY_SURFACE_ADDRESS(x) (((x) >> 0) & 0xFFFFFFFF) |
||
| 513 | #define C_006910_D2GRPH_PRIMARY_SURFACE_ADDRESS 0x00000000 |
||
| 514 | #define R_006918_D2GRPH_SECONDARY_SURFACE_ADDRESS 0x006918 |
||
| 515 | #define S_006918_D2GRPH_SECONDARY_SURFACE_ADDRESS(x) (((x) & 0xFFFFFFFF) << 0) |
||
| 516 | #define G_006918_D2GRPH_SECONDARY_SURFACE_ADDRESS(x) (((x) >> 0) & 0xFFFFFFFF) |
||
| 517 | #define C_006918_D2GRPH_SECONDARY_SURFACE_ADDRESS 0x00000000 |
||
| 518 | |||
| 519 | |||
| 520 | #define R_000001_MC_FB_LOCATION 0x000001 |
||
| 521 | #define S_000001_MC_FB_START(x) (((x) & 0xFFFF) << 0) |
||
| 522 | #define G_000001_MC_FB_START(x) (((x) >> 0) & 0xFFFF) |
||
| 523 | #define C_000001_MC_FB_START 0xFFFF0000 |
||
| 524 | #define S_000001_MC_FB_TOP(x) (((x) & 0xFFFF) << 16) |
||
| 525 | #define G_000001_MC_FB_TOP(x) (((x) >> 16) & 0xFFFF) |
||
| 526 | #define C_000001_MC_FB_TOP 0x0000FFFF |
||
| 527 | #define R_000002_MC_AGP_LOCATION 0x000002 |
||
| 528 | #define S_000002_MC_AGP_START(x) (((x) & 0xFFFF) << 0) |
||
| 529 | #define G_000002_MC_AGP_START(x) (((x) >> 0) & 0xFFFF) |
||
| 530 | #define C_000002_MC_AGP_START 0xFFFF0000 |
||
| 531 | #define S_000002_MC_AGP_TOP(x) (((x) & 0xFFFF) << 16) |
||
| 532 | #define G_000002_MC_AGP_TOP(x) (((x) >> 16) & 0xFFFF) |
||
| 533 | #define C_000002_MC_AGP_TOP 0x0000FFFF |
||
| 534 | #define R_000003_MC_AGP_BASE 0x000003 |
||
| 535 | #define S_000003_AGP_BASE_ADDR(x) (((x) & 0xFFFFFFFF) << 0) |
||
| 536 | #define G_000003_AGP_BASE_ADDR(x) (((x) >> 0) & 0xFFFFFFFF) |
||
| 537 | #define C_000003_AGP_BASE_ADDR 0x00000000 |
||
| 538 | #define R_000004_MC_AGP_BASE_2 0x000004 |
||
| 539 | #define S_000004_AGP_BASE_ADDR_2(x) (((x) & 0xF) << 0) |
||
| 540 | #define G_000004_AGP_BASE_ADDR_2(x) (((x) >> 0) & 0xF) |
||
| 541 | #define C_000004_AGP_BASE_ADDR_2 0xFFFFFFF0 |
||
| 542 | |||
| 543 | |||
| 544 | #define R_00000F_CP_DYN_CNTL 0x00000F |
||
| 545 | #define S_00000F_CP_FORCEON(x) (((x) & 0x1) << 0) |
||
| 546 | #define G_00000F_CP_FORCEON(x) (((x) >> 0) & 0x1) |
||
| 547 | #define C_00000F_CP_FORCEON 0xFFFFFFFE |
||
| 548 | #define S_00000F_CP_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 1) |
||
| 549 | #define G_00000F_CP_MAX_DYN_STOP_LAT(x) (((x) >> 1) & 0x1) |
||
| 550 | #define C_00000F_CP_MAX_DYN_STOP_LAT 0xFFFFFFFD |
||
| 551 | #define S_00000F_CP_CLOCK_STATUS(x) (((x) & 0x1) << 2) |
||
| 552 | #define G_00000F_CP_CLOCK_STATUS(x) (((x) >> 2) & 0x1) |
||
| 553 | #define C_00000F_CP_CLOCK_STATUS 0xFFFFFFFB |
||
| 554 | #define S_00000F_CP_PROG_SHUTOFF(x) (((x) & 0x1) << 3) |
||
| 555 | #define G_00000F_CP_PROG_SHUTOFF(x) (((x) >> 3) & 0x1) |
||
| 556 | #define C_00000F_CP_PROG_SHUTOFF 0xFFFFFFF7 |
||
| 557 | #define S_00000F_CP_PROG_DELAY_VALUE(x) (((x) & 0xFF) << 4) |
||
| 558 | #define G_00000F_CP_PROG_DELAY_VALUE(x) (((x) >> 4) & 0xFF) |
||
| 559 | #define C_00000F_CP_PROG_DELAY_VALUE 0xFFFFF00F |
||
| 560 | #define S_00000F_CP_LOWER_POWER_IDLE(x) (((x) & 0xFF) << 12) |
||
| 561 | #define G_00000F_CP_LOWER_POWER_IDLE(x) (((x) >> 12) & 0xFF) |
||
| 562 | #define C_00000F_CP_LOWER_POWER_IDLE 0xFFF00FFF |
||
| 563 | #define S_00000F_CP_LOWER_POWER_IGNORE(x) (((x) & 0x1) << 20) |
||
| 564 | #define G_00000F_CP_LOWER_POWER_IGNORE(x) (((x) >> 20) & 0x1) |
||
| 565 | #define C_00000F_CP_LOWER_POWER_IGNORE 0xFFEFFFFF |
||
| 566 | #define S_00000F_CP_NORMAL_POWER_IGNORE(x) (((x) & 0x1) << 21) |
||
| 567 | #define G_00000F_CP_NORMAL_POWER_IGNORE(x) (((x) >> 21) & 0x1) |
||
| 568 | #define C_00000F_CP_NORMAL_POWER_IGNORE 0xFFDFFFFF |
||
| 569 | #define S_00000F_SPARE(x) (((x) & 0x3) << 22) |
||
| 570 | #define G_00000F_SPARE(x) (((x) >> 22) & 0x3) |
||
| 571 | #define C_00000F_SPARE 0xFF3FFFFF |
||
| 572 | #define S_00000F_CP_NORMAL_POWER_BUSY(x) (((x) & 0xFF) << 24) |
||
| 573 | #define G_00000F_CP_NORMAL_POWER_BUSY(x) (((x) >> 24) & 0xFF) |
||
| 574 | #define C_00000F_CP_NORMAL_POWER_BUSY 0x00FFFFFF |
||
| 575 | #define R_000011_E2_DYN_CNTL 0x000011 |
||
| 576 | #define S_000011_E2_FORCEON(x) (((x) & 0x1) << 0) |
||
| 577 | #define G_000011_E2_FORCEON(x) (((x) >> 0) & 0x1) |
||
| 578 | #define C_000011_E2_FORCEON 0xFFFFFFFE |
||
| 579 | #define S_000011_E2_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 1) |
||
| 580 | #define G_000011_E2_MAX_DYN_STOP_LAT(x) (((x) >> 1) & 0x1) |
||
| 581 | #define C_000011_E2_MAX_DYN_STOP_LAT 0xFFFFFFFD |
||
| 582 | #define S_000011_E2_CLOCK_STATUS(x) (((x) & 0x1) << 2) |
||
| 583 | #define G_000011_E2_CLOCK_STATUS(x) (((x) >> 2) & 0x1) |
||
| 584 | #define C_000011_E2_CLOCK_STATUS 0xFFFFFFFB |
||
| 585 | #define S_000011_E2_PROG_SHUTOFF(x) (((x) & 0x1) << 3) |
||
| 586 | #define G_000011_E2_PROG_SHUTOFF(x) (((x) >> 3) & 0x1) |
||
| 587 | #define C_000011_E2_PROG_SHUTOFF 0xFFFFFFF7 |
||
| 588 | #define S_000011_E2_PROG_DELAY_VALUE(x) (((x) & 0xFF) << 4) |
||
| 589 | #define G_000011_E2_PROG_DELAY_VALUE(x) (((x) >> 4) & 0xFF) |
||
| 590 | #define C_000011_E2_PROG_DELAY_VALUE 0xFFFFF00F |
||
| 591 | #define S_000011_E2_LOWER_POWER_IDLE(x) (((x) & 0xFF) << 12) |
||
| 592 | #define G_000011_E2_LOWER_POWER_IDLE(x) (((x) >> 12) & 0xFF) |
||
| 593 | #define C_000011_E2_LOWER_POWER_IDLE 0xFFF00FFF |
||
| 594 | #define S_000011_E2_LOWER_POWER_IGNORE(x) (((x) & 0x1) << 20) |
||
| 595 | #define G_000011_E2_LOWER_POWER_IGNORE(x) (((x) >> 20) & 0x1) |
||
| 596 | #define C_000011_E2_LOWER_POWER_IGNORE 0xFFEFFFFF |
||
| 597 | #define S_000011_E2_NORMAL_POWER_IGNORE(x) (((x) & 0x1) << 21) |
||
| 598 | #define G_000011_E2_NORMAL_POWER_IGNORE(x) (((x) >> 21) & 0x1) |
||
| 599 | #define C_000011_E2_NORMAL_POWER_IGNORE 0xFFDFFFFF |
||
| 600 | #define S_000011_SPARE(x) (((x) & 0x3) << 22) |
||
| 601 | #define G_000011_SPARE(x) (((x) >> 22) & 0x3) |
||
| 602 | #define C_000011_SPARE 0xFF3FFFFF |
||
| 603 | #define S_000011_E2_NORMAL_POWER_BUSY(x) (((x) & 0xFF) << 24) |
||
| 604 | #define G_000011_E2_NORMAL_POWER_BUSY(x) (((x) >> 24) & 0xFF) |
||
| 605 | #define C_000011_E2_NORMAL_POWER_BUSY 0x00FFFFFF |
||
| 606 | #define R_000013_IDCT_DYN_CNTL 0x000013 |
||
| 607 | #define S_000013_IDCT_FORCEON(x) (((x) & 0x1) << 0) |
||
| 608 | #define G_000013_IDCT_FORCEON(x) (((x) >> 0) & 0x1) |
||
| 609 | #define C_000013_IDCT_FORCEON 0xFFFFFFFE |
||
| 610 | #define S_000013_IDCT_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 1) |
||
| 611 | #define G_000013_IDCT_MAX_DYN_STOP_LAT(x) (((x) >> 1) & 0x1) |
||
| 612 | #define C_000013_IDCT_MAX_DYN_STOP_LAT 0xFFFFFFFD |
||
| 613 | #define S_000013_IDCT_CLOCK_STATUS(x) (((x) & 0x1) << 2) |
||
| 614 | #define G_000013_IDCT_CLOCK_STATUS(x) (((x) >> 2) & 0x1) |
||
| 615 | #define C_000013_IDCT_CLOCK_STATUS 0xFFFFFFFB |
||
| 616 | #define S_000013_IDCT_PROG_SHUTOFF(x) (((x) & 0x1) << 3) |
||
| 617 | #define G_000013_IDCT_PROG_SHUTOFF(x) (((x) >> 3) & 0x1) |
||
| 618 | #define C_000013_IDCT_PROG_SHUTOFF 0xFFFFFFF7 |
||
| 619 | #define S_000013_IDCT_PROG_DELAY_VALUE(x) (((x) & 0xFF) << 4) |
||
| 620 | #define G_000013_IDCT_PROG_DELAY_VALUE(x) (((x) >> 4) & 0xFF) |
||
| 621 | #define C_000013_IDCT_PROG_DELAY_VALUE 0xFFFFF00F |
||
| 622 | #define S_000013_IDCT_LOWER_POWER_IDLE(x) (((x) & 0xFF) << 12) |
||
| 623 | #define G_000013_IDCT_LOWER_POWER_IDLE(x) (((x) >> 12) & 0xFF) |
||
| 624 | #define C_000013_IDCT_LOWER_POWER_IDLE 0xFFF00FFF |
||
| 625 | #define S_000013_IDCT_LOWER_POWER_IGNORE(x) (((x) & 0x1) << 20) |
||
| 626 | #define G_000013_IDCT_LOWER_POWER_IGNORE(x) (((x) >> 20) & 0x1) |
||
| 627 | #define C_000013_IDCT_LOWER_POWER_IGNORE 0xFFEFFFFF |
||
| 628 | #define S_000013_IDCT_NORMAL_POWER_IGNORE(x) (((x) & 0x1) << 21) |
||
| 629 | #define G_000013_IDCT_NORMAL_POWER_IGNORE(x) (((x) >> 21) & 0x1) |
||
| 630 | #define C_000013_IDCT_NORMAL_POWER_IGNORE 0xFFDFFFFF |
||
| 631 | #define S_000013_SPARE(x) (((x) & 0x3) << 22) |
||
| 632 | #define G_000013_SPARE(x) (((x) >> 22) & 0x3) |
||
| 633 | #define C_000013_SPARE 0xFF3FFFFF |
||
| 634 | #define S_000013_IDCT_NORMAL_POWER_BUSY(x) (((x) & 0xFF) << 24) |
||
| 635 | #define G_000013_IDCT_NORMAL_POWER_BUSY(x) (((x) >> 24) & 0xFF) |
||
| 636 | #define C_000013_IDCT_NORMAL_POWER_BUSY 0x00FFFFFF |
||
| 637 | |||
| 638 | #endif |