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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 1117 | serge | 1 | /* |
| 2 | * Copyright 2008 Advanced Micro Devices, Inc. |
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| 3 | * Copyright 2008 Red Hat Inc. |
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| 4 | * Copyright 2009 Jerome Glisse. |
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| 5 | * |
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| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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| 7 | * copy of this software and associated documentation files (the "Software"), |
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| 8 | * to deal in the Software without restriction, including without limitation |
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| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
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| 11 | * Software is furnished to do so, subject to the following conditions: |
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| 12 | * |
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| 13 | * The above copyright notice and this permission notice shall be included in |
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| 14 | * all copies or substantial portions of the Software. |
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| 15 | * |
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| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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| 19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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| 20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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| 21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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| 22 | * OTHER DEALINGS IN THE SOFTWARE. |
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| 23 | * |
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| 24 | * Authors: Dave Airlie |
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| 25 | * Alex Deucher |
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| 26 | * Jerome Glisse |
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| 27 | */ |
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| 1179 | serge | 28 | #include |
| 1986 | serge | 29 | #include |
| 2997 | Serge | 30 | #include |
| 1179 | serge | 31 | #include "rv515d.h" |
| 1117 | serge | 32 | #include "radeon.h" |
| 1963 | serge | 33 | #include "radeon_asic.h" |
| 1221 | serge | 34 | #include "atom.h" |
| 1179 | serge | 35 | #include "rv515_reg_safe.h" |
| 1117 | serge | 36 | |
| 1221 | serge | 37 | /* This files gather functions specifics to: rv515 */ |
| 2997 | Serge | 38 | static int rv515_debugfs_pipes_info_init(struct radeon_device *rdev); |
| 39 | static int rv515_debugfs_ga_info_init(struct radeon_device *rdev); |
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| 40 | static void rv515_gpu_init(struct radeon_device *rdev); |
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| 1117 | serge | 41 | int rv515_mc_wait_for_idle(struct radeon_device *rdev); |
| 42 | |||
| 3192 | Serge | 43 | static const u32 crtc_offsets[2] = |
| 44 | { |
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| 45 | 0, |
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| 46 | AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL |
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| 47 | }; |
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| 48 | |||
| 1221 | serge | 49 | void rv515_debugfs(struct radeon_device *rdev) |
| 1117 | serge | 50 | { |
| 1129 | serge | 51 | if (r100_debugfs_rbbm_init(rdev)) { |
| 52 | DRM_ERROR("Failed to register debugfs file for RBBM !\n"); |
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| 53 | } |
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| 54 | if (rv515_debugfs_pipes_info_init(rdev)) { |
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| 55 | DRM_ERROR("Failed to register debugfs file for pipes !\n"); |
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| 56 | } |
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| 57 | if (rv515_debugfs_ga_info_init(rdev)) { |
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| 58 | DRM_ERROR("Failed to register debugfs file for pipes !\n"); |
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| 59 | } |
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| 1117 | serge | 60 | } |
| 61 | |||
| 2997 | Serge | 62 | void rv515_ring_start(struct radeon_device *rdev, struct radeon_ring *ring) |
| 1117 | serge | 63 | { |
| 64 | int r; |
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| 65 | |||
| 2997 | Serge | 66 | r = radeon_ring_lock(rdev, ring, 64); |
| 1117 | serge | 67 | if (r) { |
| 68 | return; |
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| 69 | } |
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| 2997 | Serge | 70 | radeon_ring_write(ring, PACKET0(ISYNC_CNTL, 0)); |
| 71 | radeon_ring_write(ring, |
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| 1179 | serge | 72 | ISYNC_ANY2D_IDLE3D | |
| 73 | ISYNC_ANY3D_IDLE2D | |
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| 74 | ISYNC_WAIT_IDLEGUI | |
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| 75 | ISYNC_CPSCRATCH_IDLEGUI); |
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| 2997 | Serge | 76 | radeon_ring_write(ring, PACKET0(WAIT_UNTIL, 0)); |
| 77 | radeon_ring_write(ring, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN); |
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| 78 | radeon_ring_write(ring, PACKET0(R300_DST_PIPE_CONFIG, 0)); |
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| 79 | radeon_ring_write(ring, R300_PIPE_AUTO_CONFIG); |
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| 80 | radeon_ring_write(ring, PACKET0(GB_SELECT, 0)); |
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| 81 | radeon_ring_write(ring, 0); |
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| 82 | radeon_ring_write(ring, PACKET0(GB_ENABLE, 0)); |
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| 83 | radeon_ring_write(ring, 0); |
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| 84 | radeon_ring_write(ring, PACKET0(R500_SU_REG_DEST, 0)); |
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| 85 | radeon_ring_write(ring, (1 << rdev->num_gb_pipes) - 1); |
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| 86 | radeon_ring_write(ring, PACKET0(VAP_INDEX_OFFSET, 0)); |
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| 87 | radeon_ring_write(ring, 0); |
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| 88 | radeon_ring_write(ring, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0)); |
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| 89 | radeon_ring_write(ring, RB3D_DC_FLUSH | RB3D_DC_FREE); |
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| 90 | radeon_ring_write(ring, PACKET0(ZB_ZCACHE_CTLSTAT, 0)); |
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| 91 | radeon_ring_write(ring, ZC_FLUSH | ZC_FREE); |
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| 92 | radeon_ring_write(ring, PACKET0(WAIT_UNTIL, 0)); |
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| 93 | radeon_ring_write(ring, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN); |
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| 94 | radeon_ring_write(ring, PACKET0(GB_AA_CONFIG, 0)); |
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| 95 | radeon_ring_write(ring, 0); |
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| 96 | radeon_ring_write(ring, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0)); |
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| 97 | radeon_ring_write(ring, RB3D_DC_FLUSH | RB3D_DC_FREE); |
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| 98 | radeon_ring_write(ring, PACKET0(ZB_ZCACHE_CTLSTAT, 0)); |
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| 99 | radeon_ring_write(ring, ZC_FLUSH | ZC_FREE); |
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| 100 | radeon_ring_write(ring, PACKET0(GB_MSPOS0, 0)); |
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| 101 | radeon_ring_write(ring, |
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| 1179 | serge | 102 | ((6 << MS_X0_SHIFT) | |
| 103 | (6 << MS_Y0_SHIFT) | |
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| 104 | (6 << MS_X1_SHIFT) | |
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| 105 | (6 << MS_Y1_SHIFT) | |
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| 106 | (6 << MS_X2_SHIFT) | |
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| 107 | (6 << MS_Y2_SHIFT) | |
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| 108 | (6 << MSBD0_Y_SHIFT) | |
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| 109 | (6 << MSBD0_X_SHIFT))); |
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| 2997 | Serge | 110 | radeon_ring_write(ring, PACKET0(GB_MSPOS1, 0)); |
| 111 | radeon_ring_write(ring, |
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| 1179 | serge | 112 | ((6 << MS_X3_SHIFT) | |
| 113 | (6 << MS_Y3_SHIFT) | |
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| 114 | (6 << MS_X4_SHIFT) | |
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| 115 | (6 << MS_Y4_SHIFT) | |
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| 116 | (6 << MS_X5_SHIFT) | |
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| 117 | (6 << MS_Y5_SHIFT) | |
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| 118 | (6 << MSBD1_SHIFT))); |
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| 2997 | Serge | 119 | radeon_ring_write(ring, PACKET0(GA_ENHANCE, 0)); |
| 120 | radeon_ring_write(ring, GA_DEADLOCK_CNTL | GA_FASTSYNC_CNTL); |
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| 121 | radeon_ring_write(ring, PACKET0(GA_POLY_MODE, 0)); |
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| 122 | radeon_ring_write(ring, FRONT_PTYPE_TRIANGE | BACK_PTYPE_TRIANGE); |
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| 123 | radeon_ring_write(ring, PACKET0(GA_ROUND_MODE, 0)); |
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| 124 | radeon_ring_write(ring, GEOMETRY_ROUND_NEAREST | COLOR_ROUND_NEAREST); |
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| 125 | radeon_ring_write(ring, PACKET0(0x20C8, 0)); |
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| 126 | radeon_ring_write(ring, 0); |
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| 127 | radeon_ring_unlock_commit(rdev, ring); |
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| 1117 | serge | 128 | } |
| 129 | |||
| 130 | int rv515_mc_wait_for_idle(struct radeon_device *rdev) |
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| 131 | { |
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| 132 | unsigned i; |
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| 133 | uint32_t tmp; |
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| 134 | |||
| 135 | for (i = 0; i < rdev->usec_timeout; i++) { |
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| 136 | /* read MC_STATUS */ |
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| 1179 | serge | 137 | tmp = RREG32_MC(MC_STATUS); |
| 138 | if (tmp & MC_STATUS_IDLE) { |
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| 1117 | serge | 139 | return 0; |
| 140 | } |
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| 141 | DRM_UDELAY(1); |
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| 142 | } |
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| 143 | return -1; |
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| 144 | } |
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| 145 | |||
| 1221 | serge | 146 | void rv515_vga_render_disable(struct radeon_device *rdev) |
| 147 | { |
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| 148 | WREG32(R_000300_VGA_RENDER_CONTROL, |
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| 149 | RREG32(R_000300_VGA_RENDER_CONTROL) & C_000300_VGA_VSTATUS_CNTL); |
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| 150 | } |
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| 151 | |||
| 2997 | Serge | 152 | static void rv515_gpu_init(struct radeon_device *rdev) |
| 1117 | serge | 153 | { |
| 154 | unsigned pipe_select_current, gb_pipe_select, tmp; |
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| 155 | |||
| 156 | if (r100_gui_wait_for_idle(rdev)) { |
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| 157 | printk(KERN_WARNING "Failed to wait GUI idle while " |
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| 2997 | Serge | 158 | "resetting GPU. Bad things might happen.\n"); |
| 1117 | serge | 159 | } |
| 1221 | serge | 160 | rv515_vga_render_disable(rdev); |
| 1117 | serge | 161 | r420_pipes_init(rdev); |
| 1963 | serge | 162 | gb_pipe_select = RREG32(R400_GB_PIPE_SELECT); |
| 163 | tmp = RREG32(R300_DST_PIPE_CONFIG); |
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| 1117 | serge | 164 | pipe_select_current = (tmp >> 2) & 3; |
| 165 | tmp = (1 << pipe_select_current) | |
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| 166 | (((gb_pipe_select >> 8) & 0xF) << 4); |
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| 167 | WREG32_PLL(0x000D, tmp); |
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| 168 | if (r100_gui_wait_for_idle(rdev)) { |
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| 169 | printk(KERN_WARNING "Failed to wait GUI idle while " |
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| 2997 | Serge | 170 | "resetting GPU. Bad things might happen.\n"); |
| 1117 | serge | 171 | } |
| 172 | if (rv515_mc_wait_for_idle(rdev)) { |
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| 173 | printk(KERN_WARNING "Failed to wait MC idle while " |
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| 174 | "programming pipes. Bad things might happen.\n"); |
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| 175 | } |
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| 176 | } |
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| 177 | |||
| 178 | static void rv515_vram_get_type(struct radeon_device *rdev) |
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| 179 | { |
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| 180 | uint32_t tmp; |
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| 181 | |||
| 182 | rdev->mc.vram_width = 128; |
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| 183 | rdev->mc.vram_is_ddr = true; |
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| 1179 | serge | 184 | tmp = RREG32_MC(RV515_MC_CNTL) & MEM_NUM_CHANNELS_MASK; |
| 1117 | serge | 185 | switch (tmp) { |
| 186 | case 0: |
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| 187 | rdev->mc.vram_width = 64; |
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| 188 | break; |
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| 189 | case 1: |
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| 190 | rdev->mc.vram_width = 128; |
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| 191 | break; |
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| 192 | default: |
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| 193 | rdev->mc.vram_width = 128; |
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| 194 | break; |
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| 195 | } |
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| 196 | } |
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| 197 | |||
| 2997 | Serge | 198 | static void rv515_mc_init(struct radeon_device *rdev) |
| 1117 | serge | 199 | { |
| 1179 | serge | 200 | |
| 1117 | serge | 201 | rv515_vram_get_type(rdev); |
| 1179 | serge | 202 | r100_vram_init_sizes(rdev); |
| 1430 | serge | 203 | radeon_vram_location(rdev, &rdev->mc, 0); |
| 1963 | serge | 204 | rdev->mc.gtt_base_align = 0; |
| 1430 | serge | 205 | if (!(rdev->flags & RADEON_IS_AGP)) |
| 206 | radeon_gtt_location(rdev, &rdev->mc); |
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| 1963 | serge | 207 | radeon_update_bandwidth_info(rdev); |
| 1117 | serge | 208 | } |
| 209 | |||
| 210 | uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg) |
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| 211 | { |
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| 212 | uint32_t r; |
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| 213 | |||
| 1179 | serge | 214 | WREG32(MC_IND_INDEX, 0x7f0000 | (reg & 0xffff)); |
| 215 | r = RREG32(MC_IND_DATA); |
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| 216 | WREG32(MC_IND_INDEX, 0); |
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| 1117 | serge | 217 | return r; |
| 218 | } |
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| 219 | |||
| 220 | void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
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| 221 | { |
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| 1179 | serge | 222 | WREG32(MC_IND_INDEX, 0xff0000 | ((reg) & 0xffff)); |
| 223 | WREG32(MC_IND_DATA, (v)); |
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| 224 | WREG32(MC_IND_INDEX, 0); |
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| 1117 | serge | 225 | } |
| 226 | |||
| 227 | #if defined(CONFIG_DEBUG_FS) |
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| 228 | static int rv515_debugfs_pipes_info(struct seq_file *m, void *data) |
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| 229 | { |
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| 230 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
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| 231 | struct drm_device *dev = node->minor->dev; |
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| 232 | struct radeon_device *rdev = dev->dev_private; |
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| 233 | uint32_t tmp; |
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| 234 | |||
| 1179 | serge | 235 | tmp = RREG32(GB_PIPE_SELECT); |
| 1117 | serge | 236 | seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp); |
| 1179 | serge | 237 | tmp = RREG32(SU_REG_DEST); |
| 1117 | serge | 238 | seq_printf(m, "SU_REG_DEST 0x%08x\n", tmp); |
| 1179 | serge | 239 | tmp = RREG32(GB_TILE_CONFIG); |
| 1117 | serge | 240 | seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp); |
| 1179 | serge | 241 | tmp = RREG32(DST_PIPE_CONFIG); |
| 1117 | serge | 242 | seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp); |
| 243 | return 0; |
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| 244 | } |
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| 245 | |||
| 246 | static int rv515_debugfs_ga_info(struct seq_file *m, void *data) |
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| 247 | { |
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| 248 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
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| 249 | struct drm_device *dev = node->minor->dev; |
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| 250 | struct radeon_device *rdev = dev->dev_private; |
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| 251 | uint32_t tmp; |
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| 252 | |||
| 253 | tmp = RREG32(0x2140); |
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| 254 | seq_printf(m, "VAP_CNTL_STATUS 0x%08x\n", tmp); |
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| 1963 | serge | 255 | radeon_asic_reset(rdev); |
| 1117 | serge | 256 | tmp = RREG32(0x425C); |
| 257 | seq_printf(m, "GA_IDLE 0x%08x\n", tmp); |
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| 258 | return 0; |
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| 259 | } |
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| 260 | |||
| 261 | static struct drm_info_list rv515_pipes_info_list[] = { |
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| 262 | {"rv515_pipes_info", rv515_debugfs_pipes_info, 0, NULL}, |
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| 263 | }; |
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| 264 | |||
| 265 | static struct drm_info_list rv515_ga_info_list[] = { |
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| 266 | {"rv515_ga_info", rv515_debugfs_ga_info, 0, NULL}, |
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| 267 | }; |
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| 268 | #endif |
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| 269 | |||
| 2997 | Serge | 270 | static int rv515_debugfs_pipes_info_init(struct radeon_device *rdev) |
| 1117 | serge | 271 | { |
| 272 | #if defined(CONFIG_DEBUG_FS) |
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| 273 | return radeon_debugfs_add_files(rdev, rv515_pipes_info_list, 1); |
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| 274 | #else |
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| 275 | return 0; |
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| 276 | #endif |
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| 277 | } |
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| 278 | |||
| 2997 | Serge | 279 | static int rv515_debugfs_ga_info_init(struct radeon_device *rdev) |
| 1117 | serge | 280 | { |
| 281 | #if defined(CONFIG_DEBUG_FS) |
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| 282 | return radeon_debugfs_add_files(rdev, rv515_ga_info_list, 1); |
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| 283 | #else |
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| 284 | return 0; |
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| 285 | #endif |
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| 286 | } |
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| 287 | |||
| 1221 | serge | 288 | void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save) |
| 1179 | serge | 289 | { |
| 3192 | Serge | 290 | u32 crtc_enabled, tmp, frame_count, blackout; |
| 291 | int i, j; |
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| 292 | |||
| 1221 | serge | 293 | save->vga_render_control = RREG32(R_000300_VGA_RENDER_CONTROL); |
| 294 | save->vga_hdp_control = RREG32(R_000328_VGA_HDP_CONTROL); |
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| 1179 | serge | 295 | |
| 3192 | Serge | 296 | /* disable VGA render */ |
| 1221 | serge | 297 | WREG32(R_000300_VGA_RENDER_CONTROL, 0); |
| 3192 | Serge | 298 | /* blank the display controllers */ |
| 299 | for (i = 0; i < rdev->num_crtc; i++) { |
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| 300 | crtc_enabled = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]) & AVIVO_CRTC_EN; |
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| 301 | if (crtc_enabled) { |
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| 302 | save->crtc_enabled[i] = true; |
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| 303 | tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]); |
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| 304 | if (!(tmp & AVIVO_CRTC_DISP_READ_REQUEST_DISABLE)) { |
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| 305 | radeon_wait_for_vblank(rdev, i); |
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| 3764 | Serge | 306 | WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 1); |
| 3192 | Serge | 307 | tmp |= AVIVO_CRTC_DISP_READ_REQUEST_DISABLE; |
| 308 | WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp); |
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| 3764 | Serge | 309 | WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 0); |
| 3192 | Serge | 310 | } |
| 311 | /* wait for the next frame */ |
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| 312 | frame_count = radeon_get_vblank_counter(rdev, i); |
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| 313 | for (j = 0; j < rdev->usec_timeout; j++) { |
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| 314 | if (radeon_get_vblank_counter(rdev, i) != frame_count) |
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| 315 | break; |
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| 316 | udelay(1); |
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| 317 | } |
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| 3764 | Serge | 318 | |
| 319 | /* XXX this is a hack to avoid strange behavior with EFI on certain systems */ |
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| 320 | WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 1); |
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| 321 | tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]); |
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| 322 | tmp &= ~AVIVO_CRTC_EN; |
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| 323 | WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp); |
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| 324 | WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 0); |
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| 325 | save->crtc_enabled[i] = false; |
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| 326 | /* ***** */ |
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| 3192 | Serge | 327 | } else { |
| 328 | save->crtc_enabled[i] = false; |
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| 329 | } |
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| 330 | } |
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| 331 | |||
| 332 | radeon_mc_wait_for_idle(rdev); |
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| 333 | |||
| 334 | if (rdev->family >= CHIP_R600) { |
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| 335 | if (rdev->family >= CHIP_RV770) |
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| 336 | blackout = RREG32(R700_MC_CITF_CNTL); |
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| 337 | else |
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| 338 | blackout = RREG32(R600_CITF_CNTL); |
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| 339 | if ((blackout & R600_BLACKOUT_MASK) != R600_BLACKOUT_MASK) { |
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| 340 | /* Block CPU access */ |
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| 341 | WREG32(R600_BIF_FB_EN, 0); |
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| 342 | /* blackout the MC */ |
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| 343 | blackout |= R600_BLACKOUT_MASK; |
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| 344 | if (rdev->family >= CHIP_RV770) |
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| 345 | WREG32(R700_MC_CITF_CNTL, blackout); |
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| 346 | else |
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| 347 | WREG32(R600_CITF_CNTL, blackout); |
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| 348 | } |
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| 349 | } |
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| 3764 | Serge | 350 | /* wait for the MC to settle */ |
| 351 | udelay(100); |
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| 352 | |||
| 353 | /* lock double buffered regs */ |
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| 354 | for (i = 0; i < rdev->num_crtc; i++) { |
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| 355 | if (save->crtc_enabled[i]) { |
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| 356 | tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]); |
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| 357 | if (!(tmp & AVIVO_D1GRPH_UPDATE_LOCK)) { |
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| 358 | tmp |= AVIVO_D1GRPH_UPDATE_LOCK; |
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| 359 | WREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i], tmp); |
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| 360 | } |
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| 361 | tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i]); |
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| 362 | if (!(tmp & 1)) { |
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| 363 | tmp |= 1; |
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| 364 | WREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp); |
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| 365 | } |
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| 366 | } |
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| 367 | } |
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| 1221 | serge | 368 | } |
| 369 | |||
| 370 | void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save) |
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| 371 | { |
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| 3192 | Serge | 372 | u32 tmp, frame_count; |
| 373 | int i, j; |
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| 374 | |||
| 375 | /* update crtc base addresses */ |
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| 376 | for (i = 0; i < rdev->num_crtc; i++) { |
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| 377 | if (rdev->family >= CHIP_RV770) { |
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| 3764 | Serge | 378 | if (i == 0) { |
| 3192 | Serge | 379 | WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, |
| 380 | upper_32_bits(rdev->mc.vram_start)); |
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| 381 | WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, |
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| 382 | upper_32_bits(rdev->mc.vram_start)); |
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| 383 | } else { |
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| 384 | WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, |
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| 385 | upper_32_bits(rdev->mc.vram_start)); |
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| 386 | WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, |
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| 387 | upper_32_bits(rdev->mc.vram_start)); |
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| 388 | } |
||
| 389 | } |
||
| 390 | WREG32(R_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i], |
||
| 391 | (u32)rdev->mc.vram_start); |
||
| 392 | WREG32(R_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i], |
||
| 393 | (u32)rdev->mc.vram_start); |
||
| 394 | } |
||
| 395 | WREG32(R_000310_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start); |
||
| 396 | |||
| 3764 | Serge | 397 | /* unlock regs and wait for update */ |
| 398 | for (i = 0; i < rdev->num_crtc; i++) { |
||
| 399 | if (save->crtc_enabled[i]) { |
||
| 400 | tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + crtc_offsets[i]); |
||
| 401 | if ((tmp & 0x3) != 0) { |
||
| 402 | tmp &= ~0x3; |
||
| 403 | WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + crtc_offsets[i], tmp); |
||
| 404 | } |
||
| 405 | tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]); |
||
| 406 | if (tmp & AVIVO_D1GRPH_UPDATE_LOCK) { |
||
| 407 | tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK; |
||
| 408 | WREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i], tmp); |
||
| 409 | } |
||
| 410 | tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i]); |
||
| 411 | if (tmp & 1) { |
||
| 412 | tmp &= ~1; |
||
| 413 | WREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp); |
||
| 414 | } |
||
| 415 | for (j = 0; j < rdev->usec_timeout; j++) { |
||
| 416 | tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]); |
||
| 417 | if ((tmp & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING) == 0) |
||
| 418 | break; |
||
| 419 | udelay(1); |
||
| 420 | } |
||
| 421 | } |
||
| 422 | } |
||
| 423 | |||
| 3192 | Serge | 424 | if (rdev->family >= CHIP_R600) { |
| 425 | /* unblackout the MC */ |
||
| 426 | if (rdev->family >= CHIP_RV770) |
||
| 427 | tmp = RREG32(R700_MC_CITF_CNTL); |
||
| 428 | else |
||
| 429 | tmp = RREG32(R600_CITF_CNTL); |
||
| 430 | tmp &= ~R600_BLACKOUT_MASK; |
||
| 431 | if (rdev->family >= CHIP_RV770) |
||
| 432 | WREG32(R700_MC_CITF_CNTL, tmp); |
||
| 433 | else |
||
| 434 | WREG32(R600_CITF_CNTL, tmp); |
||
| 435 | /* allow CPU access */ |
||
| 436 | WREG32(R600_BIF_FB_EN, R600_FB_READ_EN | R600_FB_WRITE_EN); |
||
| 437 | } |
||
| 438 | |||
| 439 | for (i = 0; i < rdev->num_crtc; i++) { |
||
| 440 | if (save->crtc_enabled[i]) { |
||
| 441 | tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]); |
||
| 442 | tmp &= ~AVIVO_CRTC_DISP_READ_REQUEST_DISABLE; |
||
| 443 | WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp); |
||
| 444 | /* wait for the next frame */ |
||
| 445 | frame_count = radeon_get_vblank_counter(rdev, i); |
||
| 446 | for (j = 0; j < rdev->usec_timeout; j++) { |
||
| 447 | if (radeon_get_vblank_counter(rdev, i) != frame_count) |
||
| 448 | break; |
||
| 449 | udelay(1); |
||
| 450 | } |
||
| 451 | } |
||
| 452 | } |
||
| 453 | /* Unlock vga access */ |
||
| 1221 | serge | 454 | WREG32(R_000328_VGA_HDP_CONTROL, save->vga_hdp_control); |
| 455 | mdelay(1); |
||
| 456 | WREG32(R_000300_VGA_RENDER_CONTROL, save->vga_render_control); |
||
| 457 | } |
||
| 458 | |||
| 2997 | Serge | 459 | static void rv515_mc_program(struct radeon_device *rdev) |
| 1221 | serge | 460 | { |
| 461 | struct rv515_mc_save save; |
||
| 462 | |||
| 463 | /* Stops all mc clients */ |
||
| 464 | rv515_mc_stop(rdev, &save); |
||
| 465 | |||
| 466 | /* Wait for mc idle */ |
||
| 467 | if (rv515_mc_wait_for_idle(rdev)) |
||
| 468 | dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); |
||
| 469 | /* Write VRAM size in case we are limiting it */ |
||
| 470 | WREG32(R_0000F8_CONFIG_MEMSIZE, rdev->mc.real_vram_size); |
||
| 471 | /* Program MC, should be a 32bits limited address space */ |
||
| 472 | WREG32_MC(R_000001_MC_FB_LOCATION, |
||
| 473 | S_000001_MC_FB_START(rdev->mc.vram_start >> 16) | |
||
| 474 | S_000001_MC_FB_TOP(rdev->mc.vram_end >> 16)); |
||
| 475 | WREG32(R_000134_HDP_FB_LOCATION, |
||
| 476 | S_000134_HDP_FB_START(rdev->mc.vram_start >> 16)); |
||
| 477 | if (rdev->flags & RADEON_IS_AGP) { |
||
| 478 | WREG32_MC(R_000002_MC_AGP_LOCATION, |
||
| 479 | S_000002_MC_AGP_START(rdev->mc.gtt_start >> 16) | |
||
| 480 | S_000002_MC_AGP_TOP(rdev->mc.gtt_end >> 16)); |
||
| 481 | WREG32_MC(R_000003_MC_AGP_BASE, lower_32_bits(rdev->mc.agp_base)); |
||
| 482 | WREG32_MC(R_000004_MC_AGP_BASE_2, |
||
| 483 | S_000004_AGP_BASE_ADDR_2(upper_32_bits(rdev->mc.agp_base))); |
||
| 484 | } else { |
||
| 485 | WREG32_MC(R_000002_MC_AGP_LOCATION, 0xFFFFFFFF); |
||
| 486 | WREG32_MC(R_000003_MC_AGP_BASE, 0); |
||
| 487 | WREG32_MC(R_000004_MC_AGP_BASE_2, 0); |
||
| 488 | } |
||
| 489 | |||
| 490 | rv515_mc_resume(rdev, &save); |
||
| 491 | } |
||
| 492 | |||
| 493 | void rv515_clock_startup(struct radeon_device *rdev) |
||
| 494 | { |
||
| 495 | if (radeon_dynclks != -1 && radeon_dynclks) |
||
| 496 | radeon_atom_set_clock_gating(rdev, 1); |
||
| 497 | /* We need to force on some of the block */ |
||
| 498 | WREG32_PLL(R_00000F_CP_DYN_CNTL, |
||
| 499 | RREG32_PLL(R_00000F_CP_DYN_CNTL) | S_00000F_CP_FORCEON(1)); |
||
| 500 | WREG32_PLL(R_000011_E2_DYN_CNTL, |
||
| 501 | RREG32_PLL(R_000011_E2_DYN_CNTL) | S_000011_E2_FORCEON(1)); |
||
| 502 | WREG32_PLL(R_000013_IDCT_DYN_CNTL, |
||
| 503 | RREG32_PLL(R_000013_IDCT_DYN_CNTL) | S_000013_IDCT_FORCEON(1)); |
||
| 504 | } |
||
| 505 | |||
| 506 | static int rv515_startup(struct radeon_device *rdev) |
||
| 507 | { |
||
| 508 | int r; |
||
| 509 | |||
| 510 | rv515_mc_program(rdev); |
||
| 511 | /* Resume clock */ |
||
| 512 | rv515_clock_startup(rdev); |
||
| 513 | /* Initialize GPU configuration (# pipes, ...) */ |
||
| 514 | rv515_gpu_init(rdev); |
||
| 515 | /* Initialize GART (initialize after TTM so we can allocate |
||
| 516 | * memory through TTM but finalize after TTM) */ |
||
| 517 | if (rdev->flags & RADEON_IS_PCIE) { |
||
| 518 | r = rv370_pcie_gart_enable(rdev); |
||
| 519 | if (r) |
||
| 520 | return r; |
||
| 521 | } |
||
| 2005 | serge | 522 | |
| 523 | /* allocate wb buffer */ |
||
| 524 | r = radeon_wb_init(rdev); |
||
| 525 | if (r) |
||
| 526 | return r; |
||
| 527 | |||
| 3120 | serge | 528 | r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); |
| 529 | if (r) { |
||
| 530 | dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); |
||
| 531 | return r; |
||
| 532 | } |
||
| 533 | |||
| 1221 | serge | 534 | /* Enable IRQ */ |
| 3764 | Serge | 535 | if (!rdev->irq.installed) { |
| 536 | r = radeon_irq_kms_init(rdev); |
||
| 537 | if (r) |
||
| 538 | return r; |
||
| 539 | } |
||
| 540 | |||
| 2005 | serge | 541 | rs600_irq_set(rdev); |
| 1403 | serge | 542 | rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); |
| 1221 | serge | 543 | /* 1M ring buffer */ |
| 1413 | serge | 544 | r = r100_cp_init(rdev, 1024 * 1024); |
| 545 | if (r) { |
||
| 1963 | serge | 546 | dev_err(rdev->dev, "failed initializing CP (%d).\n", r); |
| 1413 | serge | 547 | return r; |
| 548 | } |
||
| 2997 | Serge | 549 | |
| 550 | r = radeon_ib_pool_init(rdev); |
||
| 2005 | serge | 551 | if (r) { |
| 2997 | Serge | 552 | dev_err(rdev->dev, "IB initialization failed (%d).\n", r); |
| 2005 | serge | 553 | return r; |
| 554 | } |
||
| 2997 | Serge | 555 | |
| 1221 | serge | 556 | return 0; |
| 557 | } |
||
| 558 | |||
| 559 | |||
| 560 | void rv515_set_safe_registers(struct radeon_device *rdev) |
||
| 561 | { |
||
| 1179 | serge | 562 | rdev->config.r300.reg_safe_bm = rv515_reg_safe_bm; |
| 563 | rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rv515_reg_safe_bm); |
||
| 1221 | serge | 564 | } |
| 565 | |||
| 566 | int rv515_init(struct radeon_device *rdev) |
||
| 567 | { |
||
| 568 | int r; |
||
| 569 | |||
| 570 | /* Initialize scratch registers */ |
||
| 571 | radeon_scratch_init(rdev); |
||
| 572 | /* Initialize surface registers */ |
||
| 573 | radeon_surface_init(rdev); |
||
| 574 | /* TODO: disable VGA need to use VGA request */ |
||
| 1963 | serge | 575 | /* restore some register to sane defaults */ |
| 576 | r100_restore_sanity(rdev); |
||
| 1221 | serge | 577 | /* BIOS*/ |
| 578 | if (!radeon_get_bios(rdev)) { |
||
| 579 | if (ASIC_IS_AVIVO(rdev)) |
||
| 580 | return -EINVAL; |
||
| 581 | } |
||
| 582 | if (rdev->is_atom_bios) { |
||
| 583 | r = radeon_atombios_init(rdev); |
||
| 584 | if (r) |
||
| 585 | return r; |
||
| 586 | } else { |
||
| 587 | dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n"); |
||
| 588 | return -EINVAL; |
||
| 589 | } |
||
| 590 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ |
||
| 1963 | serge | 591 | if (radeon_asic_reset(rdev)) { |
| 1221 | serge | 592 | dev_warn(rdev->dev, |
| 593 | "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", |
||
| 594 | RREG32(R_000E40_RBBM_STATUS), |
||
| 595 | RREG32(R_0007C0_CP_STAT)); |
||
| 596 | } |
||
| 597 | /* check if cards are posted or not */ |
||
| 1403 | serge | 598 | if (radeon_boot_test_post_card(rdev) == false) |
| 599 | return -EINVAL; |
||
| 1221 | serge | 600 | /* Initialize clocks */ |
| 601 | radeon_get_clock_info(rdev->ddev); |
||
| 1430 | serge | 602 | /* initialize AGP */ |
| 603 | if (rdev->flags & RADEON_IS_AGP) { |
||
| 604 | r = radeon_agp_init(rdev); |
||
| 605 | if (r) { |
||
| 606 | radeon_agp_disable(rdev); |
||
| 607 | } |
||
| 608 | } |
||
| 609 | /* initialize memory controller */ |
||
| 610 | rv515_mc_init(rdev); |
||
| 1221 | serge | 611 | rv515_debugfs(rdev); |
| 612 | /* Fence driver */ |
||
| 2005 | serge | 613 | r = radeon_fence_driver_init(rdev); |
| 614 | if (r) |
||
| 615 | return r; |
||
| 1221 | serge | 616 | /* Memory manager */ |
| 1403 | serge | 617 | r = radeon_bo_init(rdev); |
| 1221 | serge | 618 | if (r) |
| 619 | return r; |
||
| 620 | r = rv370_pcie_gart_init(rdev); |
||
| 621 | if (r) |
||
| 622 | return r; |
||
| 623 | rv515_set_safe_registers(rdev); |
||
| 2997 | Serge | 624 | |
| 1221 | serge | 625 | rdev->accel_working = true; |
| 626 | r = rv515_startup(rdev); |
||
| 627 | if (r) { |
||
| 628 | /* Somethings want wront with the accel init stop accel */ |
||
| 629 | dev_err(rdev->dev, "Disabling GPU acceleration\n"); |
||
| 630 | rdev->accel_working = false; |
||
| 631 | } |
||
| 1179 | serge | 632 | return 0; |
| 633 | } |
||
| 634 | |||
| 635 | void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *crtc) |
||
| 636 | { |
||
| 637 | int index_reg = 0x6578 + crtc->crtc_offset; |
||
| 638 | int data_reg = 0x657c + crtc->crtc_offset; |
||
| 639 | |||
| 640 | WREG32(0x659C + crtc->crtc_offset, 0x0); |
||
| 641 | WREG32(0x6594 + crtc->crtc_offset, 0x705); |
||
| 642 | WREG32(0x65A4 + crtc->crtc_offset, 0x10001); |
||
| 643 | WREG32(0x65D8 + crtc->crtc_offset, 0x0); |
||
| 644 | WREG32(0x65B0 + crtc->crtc_offset, 0x0); |
||
| 645 | WREG32(0x65C0 + crtc->crtc_offset, 0x0); |
||
| 646 | WREG32(0x65D4 + crtc->crtc_offset, 0x0); |
||
| 647 | WREG32(index_reg, 0x0); |
||
| 648 | WREG32(data_reg, 0x841880A8); |
||
| 649 | WREG32(index_reg, 0x1); |
||
| 650 | WREG32(data_reg, 0x84208680); |
||
| 651 | WREG32(index_reg, 0x2); |
||
| 652 | WREG32(data_reg, 0xBFF880B0); |
||
| 653 | WREG32(index_reg, 0x100); |
||
| 654 | WREG32(data_reg, 0x83D88088); |
||
| 655 | WREG32(index_reg, 0x101); |
||
| 656 | WREG32(data_reg, 0x84608680); |
||
| 657 | WREG32(index_reg, 0x102); |
||
| 658 | WREG32(data_reg, 0xBFF080D0); |
||
| 659 | WREG32(index_reg, 0x200); |
||
| 660 | WREG32(data_reg, 0x83988068); |
||
| 661 | WREG32(index_reg, 0x201); |
||
| 662 | WREG32(data_reg, 0x84A08680); |
||
| 663 | WREG32(index_reg, 0x202); |
||
| 664 | WREG32(data_reg, 0xBFF080F8); |
||
| 665 | WREG32(index_reg, 0x300); |
||
| 666 | WREG32(data_reg, 0x83588058); |
||
| 667 | WREG32(index_reg, 0x301); |
||
| 668 | WREG32(data_reg, 0x84E08660); |
||
| 669 | WREG32(index_reg, 0x302); |
||
| 670 | WREG32(data_reg, 0xBFF88120); |
||
| 671 | WREG32(index_reg, 0x400); |
||
| 672 | WREG32(data_reg, 0x83188040); |
||
| 673 | WREG32(index_reg, 0x401); |
||
| 674 | WREG32(data_reg, 0x85008660); |
||
| 675 | WREG32(index_reg, 0x402); |
||
| 676 | WREG32(data_reg, 0xBFF88150); |
||
| 677 | WREG32(index_reg, 0x500); |
||
| 678 | WREG32(data_reg, 0x82D88030); |
||
| 679 | WREG32(index_reg, 0x501); |
||
| 680 | WREG32(data_reg, 0x85408640); |
||
| 681 | WREG32(index_reg, 0x502); |
||
| 682 | WREG32(data_reg, 0xBFF88180); |
||
| 683 | WREG32(index_reg, 0x600); |
||
| 684 | WREG32(data_reg, 0x82A08018); |
||
| 685 | WREG32(index_reg, 0x601); |
||
| 686 | WREG32(data_reg, 0x85808620); |
||
| 687 | WREG32(index_reg, 0x602); |
||
| 688 | WREG32(data_reg, 0xBFF081B8); |
||
| 689 | WREG32(index_reg, 0x700); |
||
| 690 | WREG32(data_reg, 0x82608010); |
||
| 691 | WREG32(index_reg, 0x701); |
||
| 692 | WREG32(data_reg, 0x85A08600); |
||
| 693 | WREG32(index_reg, 0x702); |
||
| 694 | WREG32(data_reg, 0x800081F0); |
||
| 695 | WREG32(index_reg, 0x800); |
||
| 696 | WREG32(data_reg, 0x8228BFF8); |
||
| 697 | WREG32(index_reg, 0x801); |
||
| 698 | WREG32(data_reg, 0x85E085E0); |
||
| 699 | WREG32(index_reg, 0x802); |
||
| 700 | WREG32(data_reg, 0xBFF88228); |
||
| 701 | WREG32(index_reg, 0x10000); |
||
| 702 | WREG32(data_reg, 0x82A8BF00); |
||
| 703 | WREG32(index_reg, 0x10001); |
||
| 704 | WREG32(data_reg, 0x82A08CC0); |
||
| 705 | WREG32(index_reg, 0x10002); |
||
| 706 | WREG32(data_reg, 0x8008BEF8); |
||
| 707 | WREG32(index_reg, 0x10100); |
||
| 708 | WREG32(data_reg, 0x81F0BF28); |
||
| 709 | WREG32(index_reg, 0x10101); |
||
| 710 | WREG32(data_reg, 0x83608CA0); |
||
| 711 | WREG32(index_reg, 0x10102); |
||
| 712 | WREG32(data_reg, 0x8018BED0); |
||
| 713 | WREG32(index_reg, 0x10200); |
||
| 714 | WREG32(data_reg, 0x8148BF38); |
||
| 715 | WREG32(index_reg, 0x10201); |
||
| 716 | WREG32(data_reg, 0x84408C80); |
||
| 717 | WREG32(index_reg, 0x10202); |
||
| 718 | WREG32(data_reg, 0x8008BEB8); |
||
| 719 | WREG32(index_reg, 0x10300); |
||
| 720 | WREG32(data_reg, 0x80B0BF78); |
||
| 721 | WREG32(index_reg, 0x10301); |
||
| 722 | WREG32(data_reg, 0x85008C20); |
||
| 723 | WREG32(index_reg, 0x10302); |
||
| 724 | WREG32(data_reg, 0x8020BEA0); |
||
| 725 | WREG32(index_reg, 0x10400); |
||
| 726 | WREG32(data_reg, 0x8028BF90); |
||
| 727 | WREG32(index_reg, 0x10401); |
||
| 728 | WREG32(data_reg, 0x85E08BC0); |
||
| 729 | WREG32(index_reg, 0x10402); |
||
| 730 | WREG32(data_reg, 0x8018BE90); |
||
| 731 | WREG32(index_reg, 0x10500); |
||
| 732 | WREG32(data_reg, 0xBFB8BFB0); |
||
| 733 | WREG32(index_reg, 0x10501); |
||
| 734 | WREG32(data_reg, 0x86C08B40); |
||
| 735 | WREG32(index_reg, 0x10502); |
||
| 736 | WREG32(data_reg, 0x8010BE90); |
||
| 737 | WREG32(index_reg, 0x10600); |
||
| 738 | WREG32(data_reg, 0xBF58BFC8); |
||
| 739 | WREG32(index_reg, 0x10601); |
||
| 740 | WREG32(data_reg, 0x87A08AA0); |
||
| 741 | WREG32(index_reg, 0x10602); |
||
| 742 | WREG32(data_reg, 0x8010BE98); |
||
| 743 | WREG32(index_reg, 0x10700); |
||
| 744 | WREG32(data_reg, 0xBF10BFF0); |
||
| 745 | WREG32(index_reg, 0x10701); |
||
| 746 | WREG32(data_reg, 0x886089E0); |
||
| 747 | WREG32(index_reg, 0x10702); |
||
| 748 | WREG32(data_reg, 0x8018BEB0); |
||
| 749 | WREG32(index_reg, 0x10800); |
||
| 750 | WREG32(data_reg, 0xBED8BFE8); |
||
| 751 | WREG32(index_reg, 0x10801); |
||
| 752 | WREG32(data_reg, 0x89408940); |
||
| 753 | WREG32(index_reg, 0x10802); |
||
| 754 | WREG32(data_reg, 0xBFE8BED8); |
||
| 755 | WREG32(index_reg, 0x20000); |
||
| 756 | WREG32(data_reg, 0x80008000); |
||
| 757 | WREG32(index_reg, 0x20001); |
||
| 758 | WREG32(data_reg, 0x90008000); |
||
| 759 | WREG32(index_reg, 0x20002); |
||
| 760 | WREG32(data_reg, 0x80008000); |
||
| 761 | WREG32(index_reg, 0x20003); |
||
| 762 | WREG32(data_reg, 0x80008000); |
||
| 763 | WREG32(index_reg, 0x20100); |
||
| 764 | WREG32(data_reg, 0x80108000); |
||
| 765 | WREG32(index_reg, 0x20101); |
||
| 766 | WREG32(data_reg, 0x8FE0BF70); |
||
| 767 | WREG32(index_reg, 0x20102); |
||
| 768 | WREG32(data_reg, 0xBFE880C0); |
||
| 769 | WREG32(index_reg, 0x20103); |
||
| 770 | WREG32(data_reg, 0x80008000); |
||
| 771 | WREG32(index_reg, 0x20200); |
||
| 772 | WREG32(data_reg, 0x8018BFF8); |
||
| 773 | WREG32(index_reg, 0x20201); |
||
| 774 | WREG32(data_reg, 0x8F80BF08); |
||
| 775 | WREG32(index_reg, 0x20202); |
||
| 776 | WREG32(data_reg, 0xBFD081A0); |
||
| 777 | WREG32(index_reg, 0x20203); |
||
| 778 | WREG32(data_reg, 0xBFF88000); |
||
| 779 | WREG32(index_reg, 0x20300); |
||
| 780 | WREG32(data_reg, 0x80188000); |
||
| 781 | WREG32(index_reg, 0x20301); |
||
| 782 | WREG32(data_reg, 0x8EE0BEC0); |
||
| 783 | WREG32(index_reg, 0x20302); |
||
| 784 | WREG32(data_reg, 0xBFB082A0); |
||
| 785 | WREG32(index_reg, 0x20303); |
||
| 786 | WREG32(data_reg, 0x80008000); |
||
| 787 | WREG32(index_reg, 0x20400); |
||
| 788 | WREG32(data_reg, 0x80188000); |
||
| 789 | WREG32(index_reg, 0x20401); |
||
| 790 | WREG32(data_reg, 0x8E00BEA0); |
||
| 791 | WREG32(index_reg, 0x20402); |
||
| 792 | WREG32(data_reg, 0xBF8883C0); |
||
| 793 | WREG32(index_reg, 0x20403); |
||
| 794 | WREG32(data_reg, 0x80008000); |
||
| 795 | WREG32(index_reg, 0x20500); |
||
| 796 | WREG32(data_reg, 0x80188000); |
||
| 797 | WREG32(index_reg, 0x20501); |
||
| 798 | WREG32(data_reg, 0x8D00BE90); |
||
| 799 | WREG32(index_reg, 0x20502); |
||
| 800 | WREG32(data_reg, 0xBF588500); |
||
| 801 | WREG32(index_reg, 0x20503); |
||
| 802 | WREG32(data_reg, 0x80008008); |
||
| 803 | WREG32(index_reg, 0x20600); |
||
| 804 | WREG32(data_reg, 0x80188000); |
||
| 805 | WREG32(index_reg, 0x20601); |
||
| 806 | WREG32(data_reg, 0x8BC0BE98); |
||
| 807 | WREG32(index_reg, 0x20602); |
||
| 808 | WREG32(data_reg, 0xBF308660); |
||
| 809 | WREG32(index_reg, 0x20603); |
||
| 810 | WREG32(data_reg, 0x80008008); |
||
| 811 | WREG32(index_reg, 0x20700); |
||
| 812 | WREG32(data_reg, 0x80108000); |
||
| 813 | WREG32(index_reg, 0x20701); |
||
| 814 | WREG32(data_reg, 0x8A80BEB0); |
||
| 815 | WREG32(index_reg, 0x20702); |
||
| 816 | WREG32(data_reg, 0xBF0087C0); |
||
| 817 | WREG32(index_reg, 0x20703); |
||
| 818 | WREG32(data_reg, 0x80008008); |
||
| 819 | WREG32(index_reg, 0x20800); |
||
| 820 | WREG32(data_reg, 0x80108000); |
||
| 821 | WREG32(index_reg, 0x20801); |
||
| 822 | WREG32(data_reg, 0x8920BED0); |
||
| 823 | WREG32(index_reg, 0x20802); |
||
| 824 | WREG32(data_reg, 0xBED08920); |
||
| 825 | WREG32(index_reg, 0x20803); |
||
| 826 | WREG32(data_reg, 0x80008010); |
||
| 827 | WREG32(index_reg, 0x30000); |
||
| 828 | WREG32(data_reg, 0x90008000); |
||
| 829 | WREG32(index_reg, 0x30001); |
||
| 830 | WREG32(data_reg, 0x80008000); |
||
| 831 | WREG32(index_reg, 0x30100); |
||
| 832 | WREG32(data_reg, 0x8FE0BF90); |
||
| 833 | WREG32(index_reg, 0x30101); |
||
| 834 | WREG32(data_reg, 0xBFF880A0); |
||
| 835 | WREG32(index_reg, 0x30200); |
||
| 836 | WREG32(data_reg, 0x8F60BF40); |
||
| 837 | WREG32(index_reg, 0x30201); |
||
| 838 | WREG32(data_reg, 0xBFE88180); |
||
| 839 | WREG32(index_reg, 0x30300); |
||
| 840 | WREG32(data_reg, 0x8EC0BF00); |
||
| 841 | WREG32(index_reg, 0x30301); |
||
| 842 | WREG32(data_reg, 0xBFC88280); |
||
| 843 | WREG32(index_reg, 0x30400); |
||
| 844 | WREG32(data_reg, 0x8DE0BEE0); |
||
| 845 | WREG32(index_reg, 0x30401); |
||
| 846 | WREG32(data_reg, 0xBFA083A0); |
||
| 847 | WREG32(index_reg, 0x30500); |
||
| 848 | WREG32(data_reg, 0x8CE0BED0); |
||
| 849 | WREG32(index_reg, 0x30501); |
||
| 850 | WREG32(data_reg, 0xBF7884E0); |
||
| 851 | WREG32(index_reg, 0x30600); |
||
| 852 | WREG32(data_reg, 0x8BA0BED8); |
||
| 853 | WREG32(index_reg, 0x30601); |
||
| 854 | WREG32(data_reg, 0xBF508640); |
||
| 855 | WREG32(index_reg, 0x30700); |
||
| 856 | WREG32(data_reg, 0x8A60BEE8); |
||
| 857 | WREG32(index_reg, 0x30701); |
||
| 858 | WREG32(data_reg, 0xBF2087A0); |
||
| 859 | WREG32(index_reg, 0x30800); |
||
| 860 | WREG32(data_reg, 0x8900BF00); |
||
| 861 | WREG32(index_reg, 0x30801); |
||
| 862 | WREG32(data_reg, 0xBF008900); |
||
| 863 | } |
||
| 864 | |||
| 865 | struct rv515_watermark { |
||
| 866 | u32 lb_request_fifo_depth; |
||
| 867 | fixed20_12 num_line_pair; |
||
| 868 | fixed20_12 estimated_width; |
||
| 869 | fixed20_12 worst_case_latency; |
||
| 870 | fixed20_12 consumption_rate; |
||
| 871 | fixed20_12 active_time; |
||
| 872 | fixed20_12 dbpp; |
||
| 873 | fixed20_12 priority_mark_max; |
||
| 874 | fixed20_12 priority_mark; |
||
| 875 | fixed20_12 sclk; |
||
| 1117 | serge | 876 | }; |
| 877 | |||
| 2997 | Serge | 878 | static void rv515_crtc_bandwidth_compute(struct radeon_device *rdev, |
| 1179 | serge | 879 | struct radeon_crtc *crtc, |
| 880 | struct rv515_watermark *wm) |
||
| 881 | { |
||
| 882 | struct drm_display_mode *mode = &crtc->base.mode; |
||
| 883 | fixed20_12 a, b, c; |
||
| 884 | fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width; |
||
| 885 | fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency; |
||
| 1117 | serge | 886 | |
| 1179 | serge | 887 | if (!crtc->base.enabled) { |
| 888 | /* FIXME: wouldn't it better to set priority mark to maximum */ |
||
| 889 | wm->lb_request_fifo_depth = 4; |
||
| 890 | return; |
||
| 891 | } |
||
| 1117 | serge | 892 | |
| 1963 | serge | 893 | if (crtc->vsc.full > dfixed_const(2)) |
| 894 | wm->num_line_pair.full = dfixed_const(2); |
||
| 1179 | serge | 895 | else |
| 1963 | serge | 896 | wm->num_line_pair.full = dfixed_const(1); |
| 1179 | serge | 897 | |
| 1963 | serge | 898 | b.full = dfixed_const(mode->crtc_hdisplay); |
| 899 | c.full = dfixed_const(256); |
||
| 900 | a.full = dfixed_div(b, c); |
||
| 901 | request_fifo_depth.full = dfixed_mul(a, wm->num_line_pair); |
||
| 902 | request_fifo_depth.full = dfixed_ceil(request_fifo_depth); |
||
| 903 | if (a.full < dfixed_const(4)) { |
||
| 1179 | serge | 904 | wm->lb_request_fifo_depth = 4; |
| 905 | } else { |
||
| 1963 | serge | 906 | wm->lb_request_fifo_depth = dfixed_trunc(request_fifo_depth); |
| 1179 | serge | 907 | } |
| 908 | |||
| 909 | /* Determine consumption rate |
||
| 910 | * pclk = pixel clock period(ns) = 1000 / (mode.clock / 1000) |
||
| 911 | * vtaps = number of vertical taps, |
||
| 912 | * vsc = vertical scaling ratio, defined as source/destination |
||
| 913 | * hsc = horizontal scaling ration, defined as source/destination |
||
| 914 | */ |
||
| 1963 | serge | 915 | a.full = dfixed_const(mode->clock); |
| 916 | b.full = dfixed_const(1000); |
||
| 917 | a.full = dfixed_div(a, b); |
||
| 918 | pclk.full = dfixed_div(b, a); |
||
| 1179 | serge | 919 | if (crtc->rmx_type != RMX_OFF) { |
| 1963 | serge | 920 | b.full = dfixed_const(2); |
| 1179 | serge | 921 | if (crtc->vsc.full > b.full) |
| 922 | b.full = crtc->vsc.full; |
||
| 1963 | serge | 923 | b.full = dfixed_mul(b, crtc->hsc); |
| 924 | c.full = dfixed_const(2); |
||
| 925 | b.full = dfixed_div(b, c); |
||
| 926 | consumption_time.full = dfixed_div(pclk, b); |
||
| 1179 | serge | 927 | } else { |
| 928 | consumption_time.full = pclk.full; |
||
| 929 | } |
||
| 1963 | serge | 930 | a.full = dfixed_const(1); |
| 931 | wm->consumption_rate.full = dfixed_div(a, consumption_time); |
||
| 1179 | serge | 932 | |
| 933 | |||
| 934 | /* Determine line time |
||
| 935 | * LineTime = total time for one line of displayhtotal |
||
| 936 | * LineTime = total number of horizontal pixels |
||
| 937 | * pclk = pixel clock period(ns) |
||
| 938 | */ |
||
| 1963 | serge | 939 | a.full = dfixed_const(crtc->base.mode.crtc_htotal); |
| 940 | line_time.full = dfixed_mul(a, pclk); |
||
| 1179 | serge | 941 | |
| 942 | /* Determine active time |
||
| 943 | * ActiveTime = time of active region of display within one line, |
||
| 944 | * hactive = total number of horizontal active pixels |
||
| 945 | * htotal = total number of horizontal pixels |
||
| 946 | */ |
||
| 1963 | serge | 947 | a.full = dfixed_const(crtc->base.mode.crtc_htotal); |
| 948 | b.full = dfixed_const(crtc->base.mode.crtc_hdisplay); |
||
| 949 | wm->active_time.full = dfixed_mul(line_time, b); |
||
| 950 | wm->active_time.full = dfixed_div(wm->active_time, a); |
||
| 1179 | serge | 951 | |
| 952 | /* Determine chunk time |
||
| 953 | * ChunkTime = the time it takes the DCP to send one chunk of data |
||
| 954 | * to the LB which consists of pipeline delay and inter chunk gap |
||
| 955 | * sclk = system clock(Mhz) |
||
| 956 | */ |
||
| 1963 | serge | 957 | a.full = dfixed_const(600 * 1000); |
| 958 | chunk_time.full = dfixed_div(a, rdev->pm.sclk); |
||
| 959 | read_delay_latency.full = dfixed_const(1000); |
||
| 1179 | serge | 960 | |
| 961 | /* Determine the worst case latency |
||
| 962 | * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines) |
||
| 963 | * WorstCaseLatency = worst case time from urgent to when the MC starts |
||
| 964 | * to return data |
||
| 965 | * READ_DELAY_IDLE_MAX = constant of 1us |
||
| 966 | * ChunkTime = time it takes the DCP to send one chunk of data to the LB |
||
| 967 | * which consists of pipeline delay and inter chunk gap |
||
| 968 | */ |
||
| 1963 | serge | 969 | if (dfixed_trunc(wm->num_line_pair) > 1) { |
| 970 | a.full = dfixed_const(3); |
||
| 971 | wm->worst_case_latency.full = dfixed_mul(a, chunk_time); |
||
| 1179 | serge | 972 | wm->worst_case_latency.full += read_delay_latency.full; |
| 973 | } else { |
||
| 974 | wm->worst_case_latency.full = chunk_time.full + read_delay_latency.full; |
||
| 975 | } |
||
| 976 | |||
| 977 | /* Determine the tolerable latency |
||
| 978 | * TolerableLatency = Any given request has only 1 line time |
||
| 979 | * for the data to be returned |
||
| 980 | * LBRequestFifoDepth = Number of chunk requests the LB can |
||
| 981 | * put into the request FIFO for a display |
||
| 982 | * LineTime = total time for one line of display |
||
| 983 | * ChunkTime = the time it takes the DCP to send one chunk |
||
| 984 | * of data to the LB which consists of |
||
| 985 | * pipeline delay and inter chunk gap |
||
| 986 | */ |
||
| 1963 | serge | 987 | if ((2+wm->lb_request_fifo_depth) >= dfixed_trunc(request_fifo_depth)) { |
| 1179 | serge | 988 | tolerable_latency.full = line_time.full; |
| 989 | } else { |
||
| 1963 | serge | 990 | tolerable_latency.full = dfixed_const(wm->lb_request_fifo_depth - 2); |
| 1179 | serge | 991 | tolerable_latency.full = request_fifo_depth.full - tolerable_latency.full; |
| 1963 | serge | 992 | tolerable_latency.full = dfixed_mul(tolerable_latency, chunk_time); |
| 1179 | serge | 993 | tolerable_latency.full = line_time.full - tolerable_latency.full; |
| 994 | } |
||
| 995 | /* We assume worst case 32bits (4 bytes) */ |
||
| 1963 | serge | 996 | wm->dbpp.full = dfixed_const(2 * 16); |
| 1179 | serge | 997 | |
| 998 | /* Determine the maximum priority mark |
||
| 999 | * width = viewport width in pixels |
||
| 1000 | */ |
||
| 1963 | serge | 1001 | a.full = dfixed_const(16); |
| 1002 | wm->priority_mark_max.full = dfixed_const(crtc->base.mode.crtc_hdisplay); |
||
| 1003 | wm->priority_mark_max.full = dfixed_div(wm->priority_mark_max, a); |
||
| 1004 | wm->priority_mark_max.full = dfixed_ceil(wm->priority_mark_max); |
||
| 1179 | serge | 1005 | |
| 1006 | /* Determine estimated width */ |
||
| 1007 | estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full; |
||
| 1963 | serge | 1008 | estimated_width.full = dfixed_div(estimated_width, consumption_time); |
| 1009 | if (dfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) { |
||
| 1403 | serge | 1010 | wm->priority_mark.full = wm->priority_mark_max.full; |
| 1179 | serge | 1011 | } else { |
| 1963 | serge | 1012 | a.full = dfixed_const(16); |
| 1013 | wm->priority_mark.full = dfixed_div(estimated_width, a); |
||
| 1014 | wm->priority_mark.full = dfixed_ceil(wm->priority_mark); |
||
| 1179 | serge | 1015 | wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full; |
| 1016 | } |
||
| 1017 | } |
||
| 1018 | |||
| 1019 | void rv515_bandwidth_avivo_update(struct radeon_device *rdev) |
||
| 1117 | serge | 1020 | { |
| 1179 | serge | 1021 | struct drm_display_mode *mode0 = NULL; |
| 1022 | struct drm_display_mode *mode1 = NULL; |
||
| 1023 | struct rv515_watermark wm0; |
||
| 1024 | struct rv515_watermark wm1; |
||
| 1025 | u32 tmp; |
||
| 1963 | serge | 1026 | u32 d1mode_priority_a_cnt = MODE_PRIORITY_OFF; |
| 1027 | u32 d2mode_priority_a_cnt = MODE_PRIORITY_OFF; |
||
| 1179 | serge | 1028 | fixed20_12 priority_mark02, priority_mark12, fill_rate; |
| 1029 | fixed20_12 a, b; |
||
| 1117 | serge | 1030 | |
| 1179 | serge | 1031 | if (rdev->mode_info.crtcs[0]->base.enabled) |
| 1032 | mode0 = &rdev->mode_info.crtcs[0]->base.mode; |
||
| 1033 | if (rdev->mode_info.crtcs[1]->base.enabled) |
||
| 1034 | mode1 = &rdev->mode_info.crtcs[1]->base.mode; |
||
| 1035 | rs690_line_buffer_adjust(rdev, mode0, mode1); |
||
| 1036 | |||
| 1037 | rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0); |
||
| 1038 | rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1); |
||
| 1039 | |||
| 1040 | tmp = wm0.lb_request_fifo_depth; |
||
| 1041 | tmp |= wm1.lb_request_fifo_depth << 16; |
||
| 1042 | WREG32(LB_MAX_REQ_OUTSTANDING, tmp); |
||
| 1043 | |||
| 1044 | if (mode0 && mode1) { |
||
| 1963 | serge | 1045 | if (dfixed_trunc(wm0.dbpp) > 64) |
| 1046 | a.full = dfixed_div(wm0.dbpp, wm0.num_line_pair); |
||
| 1179 | serge | 1047 | else |
| 1048 | a.full = wm0.num_line_pair.full; |
||
| 1963 | serge | 1049 | if (dfixed_trunc(wm1.dbpp) > 64) |
| 1050 | b.full = dfixed_div(wm1.dbpp, wm1.num_line_pair); |
||
| 1179 | serge | 1051 | else |
| 1052 | b.full = wm1.num_line_pair.full; |
||
| 1053 | a.full += b.full; |
||
| 1963 | serge | 1054 | fill_rate.full = dfixed_div(wm0.sclk, a); |
| 1179 | serge | 1055 | if (wm0.consumption_rate.full > fill_rate.full) { |
| 1056 | b.full = wm0.consumption_rate.full - fill_rate.full; |
||
| 1963 | serge | 1057 | b.full = dfixed_mul(b, wm0.active_time); |
| 1058 | a.full = dfixed_const(16); |
||
| 1059 | b.full = dfixed_div(b, a); |
||
| 1060 | a.full = dfixed_mul(wm0.worst_case_latency, |
||
| 1179 | serge | 1061 | wm0.consumption_rate); |
| 1062 | priority_mark02.full = a.full + b.full; |
||
| 1063 | } else { |
||
| 1963 | serge | 1064 | a.full = dfixed_mul(wm0.worst_case_latency, |
| 1179 | serge | 1065 | wm0.consumption_rate); |
| 1963 | serge | 1066 | b.full = dfixed_const(16 * 1000); |
| 1067 | priority_mark02.full = dfixed_div(a, b); |
||
| 1179 | serge | 1068 | } |
| 1069 | if (wm1.consumption_rate.full > fill_rate.full) { |
||
| 1070 | b.full = wm1.consumption_rate.full - fill_rate.full; |
||
| 1963 | serge | 1071 | b.full = dfixed_mul(b, wm1.active_time); |
| 1072 | a.full = dfixed_const(16); |
||
| 1073 | b.full = dfixed_div(b, a); |
||
| 1074 | a.full = dfixed_mul(wm1.worst_case_latency, |
||
| 1179 | serge | 1075 | wm1.consumption_rate); |
| 1076 | priority_mark12.full = a.full + b.full; |
||
| 1077 | } else { |
||
| 1963 | serge | 1078 | a.full = dfixed_mul(wm1.worst_case_latency, |
| 1179 | serge | 1079 | wm1.consumption_rate); |
| 1963 | serge | 1080 | b.full = dfixed_const(16 * 1000); |
| 1081 | priority_mark12.full = dfixed_div(a, b); |
||
| 1179 | serge | 1082 | } |
| 1083 | if (wm0.priority_mark.full > priority_mark02.full) |
||
| 1084 | priority_mark02.full = wm0.priority_mark.full; |
||
| 1963 | serge | 1085 | if (dfixed_trunc(priority_mark02) < 0) |
| 1179 | serge | 1086 | priority_mark02.full = 0; |
| 1087 | if (wm0.priority_mark_max.full > priority_mark02.full) |
||
| 1088 | priority_mark02.full = wm0.priority_mark_max.full; |
||
| 1089 | if (wm1.priority_mark.full > priority_mark12.full) |
||
| 1090 | priority_mark12.full = wm1.priority_mark.full; |
||
| 1963 | serge | 1091 | if (dfixed_trunc(priority_mark12) < 0) |
| 1179 | serge | 1092 | priority_mark12.full = 0; |
| 1093 | if (wm1.priority_mark_max.full > priority_mark12.full) |
||
| 1094 | priority_mark12.full = wm1.priority_mark_max.full; |
||
| 1963 | serge | 1095 | d1mode_priority_a_cnt = dfixed_trunc(priority_mark02); |
| 1096 | d2mode_priority_a_cnt = dfixed_trunc(priority_mark12); |
||
| 1097 | if (rdev->disp_priority == 2) { |
||
| 1098 | d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; |
||
| 1099 | d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; |
||
| 1100 | } |
||
| 1179 | serge | 1101 | } else if (mode0) { |
| 1963 | serge | 1102 | if (dfixed_trunc(wm0.dbpp) > 64) |
| 1103 | a.full = dfixed_div(wm0.dbpp, wm0.num_line_pair); |
||
| 1179 | serge | 1104 | else |
| 1105 | a.full = wm0.num_line_pair.full; |
||
| 1963 | serge | 1106 | fill_rate.full = dfixed_div(wm0.sclk, a); |
| 1179 | serge | 1107 | if (wm0.consumption_rate.full > fill_rate.full) { |
| 1108 | b.full = wm0.consumption_rate.full - fill_rate.full; |
||
| 1963 | serge | 1109 | b.full = dfixed_mul(b, wm0.active_time); |
| 1110 | a.full = dfixed_const(16); |
||
| 1111 | b.full = dfixed_div(b, a); |
||
| 1112 | a.full = dfixed_mul(wm0.worst_case_latency, |
||
| 1179 | serge | 1113 | wm0.consumption_rate); |
| 1114 | priority_mark02.full = a.full + b.full; |
||
| 1115 | } else { |
||
| 1963 | serge | 1116 | a.full = dfixed_mul(wm0.worst_case_latency, |
| 1179 | serge | 1117 | wm0.consumption_rate); |
| 1963 | serge | 1118 | b.full = dfixed_const(16); |
| 1119 | priority_mark02.full = dfixed_div(a, b); |
||
| 1179 | serge | 1120 | } |
| 1121 | if (wm0.priority_mark.full > priority_mark02.full) |
||
| 1122 | priority_mark02.full = wm0.priority_mark.full; |
||
| 1963 | serge | 1123 | if (dfixed_trunc(priority_mark02) < 0) |
| 1179 | serge | 1124 | priority_mark02.full = 0; |
| 1125 | if (wm0.priority_mark_max.full > priority_mark02.full) |
||
| 1126 | priority_mark02.full = wm0.priority_mark_max.full; |
||
| 1963 | serge | 1127 | d1mode_priority_a_cnt = dfixed_trunc(priority_mark02); |
| 1128 | if (rdev->disp_priority == 2) |
||
| 1129 | d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; |
||
| 1130 | } else if (mode1) { |
||
| 1131 | if (dfixed_trunc(wm1.dbpp) > 64) |
||
| 1132 | a.full = dfixed_div(wm1.dbpp, wm1.num_line_pair); |
||
| 1179 | serge | 1133 | else |
| 1134 | a.full = wm1.num_line_pair.full; |
||
| 1963 | serge | 1135 | fill_rate.full = dfixed_div(wm1.sclk, a); |
| 1179 | serge | 1136 | if (wm1.consumption_rate.full > fill_rate.full) { |
| 1137 | b.full = wm1.consumption_rate.full - fill_rate.full; |
||
| 1963 | serge | 1138 | b.full = dfixed_mul(b, wm1.active_time); |
| 1139 | a.full = dfixed_const(16); |
||
| 1140 | b.full = dfixed_div(b, a); |
||
| 1141 | a.full = dfixed_mul(wm1.worst_case_latency, |
||
| 1179 | serge | 1142 | wm1.consumption_rate); |
| 1143 | priority_mark12.full = a.full + b.full; |
||
| 1144 | } else { |
||
| 1963 | serge | 1145 | a.full = dfixed_mul(wm1.worst_case_latency, |
| 1179 | serge | 1146 | wm1.consumption_rate); |
| 1963 | serge | 1147 | b.full = dfixed_const(16 * 1000); |
| 1148 | priority_mark12.full = dfixed_div(a, b); |
||
| 1179 | serge | 1149 | } |
| 1150 | if (wm1.priority_mark.full > priority_mark12.full) |
||
| 1151 | priority_mark12.full = wm1.priority_mark.full; |
||
| 1963 | serge | 1152 | if (dfixed_trunc(priority_mark12) < 0) |
| 1179 | serge | 1153 | priority_mark12.full = 0; |
| 1154 | if (wm1.priority_mark_max.full > priority_mark12.full) |
||
| 1155 | priority_mark12.full = wm1.priority_mark_max.full; |
||
| 1963 | serge | 1156 | d2mode_priority_a_cnt = dfixed_trunc(priority_mark12); |
| 1157 | if (rdev->disp_priority == 2) |
||
| 1158 | d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; |
||
| 1179 | serge | 1159 | } |
| 1963 | serge | 1160 | |
| 1161 | WREG32(D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt); |
||
| 1162 | WREG32(D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt); |
||
| 1163 | WREG32(D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt); |
||
| 1164 | WREG32(D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt); |
||
| 1117 | serge | 1165 | } |
| 1179 | serge | 1166 | |
| 1167 | void rv515_bandwidth_update(struct radeon_device *rdev) |
||
| 1168 | { |
||
| 1169 | uint32_t tmp; |
||
| 1170 | struct drm_display_mode *mode0 = NULL; |
||
| 1171 | struct drm_display_mode *mode1 = NULL; |
||
| 1172 | |||
| 1963 | serge | 1173 | radeon_update_display_priority(rdev); |
| 1174 | |||
| 1179 | serge | 1175 | if (rdev->mode_info.crtcs[0]->base.enabled) |
| 1176 | mode0 = &rdev->mode_info.crtcs[0]->base.mode; |
||
| 1177 | if (rdev->mode_info.crtcs[1]->base.enabled) |
||
| 1178 | mode1 = &rdev->mode_info.crtcs[1]->base.mode; |
||
| 1179 | /* |
||
| 1180 | * Set display0/1 priority up in the memory controller for |
||
| 1181 | * modes if the user specifies HIGH for displaypriority |
||
| 1182 | * option. |
||
| 1183 | */ |
||
| 1963 | serge | 1184 | if ((rdev->disp_priority == 2) && |
| 1185 | (rdev->family == CHIP_RV515)) { |
||
| 1179 | serge | 1186 | tmp = RREG32_MC(MC_MISC_LAT_TIMER); |
| 1187 | tmp &= ~MC_DISP1R_INIT_LAT_MASK; |
||
| 1188 | tmp &= ~MC_DISP0R_INIT_LAT_MASK; |
||
| 1189 | if (mode1) |
||
| 1190 | tmp |= (1 << MC_DISP1R_INIT_LAT_SHIFT); |
||
| 1191 | if (mode0) |
||
| 1192 | tmp |= (1 << MC_DISP0R_INIT_LAT_SHIFT); |
||
| 1193 | WREG32_MC(MC_MISC_LAT_TIMER, tmp); |
||
| 1194 | } |
||
| 1195 | rv515_bandwidth_avivo_update(rdev); |
||
| 1196 | } |