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Rev | Author | Line No. | Line |
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1117 | serge | 1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
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3 | * Copyright 2008 Red Hat Inc. |
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4 | * Copyright 2009 Jerome Glisse. |
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5 | * |
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6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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7 | * copy of this software and associated documentation files (the "Software"), |
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8 | * to deal in the Software without restriction, including without limitation |
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9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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10 | * and/or sell copies of the Software, and to permit persons to whom the |
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11 | * Software is furnished to do so, subject to the following conditions: |
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12 | * |
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13 | * The above copyright notice and this permission notice shall be included in |
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14 | * all copies or substantial portions of the Software. |
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15 | * |
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16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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22 | * OTHER DEALINGS IN THE SOFTWARE. |
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23 | * |
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24 | * Authors: Dave Airlie |
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25 | * Alex Deucher |
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26 | * Jerome Glisse |
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27 | */ |
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1179 | serge | 28 | #include |
1986 | serge | 29 | #include |
2997 | Serge | 30 | #include |
1179 | serge | 31 | #include "rv515d.h" |
1117 | serge | 32 | #include "radeon.h" |
1963 | serge | 33 | #include "radeon_asic.h" |
1221 | serge | 34 | #include "atom.h" |
1179 | serge | 35 | #include "rv515_reg_safe.h" |
1117 | serge | 36 | |
1221 | serge | 37 | /* This files gather functions specifics to: rv515 */ |
2997 | Serge | 38 | static int rv515_debugfs_pipes_info_init(struct radeon_device *rdev); |
39 | static int rv515_debugfs_ga_info_init(struct radeon_device *rdev); |
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40 | static void rv515_gpu_init(struct radeon_device *rdev); |
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1117 | serge | 41 | int rv515_mc_wait_for_idle(struct radeon_device *rdev); |
42 | |||
3192 | Serge | 43 | static const u32 crtc_offsets[2] = |
44 | { |
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45 | 0, |
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46 | AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL |
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47 | }; |
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48 | |||
1221 | serge | 49 | void rv515_debugfs(struct radeon_device *rdev) |
1117 | serge | 50 | { |
1129 | serge | 51 | if (r100_debugfs_rbbm_init(rdev)) { |
52 | DRM_ERROR("Failed to register debugfs file for RBBM !\n"); |
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53 | } |
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54 | if (rv515_debugfs_pipes_info_init(rdev)) { |
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55 | DRM_ERROR("Failed to register debugfs file for pipes !\n"); |
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56 | } |
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57 | if (rv515_debugfs_ga_info_init(rdev)) { |
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58 | DRM_ERROR("Failed to register debugfs file for pipes !\n"); |
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59 | } |
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1117 | serge | 60 | } |
61 | |||
2997 | Serge | 62 | void rv515_ring_start(struct radeon_device *rdev, struct radeon_ring *ring) |
1117 | serge | 63 | { |
64 | int r; |
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65 | |||
2997 | Serge | 66 | r = radeon_ring_lock(rdev, ring, 64); |
1117 | serge | 67 | if (r) { |
68 | return; |
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69 | } |
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2997 | Serge | 70 | radeon_ring_write(ring, PACKET0(ISYNC_CNTL, 0)); |
71 | radeon_ring_write(ring, |
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1179 | serge | 72 | ISYNC_ANY2D_IDLE3D | |
73 | ISYNC_ANY3D_IDLE2D | |
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74 | ISYNC_WAIT_IDLEGUI | |
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75 | ISYNC_CPSCRATCH_IDLEGUI); |
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2997 | Serge | 76 | radeon_ring_write(ring, PACKET0(WAIT_UNTIL, 0)); |
77 | radeon_ring_write(ring, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN); |
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78 | radeon_ring_write(ring, PACKET0(R300_DST_PIPE_CONFIG, 0)); |
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79 | radeon_ring_write(ring, R300_PIPE_AUTO_CONFIG); |
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80 | radeon_ring_write(ring, PACKET0(GB_SELECT, 0)); |
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81 | radeon_ring_write(ring, 0); |
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82 | radeon_ring_write(ring, PACKET0(GB_ENABLE, 0)); |
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83 | radeon_ring_write(ring, 0); |
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84 | radeon_ring_write(ring, PACKET0(R500_SU_REG_DEST, 0)); |
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85 | radeon_ring_write(ring, (1 << rdev->num_gb_pipes) - 1); |
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86 | radeon_ring_write(ring, PACKET0(VAP_INDEX_OFFSET, 0)); |
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87 | radeon_ring_write(ring, 0); |
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88 | radeon_ring_write(ring, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0)); |
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89 | radeon_ring_write(ring, RB3D_DC_FLUSH | RB3D_DC_FREE); |
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90 | radeon_ring_write(ring, PACKET0(ZB_ZCACHE_CTLSTAT, 0)); |
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91 | radeon_ring_write(ring, ZC_FLUSH | ZC_FREE); |
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92 | radeon_ring_write(ring, PACKET0(WAIT_UNTIL, 0)); |
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93 | radeon_ring_write(ring, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN); |
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94 | radeon_ring_write(ring, PACKET0(GB_AA_CONFIG, 0)); |
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95 | radeon_ring_write(ring, 0); |
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96 | radeon_ring_write(ring, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0)); |
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97 | radeon_ring_write(ring, RB3D_DC_FLUSH | RB3D_DC_FREE); |
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98 | radeon_ring_write(ring, PACKET0(ZB_ZCACHE_CTLSTAT, 0)); |
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99 | radeon_ring_write(ring, ZC_FLUSH | ZC_FREE); |
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100 | radeon_ring_write(ring, PACKET0(GB_MSPOS0, 0)); |
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101 | radeon_ring_write(ring, |
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1179 | serge | 102 | ((6 << MS_X0_SHIFT) | |
103 | (6 << MS_Y0_SHIFT) | |
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104 | (6 << MS_X1_SHIFT) | |
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105 | (6 << MS_Y1_SHIFT) | |
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106 | (6 << MS_X2_SHIFT) | |
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107 | (6 << MS_Y2_SHIFT) | |
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108 | (6 << MSBD0_Y_SHIFT) | |
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109 | (6 << MSBD0_X_SHIFT))); |
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2997 | Serge | 110 | radeon_ring_write(ring, PACKET0(GB_MSPOS1, 0)); |
111 | radeon_ring_write(ring, |
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1179 | serge | 112 | ((6 << MS_X3_SHIFT) | |
113 | (6 << MS_Y3_SHIFT) | |
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114 | (6 << MS_X4_SHIFT) | |
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115 | (6 << MS_Y4_SHIFT) | |
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116 | (6 << MS_X5_SHIFT) | |
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117 | (6 << MS_Y5_SHIFT) | |
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118 | (6 << MSBD1_SHIFT))); |
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2997 | Serge | 119 | radeon_ring_write(ring, PACKET0(GA_ENHANCE, 0)); |
120 | radeon_ring_write(ring, GA_DEADLOCK_CNTL | GA_FASTSYNC_CNTL); |
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121 | radeon_ring_write(ring, PACKET0(GA_POLY_MODE, 0)); |
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122 | radeon_ring_write(ring, FRONT_PTYPE_TRIANGE | BACK_PTYPE_TRIANGE); |
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123 | radeon_ring_write(ring, PACKET0(GA_ROUND_MODE, 0)); |
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124 | radeon_ring_write(ring, GEOMETRY_ROUND_NEAREST | COLOR_ROUND_NEAREST); |
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125 | radeon_ring_write(ring, PACKET0(0x20C8, 0)); |
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126 | radeon_ring_write(ring, 0); |
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127 | radeon_ring_unlock_commit(rdev, ring); |
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1117 | serge | 128 | } |
129 | |||
130 | int rv515_mc_wait_for_idle(struct radeon_device *rdev) |
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131 | { |
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132 | unsigned i; |
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133 | uint32_t tmp; |
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134 | |||
135 | for (i = 0; i < rdev->usec_timeout; i++) { |
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136 | /* read MC_STATUS */ |
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1179 | serge | 137 | tmp = RREG32_MC(MC_STATUS); |
138 | if (tmp & MC_STATUS_IDLE) { |
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1117 | serge | 139 | return 0; |
140 | } |
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141 | DRM_UDELAY(1); |
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142 | } |
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143 | return -1; |
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144 | } |
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145 | |||
1221 | serge | 146 | void rv515_vga_render_disable(struct radeon_device *rdev) |
147 | { |
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148 | WREG32(R_000300_VGA_RENDER_CONTROL, |
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149 | RREG32(R_000300_VGA_RENDER_CONTROL) & C_000300_VGA_VSTATUS_CNTL); |
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150 | } |
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151 | |||
2997 | Serge | 152 | static void rv515_gpu_init(struct radeon_device *rdev) |
1117 | serge | 153 | { |
154 | unsigned pipe_select_current, gb_pipe_select, tmp; |
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155 | |||
156 | if (r100_gui_wait_for_idle(rdev)) { |
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157 | printk(KERN_WARNING "Failed to wait GUI idle while " |
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2997 | Serge | 158 | "resetting GPU. Bad things might happen.\n"); |
1117 | serge | 159 | } |
1221 | serge | 160 | rv515_vga_render_disable(rdev); |
1117 | serge | 161 | r420_pipes_init(rdev); |
1963 | serge | 162 | gb_pipe_select = RREG32(R400_GB_PIPE_SELECT); |
163 | tmp = RREG32(R300_DST_PIPE_CONFIG); |
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1117 | serge | 164 | pipe_select_current = (tmp >> 2) & 3; |
165 | tmp = (1 << pipe_select_current) | |
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166 | (((gb_pipe_select >> 8) & 0xF) << 4); |
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167 | WREG32_PLL(0x000D, tmp); |
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168 | if (r100_gui_wait_for_idle(rdev)) { |
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169 | printk(KERN_WARNING "Failed to wait GUI idle while " |
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2997 | Serge | 170 | "resetting GPU. Bad things might happen.\n"); |
1117 | serge | 171 | } |
172 | if (rv515_mc_wait_for_idle(rdev)) { |
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173 | printk(KERN_WARNING "Failed to wait MC idle while " |
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174 | "programming pipes. Bad things might happen.\n"); |
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175 | } |
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176 | } |
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177 | |||
178 | static void rv515_vram_get_type(struct radeon_device *rdev) |
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179 | { |
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180 | uint32_t tmp; |
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181 | |||
182 | rdev->mc.vram_width = 128; |
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183 | rdev->mc.vram_is_ddr = true; |
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1179 | serge | 184 | tmp = RREG32_MC(RV515_MC_CNTL) & MEM_NUM_CHANNELS_MASK; |
1117 | serge | 185 | switch (tmp) { |
186 | case 0: |
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187 | rdev->mc.vram_width = 64; |
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188 | break; |
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189 | case 1: |
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190 | rdev->mc.vram_width = 128; |
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191 | break; |
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192 | default: |
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193 | rdev->mc.vram_width = 128; |
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194 | break; |
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195 | } |
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196 | } |
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197 | |||
2997 | Serge | 198 | static void rv515_mc_init(struct radeon_device *rdev) |
1117 | serge | 199 | { |
1179 | serge | 200 | |
1117 | serge | 201 | rv515_vram_get_type(rdev); |
1179 | serge | 202 | r100_vram_init_sizes(rdev); |
1430 | serge | 203 | radeon_vram_location(rdev, &rdev->mc, 0); |
1963 | serge | 204 | rdev->mc.gtt_base_align = 0; |
1430 | serge | 205 | if (!(rdev->flags & RADEON_IS_AGP)) |
206 | radeon_gtt_location(rdev, &rdev->mc); |
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1963 | serge | 207 | radeon_update_bandwidth_info(rdev); |
1117 | serge | 208 | } |
209 | |||
210 | uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg) |
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211 | { |
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212 | uint32_t r; |
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213 | |||
1179 | serge | 214 | WREG32(MC_IND_INDEX, 0x7f0000 | (reg & 0xffff)); |
215 | r = RREG32(MC_IND_DATA); |
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216 | WREG32(MC_IND_INDEX, 0); |
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1117 | serge | 217 | return r; |
218 | } |
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219 | |||
220 | void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
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221 | { |
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1179 | serge | 222 | WREG32(MC_IND_INDEX, 0xff0000 | ((reg) & 0xffff)); |
223 | WREG32(MC_IND_DATA, (v)); |
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224 | WREG32(MC_IND_INDEX, 0); |
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1117 | serge | 225 | } |
226 | |||
227 | #if defined(CONFIG_DEBUG_FS) |
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228 | static int rv515_debugfs_pipes_info(struct seq_file *m, void *data) |
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229 | { |
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230 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
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231 | struct drm_device *dev = node->minor->dev; |
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232 | struct radeon_device *rdev = dev->dev_private; |
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233 | uint32_t tmp; |
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234 | |||
1179 | serge | 235 | tmp = RREG32(GB_PIPE_SELECT); |
1117 | serge | 236 | seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp); |
1179 | serge | 237 | tmp = RREG32(SU_REG_DEST); |
1117 | serge | 238 | seq_printf(m, "SU_REG_DEST 0x%08x\n", tmp); |
1179 | serge | 239 | tmp = RREG32(GB_TILE_CONFIG); |
1117 | serge | 240 | seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp); |
1179 | serge | 241 | tmp = RREG32(DST_PIPE_CONFIG); |
1117 | serge | 242 | seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp); |
243 | return 0; |
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244 | } |
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245 | |||
246 | static int rv515_debugfs_ga_info(struct seq_file *m, void *data) |
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247 | { |
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248 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
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249 | struct drm_device *dev = node->minor->dev; |
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250 | struct radeon_device *rdev = dev->dev_private; |
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251 | uint32_t tmp; |
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252 | |||
253 | tmp = RREG32(0x2140); |
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254 | seq_printf(m, "VAP_CNTL_STATUS 0x%08x\n", tmp); |
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1963 | serge | 255 | radeon_asic_reset(rdev); |
1117 | serge | 256 | tmp = RREG32(0x425C); |
257 | seq_printf(m, "GA_IDLE 0x%08x\n", tmp); |
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258 | return 0; |
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259 | } |
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260 | |||
261 | static struct drm_info_list rv515_pipes_info_list[] = { |
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262 | {"rv515_pipes_info", rv515_debugfs_pipes_info, 0, NULL}, |
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263 | }; |
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264 | |||
265 | static struct drm_info_list rv515_ga_info_list[] = { |
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266 | {"rv515_ga_info", rv515_debugfs_ga_info, 0, NULL}, |
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267 | }; |
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268 | #endif |
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269 | |||
2997 | Serge | 270 | static int rv515_debugfs_pipes_info_init(struct radeon_device *rdev) |
1117 | serge | 271 | { |
272 | #if defined(CONFIG_DEBUG_FS) |
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273 | return radeon_debugfs_add_files(rdev, rv515_pipes_info_list, 1); |
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274 | #else |
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275 | return 0; |
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276 | #endif |
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277 | } |
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278 | |||
2997 | Serge | 279 | static int rv515_debugfs_ga_info_init(struct radeon_device *rdev) |
1117 | serge | 280 | { |
281 | #if defined(CONFIG_DEBUG_FS) |
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282 | return radeon_debugfs_add_files(rdev, rv515_ga_info_list, 1); |
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283 | #else |
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284 | return 0; |
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285 | #endif |
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286 | } |
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287 | |||
1221 | serge | 288 | void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save) |
1179 | serge | 289 | { |
3192 | Serge | 290 | u32 crtc_enabled, tmp, frame_count, blackout; |
291 | int i, j; |
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292 | |||
1221 | serge | 293 | save->vga_render_control = RREG32(R_000300_VGA_RENDER_CONTROL); |
294 | save->vga_hdp_control = RREG32(R_000328_VGA_HDP_CONTROL); |
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1179 | serge | 295 | |
3192 | Serge | 296 | /* disable VGA render */ |
1221 | serge | 297 | WREG32(R_000300_VGA_RENDER_CONTROL, 0); |
3192 | Serge | 298 | /* blank the display controllers */ |
299 | for (i = 0; i < rdev->num_crtc; i++) { |
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300 | crtc_enabled = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]) & AVIVO_CRTC_EN; |
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301 | if (crtc_enabled) { |
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302 | save->crtc_enabled[i] = true; |
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303 | tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]); |
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304 | if (!(tmp & AVIVO_CRTC_DISP_READ_REQUEST_DISABLE)) { |
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305 | radeon_wait_for_vblank(rdev, i); |
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306 | tmp |= AVIVO_CRTC_DISP_READ_REQUEST_DISABLE; |
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307 | WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp); |
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308 | } |
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309 | /* wait for the next frame */ |
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310 | frame_count = radeon_get_vblank_counter(rdev, i); |
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311 | for (j = 0; j < rdev->usec_timeout; j++) { |
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312 | if (radeon_get_vblank_counter(rdev, i) != frame_count) |
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313 | break; |
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314 | udelay(1); |
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315 | } |
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316 | } else { |
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317 | save->crtc_enabled[i] = false; |
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318 | } |
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319 | } |
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320 | |||
321 | radeon_mc_wait_for_idle(rdev); |
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322 | |||
323 | if (rdev->family >= CHIP_R600) { |
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324 | if (rdev->family >= CHIP_RV770) |
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325 | blackout = RREG32(R700_MC_CITF_CNTL); |
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326 | else |
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327 | blackout = RREG32(R600_CITF_CNTL); |
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328 | if ((blackout & R600_BLACKOUT_MASK) != R600_BLACKOUT_MASK) { |
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329 | /* Block CPU access */ |
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330 | WREG32(R600_BIF_FB_EN, 0); |
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331 | /* blackout the MC */ |
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332 | blackout |= R600_BLACKOUT_MASK; |
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333 | if (rdev->family >= CHIP_RV770) |
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334 | WREG32(R700_MC_CITF_CNTL, blackout); |
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335 | else |
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336 | WREG32(R600_CITF_CNTL, blackout); |
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337 | } |
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338 | } |
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1221 | serge | 339 | } |
340 | |||
341 | void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save) |
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342 | { |
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3192 | Serge | 343 | u32 tmp, frame_count; |
344 | int i, j; |
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345 | |||
346 | /* update crtc base addresses */ |
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347 | for (i = 0; i < rdev->num_crtc; i++) { |
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348 | if (rdev->family >= CHIP_RV770) { |
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349 | if (i == 1) { |
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350 | WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, |
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351 | upper_32_bits(rdev->mc.vram_start)); |
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352 | WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, |
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353 | upper_32_bits(rdev->mc.vram_start)); |
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354 | } else { |
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355 | WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, |
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356 | upper_32_bits(rdev->mc.vram_start)); |
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357 | WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, |
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358 | upper_32_bits(rdev->mc.vram_start)); |
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359 | } |
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360 | } |
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361 | WREG32(R_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i], |
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362 | (u32)rdev->mc.vram_start); |
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363 | WREG32(R_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i], |
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364 | (u32)rdev->mc.vram_start); |
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365 | } |
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366 | WREG32(R_000310_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start); |
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367 | |||
368 | if (rdev->family >= CHIP_R600) { |
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369 | /* unblackout the MC */ |
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370 | if (rdev->family >= CHIP_RV770) |
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371 | tmp = RREG32(R700_MC_CITF_CNTL); |
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372 | else |
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373 | tmp = RREG32(R600_CITF_CNTL); |
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374 | tmp &= ~R600_BLACKOUT_MASK; |
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375 | if (rdev->family >= CHIP_RV770) |
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376 | WREG32(R700_MC_CITF_CNTL, tmp); |
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377 | else |
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378 | WREG32(R600_CITF_CNTL, tmp); |
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379 | /* allow CPU access */ |
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380 | WREG32(R600_BIF_FB_EN, R600_FB_READ_EN | R600_FB_WRITE_EN); |
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381 | } |
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382 | |||
383 | for (i = 0; i < rdev->num_crtc; i++) { |
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384 | if (save->crtc_enabled[i]) { |
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385 | tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]); |
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386 | tmp &= ~AVIVO_CRTC_DISP_READ_REQUEST_DISABLE; |
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387 | WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp); |
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388 | /* wait for the next frame */ |
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389 | frame_count = radeon_get_vblank_counter(rdev, i); |
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390 | for (j = 0; j < rdev->usec_timeout; j++) { |
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391 | if (radeon_get_vblank_counter(rdev, i) != frame_count) |
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392 | break; |
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393 | udelay(1); |
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394 | } |
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395 | } |
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396 | } |
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397 | /* Unlock vga access */ |
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1221 | serge | 398 | WREG32(R_000328_VGA_HDP_CONTROL, save->vga_hdp_control); |
399 | mdelay(1); |
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400 | WREG32(R_000300_VGA_RENDER_CONTROL, save->vga_render_control); |
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401 | } |
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402 | |||
2997 | Serge | 403 | static void rv515_mc_program(struct radeon_device *rdev) |
1221 | serge | 404 | { |
405 | struct rv515_mc_save save; |
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406 | |||
407 | /* Stops all mc clients */ |
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408 | rv515_mc_stop(rdev, &save); |
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409 | |||
410 | /* Wait for mc idle */ |
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411 | if (rv515_mc_wait_for_idle(rdev)) |
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412 | dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); |
||
413 | /* Write VRAM size in case we are limiting it */ |
||
414 | WREG32(R_0000F8_CONFIG_MEMSIZE, rdev->mc.real_vram_size); |
||
415 | /* Program MC, should be a 32bits limited address space */ |
||
416 | WREG32_MC(R_000001_MC_FB_LOCATION, |
||
417 | S_000001_MC_FB_START(rdev->mc.vram_start >> 16) | |
||
418 | S_000001_MC_FB_TOP(rdev->mc.vram_end >> 16)); |
||
419 | WREG32(R_000134_HDP_FB_LOCATION, |
||
420 | S_000134_HDP_FB_START(rdev->mc.vram_start >> 16)); |
||
421 | if (rdev->flags & RADEON_IS_AGP) { |
||
422 | WREG32_MC(R_000002_MC_AGP_LOCATION, |
||
423 | S_000002_MC_AGP_START(rdev->mc.gtt_start >> 16) | |
||
424 | S_000002_MC_AGP_TOP(rdev->mc.gtt_end >> 16)); |
||
425 | WREG32_MC(R_000003_MC_AGP_BASE, lower_32_bits(rdev->mc.agp_base)); |
||
426 | WREG32_MC(R_000004_MC_AGP_BASE_2, |
||
427 | S_000004_AGP_BASE_ADDR_2(upper_32_bits(rdev->mc.agp_base))); |
||
428 | } else { |
||
429 | WREG32_MC(R_000002_MC_AGP_LOCATION, 0xFFFFFFFF); |
||
430 | WREG32_MC(R_000003_MC_AGP_BASE, 0); |
||
431 | WREG32_MC(R_000004_MC_AGP_BASE_2, 0); |
||
432 | } |
||
433 | |||
434 | rv515_mc_resume(rdev, &save); |
||
435 | } |
||
436 | |||
437 | void rv515_clock_startup(struct radeon_device *rdev) |
||
438 | { |
||
439 | if (radeon_dynclks != -1 && radeon_dynclks) |
||
440 | radeon_atom_set_clock_gating(rdev, 1); |
||
441 | /* We need to force on some of the block */ |
||
442 | WREG32_PLL(R_00000F_CP_DYN_CNTL, |
||
443 | RREG32_PLL(R_00000F_CP_DYN_CNTL) | S_00000F_CP_FORCEON(1)); |
||
444 | WREG32_PLL(R_000011_E2_DYN_CNTL, |
||
445 | RREG32_PLL(R_000011_E2_DYN_CNTL) | S_000011_E2_FORCEON(1)); |
||
446 | WREG32_PLL(R_000013_IDCT_DYN_CNTL, |
||
447 | RREG32_PLL(R_000013_IDCT_DYN_CNTL) | S_000013_IDCT_FORCEON(1)); |
||
448 | } |
||
449 | |||
450 | static int rv515_startup(struct radeon_device *rdev) |
||
451 | { |
||
452 | int r; |
||
453 | |||
454 | rv515_mc_program(rdev); |
||
455 | /* Resume clock */ |
||
456 | rv515_clock_startup(rdev); |
||
457 | /* Initialize GPU configuration (# pipes, ...) */ |
||
458 | rv515_gpu_init(rdev); |
||
459 | /* Initialize GART (initialize after TTM so we can allocate |
||
460 | * memory through TTM but finalize after TTM) */ |
||
461 | if (rdev->flags & RADEON_IS_PCIE) { |
||
462 | r = rv370_pcie_gart_enable(rdev); |
||
463 | if (r) |
||
464 | return r; |
||
465 | } |
||
2005 | serge | 466 | |
467 | /* allocate wb buffer */ |
||
468 | r = radeon_wb_init(rdev); |
||
469 | if (r) |
||
470 | return r; |
||
471 | |||
3120 | serge | 472 | r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); |
473 | if (r) { |
||
474 | dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); |
||
475 | return r; |
||
476 | } |
||
477 | |||
1221 | serge | 478 | /* Enable IRQ */ |
2005 | serge | 479 | rs600_irq_set(rdev); |
1403 | serge | 480 | rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); |
1221 | serge | 481 | /* 1M ring buffer */ |
1413 | serge | 482 | r = r100_cp_init(rdev, 1024 * 1024); |
483 | if (r) { |
||
1963 | serge | 484 | dev_err(rdev->dev, "failed initializing CP (%d).\n", r); |
1413 | serge | 485 | return r; |
486 | } |
||
2997 | Serge | 487 | |
488 | r = radeon_ib_pool_init(rdev); |
||
2005 | serge | 489 | if (r) { |
2997 | Serge | 490 | dev_err(rdev->dev, "IB initialization failed (%d).\n", r); |
2005 | serge | 491 | return r; |
492 | } |
||
2997 | Serge | 493 | |
1221 | serge | 494 | return 0; |
495 | } |
||
496 | |||
497 | |||
498 | void rv515_set_safe_registers(struct radeon_device *rdev) |
||
499 | { |
||
1179 | serge | 500 | rdev->config.r300.reg_safe_bm = rv515_reg_safe_bm; |
501 | rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rv515_reg_safe_bm); |
||
1221 | serge | 502 | } |
503 | |||
504 | int rv515_init(struct radeon_device *rdev) |
||
505 | { |
||
506 | int r; |
||
507 | |||
508 | /* Initialize scratch registers */ |
||
509 | radeon_scratch_init(rdev); |
||
510 | /* Initialize surface registers */ |
||
511 | radeon_surface_init(rdev); |
||
512 | /* TODO: disable VGA need to use VGA request */ |
||
1963 | serge | 513 | /* restore some register to sane defaults */ |
514 | r100_restore_sanity(rdev); |
||
1221 | serge | 515 | /* BIOS*/ |
516 | if (!radeon_get_bios(rdev)) { |
||
517 | if (ASIC_IS_AVIVO(rdev)) |
||
518 | return -EINVAL; |
||
519 | } |
||
520 | if (rdev->is_atom_bios) { |
||
521 | r = radeon_atombios_init(rdev); |
||
522 | if (r) |
||
523 | return r; |
||
524 | } else { |
||
525 | dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n"); |
||
526 | return -EINVAL; |
||
527 | } |
||
528 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ |
||
1963 | serge | 529 | if (radeon_asic_reset(rdev)) { |
1221 | serge | 530 | dev_warn(rdev->dev, |
531 | "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", |
||
532 | RREG32(R_000E40_RBBM_STATUS), |
||
533 | RREG32(R_0007C0_CP_STAT)); |
||
534 | } |
||
535 | /* check if cards are posted or not */ |
||
1403 | serge | 536 | if (radeon_boot_test_post_card(rdev) == false) |
537 | return -EINVAL; |
||
1221 | serge | 538 | /* Initialize clocks */ |
539 | radeon_get_clock_info(rdev->ddev); |
||
1430 | serge | 540 | /* initialize AGP */ |
541 | if (rdev->flags & RADEON_IS_AGP) { |
||
542 | r = radeon_agp_init(rdev); |
||
543 | if (r) { |
||
544 | radeon_agp_disable(rdev); |
||
545 | } |
||
546 | } |
||
547 | /* initialize memory controller */ |
||
548 | rv515_mc_init(rdev); |
||
1221 | serge | 549 | rv515_debugfs(rdev); |
550 | /* Fence driver */ |
||
2005 | serge | 551 | r = radeon_fence_driver_init(rdev); |
552 | if (r) |
||
553 | return r; |
||
554 | r = radeon_irq_kms_init(rdev); |
||
555 | if (r) |
||
556 | return r; |
||
1221 | serge | 557 | /* Memory manager */ |
1403 | serge | 558 | r = radeon_bo_init(rdev); |
1221 | serge | 559 | if (r) |
560 | return r; |
||
561 | r = rv370_pcie_gart_init(rdev); |
||
562 | if (r) |
||
563 | return r; |
||
564 | rv515_set_safe_registers(rdev); |
||
2997 | Serge | 565 | |
1221 | serge | 566 | rdev->accel_working = true; |
567 | r = rv515_startup(rdev); |
||
568 | if (r) { |
||
569 | /* Somethings want wront with the accel init stop accel */ |
||
570 | dev_err(rdev->dev, "Disabling GPU acceleration\n"); |
||
571 | // r100_cp_fini(rdev); |
||
572 | // r100_wb_fini(rdev); |
||
573 | // r100_ib_fini(rdev); |
||
574 | rv370_pcie_gart_fini(rdev); |
||
575 | // radeon_agp_fini(rdev); |
||
576 | rdev->accel_working = false; |
||
577 | } |
||
1179 | serge | 578 | return 0; |
579 | } |
||
580 | |||
581 | void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *crtc) |
||
582 | { |
||
583 | int index_reg = 0x6578 + crtc->crtc_offset; |
||
584 | int data_reg = 0x657c + crtc->crtc_offset; |
||
585 | |||
586 | WREG32(0x659C + crtc->crtc_offset, 0x0); |
||
587 | WREG32(0x6594 + crtc->crtc_offset, 0x705); |
||
588 | WREG32(0x65A4 + crtc->crtc_offset, 0x10001); |
||
589 | WREG32(0x65D8 + crtc->crtc_offset, 0x0); |
||
590 | WREG32(0x65B0 + crtc->crtc_offset, 0x0); |
||
591 | WREG32(0x65C0 + crtc->crtc_offset, 0x0); |
||
592 | WREG32(0x65D4 + crtc->crtc_offset, 0x0); |
||
593 | WREG32(index_reg, 0x0); |
||
594 | WREG32(data_reg, 0x841880A8); |
||
595 | WREG32(index_reg, 0x1); |
||
596 | WREG32(data_reg, 0x84208680); |
||
597 | WREG32(index_reg, 0x2); |
||
598 | WREG32(data_reg, 0xBFF880B0); |
||
599 | WREG32(index_reg, 0x100); |
||
600 | WREG32(data_reg, 0x83D88088); |
||
601 | WREG32(index_reg, 0x101); |
||
602 | WREG32(data_reg, 0x84608680); |
||
603 | WREG32(index_reg, 0x102); |
||
604 | WREG32(data_reg, 0xBFF080D0); |
||
605 | WREG32(index_reg, 0x200); |
||
606 | WREG32(data_reg, 0x83988068); |
||
607 | WREG32(index_reg, 0x201); |
||
608 | WREG32(data_reg, 0x84A08680); |
||
609 | WREG32(index_reg, 0x202); |
||
610 | WREG32(data_reg, 0xBFF080F8); |
||
611 | WREG32(index_reg, 0x300); |
||
612 | WREG32(data_reg, 0x83588058); |
||
613 | WREG32(index_reg, 0x301); |
||
614 | WREG32(data_reg, 0x84E08660); |
||
615 | WREG32(index_reg, 0x302); |
||
616 | WREG32(data_reg, 0xBFF88120); |
||
617 | WREG32(index_reg, 0x400); |
||
618 | WREG32(data_reg, 0x83188040); |
||
619 | WREG32(index_reg, 0x401); |
||
620 | WREG32(data_reg, 0x85008660); |
||
621 | WREG32(index_reg, 0x402); |
||
622 | WREG32(data_reg, 0xBFF88150); |
||
623 | WREG32(index_reg, 0x500); |
||
624 | WREG32(data_reg, 0x82D88030); |
||
625 | WREG32(index_reg, 0x501); |
||
626 | WREG32(data_reg, 0x85408640); |
||
627 | WREG32(index_reg, 0x502); |
||
628 | WREG32(data_reg, 0xBFF88180); |
||
629 | WREG32(index_reg, 0x600); |
||
630 | WREG32(data_reg, 0x82A08018); |
||
631 | WREG32(index_reg, 0x601); |
||
632 | WREG32(data_reg, 0x85808620); |
||
633 | WREG32(index_reg, 0x602); |
||
634 | WREG32(data_reg, 0xBFF081B8); |
||
635 | WREG32(index_reg, 0x700); |
||
636 | WREG32(data_reg, 0x82608010); |
||
637 | WREG32(index_reg, 0x701); |
||
638 | WREG32(data_reg, 0x85A08600); |
||
639 | WREG32(index_reg, 0x702); |
||
640 | WREG32(data_reg, 0x800081F0); |
||
641 | WREG32(index_reg, 0x800); |
||
642 | WREG32(data_reg, 0x8228BFF8); |
||
643 | WREG32(index_reg, 0x801); |
||
644 | WREG32(data_reg, 0x85E085E0); |
||
645 | WREG32(index_reg, 0x802); |
||
646 | WREG32(data_reg, 0xBFF88228); |
||
647 | WREG32(index_reg, 0x10000); |
||
648 | WREG32(data_reg, 0x82A8BF00); |
||
649 | WREG32(index_reg, 0x10001); |
||
650 | WREG32(data_reg, 0x82A08CC0); |
||
651 | WREG32(index_reg, 0x10002); |
||
652 | WREG32(data_reg, 0x8008BEF8); |
||
653 | WREG32(index_reg, 0x10100); |
||
654 | WREG32(data_reg, 0x81F0BF28); |
||
655 | WREG32(index_reg, 0x10101); |
||
656 | WREG32(data_reg, 0x83608CA0); |
||
657 | WREG32(index_reg, 0x10102); |
||
658 | WREG32(data_reg, 0x8018BED0); |
||
659 | WREG32(index_reg, 0x10200); |
||
660 | WREG32(data_reg, 0x8148BF38); |
||
661 | WREG32(index_reg, 0x10201); |
||
662 | WREG32(data_reg, 0x84408C80); |
||
663 | WREG32(index_reg, 0x10202); |
||
664 | WREG32(data_reg, 0x8008BEB8); |
||
665 | WREG32(index_reg, 0x10300); |
||
666 | WREG32(data_reg, 0x80B0BF78); |
||
667 | WREG32(index_reg, 0x10301); |
||
668 | WREG32(data_reg, 0x85008C20); |
||
669 | WREG32(index_reg, 0x10302); |
||
670 | WREG32(data_reg, 0x8020BEA0); |
||
671 | WREG32(index_reg, 0x10400); |
||
672 | WREG32(data_reg, 0x8028BF90); |
||
673 | WREG32(index_reg, 0x10401); |
||
674 | WREG32(data_reg, 0x85E08BC0); |
||
675 | WREG32(index_reg, 0x10402); |
||
676 | WREG32(data_reg, 0x8018BE90); |
||
677 | WREG32(index_reg, 0x10500); |
||
678 | WREG32(data_reg, 0xBFB8BFB0); |
||
679 | WREG32(index_reg, 0x10501); |
||
680 | WREG32(data_reg, 0x86C08B40); |
||
681 | WREG32(index_reg, 0x10502); |
||
682 | WREG32(data_reg, 0x8010BE90); |
||
683 | WREG32(index_reg, 0x10600); |
||
684 | WREG32(data_reg, 0xBF58BFC8); |
||
685 | WREG32(index_reg, 0x10601); |
||
686 | WREG32(data_reg, 0x87A08AA0); |
||
687 | WREG32(index_reg, 0x10602); |
||
688 | WREG32(data_reg, 0x8010BE98); |
||
689 | WREG32(index_reg, 0x10700); |
||
690 | WREG32(data_reg, 0xBF10BFF0); |
||
691 | WREG32(index_reg, 0x10701); |
||
692 | WREG32(data_reg, 0x886089E0); |
||
693 | WREG32(index_reg, 0x10702); |
||
694 | WREG32(data_reg, 0x8018BEB0); |
||
695 | WREG32(index_reg, 0x10800); |
||
696 | WREG32(data_reg, 0xBED8BFE8); |
||
697 | WREG32(index_reg, 0x10801); |
||
698 | WREG32(data_reg, 0x89408940); |
||
699 | WREG32(index_reg, 0x10802); |
||
700 | WREG32(data_reg, 0xBFE8BED8); |
||
701 | WREG32(index_reg, 0x20000); |
||
702 | WREG32(data_reg, 0x80008000); |
||
703 | WREG32(index_reg, 0x20001); |
||
704 | WREG32(data_reg, 0x90008000); |
||
705 | WREG32(index_reg, 0x20002); |
||
706 | WREG32(data_reg, 0x80008000); |
||
707 | WREG32(index_reg, 0x20003); |
||
708 | WREG32(data_reg, 0x80008000); |
||
709 | WREG32(index_reg, 0x20100); |
||
710 | WREG32(data_reg, 0x80108000); |
||
711 | WREG32(index_reg, 0x20101); |
||
712 | WREG32(data_reg, 0x8FE0BF70); |
||
713 | WREG32(index_reg, 0x20102); |
||
714 | WREG32(data_reg, 0xBFE880C0); |
||
715 | WREG32(index_reg, 0x20103); |
||
716 | WREG32(data_reg, 0x80008000); |
||
717 | WREG32(index_reg, 0x20200); |
||
718 | WREG32(data_reg, 0x8018BFF8); |
||
719 | WREG32(index_reg, 0x20201); |
||
720 | WREG32(data_reg, 0x8F80BF08); |
||
721 | WREG32(index_reg, 0x20202); |
||
722 | WREG32(data_reg, 0xBFD081A0); |
||
723 | WREG32(index_reg, 0x20203); |
||
724 | WREG32(data_reg, 0xBFF88000); |
||
725 | WREG32(index_reg, 0x20300); |
||
726 | WREG32(data_reg, 0x80188000); |
||
727 | WREG32(index_reg, 0x20301); |
||
728 | WREG32(data_reg, 0x8EE0BEC0); |
||
729 | WREG32(index_reg, 0x20302); |
||
730 | WREG32(data_reg, 0xBFB082A0); |
||
731 | WREG32(index_reg, 0x20303); |
||
732 | WREG32(data_reg, 0x80008000); |
||
733 | WREG32(index_reg, 0x20400); |
||
734 | WREG32(data_reg, 0x80188000); |
||
735 | WREG32(index_reg, 0x20401); |
||
736 | WREG32(data_reg, 0x8E00BEA0); |
||
737 | WREG32(index_reg, 0x20402); |
||
738 | WREG32(data_reg, 0xBF8883C0); |
||
739 | WREG32(index_reg, 0x20403); |
||
740 | WREG32(data_reg, 0x80008000); |
||
741 | WREG32(index_reg, 0x20500); |
||
742 | WREG32(data_reg, 0x80188000); |
||
743 | WREG32(index_reg, 0x20501); |
||
744 | WREG32(data_reg, 0x8D00BE90); |
||
745 | WREG32(index_reg, 0x20502); |
||
746 | WREG32(data_reg, 0xBF588500); |
||
747 | WREG32(index_reg, 0x20503); |
||
748 | WREG32(data_reg, 0x80008008); |
||
749 | WREG32(index_reg, 0x20600); |
||
750 | WREG32(data_reg, 0x80188000); |
||
751 | WREG32(index_reg, 0x20601); |
||
752 | WREG32(data_reg, 0x8BC0BE98); |
||
753 | WREG32(index_reg, 0x20602); |
||
754 | WREG32(data_reg, 0xBF308660); |
||
755 | WREG32(index_reg, 0x20603); |
||
756 | WREG32(data_reg, 0x80008008); |
||
757 | WREG32(index_reg, 0x20700); |
||
758 | WREG32(data_reg, 0x80108000); |
||
759 | WREG32(index_reg, 0x20701); |
||
760 | WREG32(data_reg, 0x8A80BEB0); |
||
761 | WREG32(index_reg, 0x20702); |
||
762 | WREG32(data_reg, 0xBF0087C0); |
||
763 | WREG32(index_reg, 0x20703); |
||
764 | WREG32(data_reg, 0x80008008); |
||
765 | WREG32(index_reg, 0x20800); |
||
766 | WREG32(data_reg, 0x80108000); |
||
767 | WREG32(index_reg, 0x20801); |
||
768 | WREG32(data_reg, 0x8920BED0); |
||
769 | WREG32(index_reg, 0x20802); |
||
770 | WREG32(data_reg, 0xBED08920); |
||
771 | WREG32(index_reg, 0x20803); |
||
772 | WREG32(data_reg, 0x80008010); |
||
773 | WREG32(index_reg, 0x30000); |
||
774 | WREG32(data_reg, 0x90008000); |
||
775 | WREG32(index_reg, 0x30001); |
||
776 | WREG32(data_reg, 0x80008000); |
||
777 | WREG32(index_reg, 0x30100); |
||
778 | WREG32(data_reg, 0x8FE0BF90); |
||
779 | WREG32(index_reg, 0x30101); |
||
780 | WREG32(data_reg, 0xBFF880A0); |
||
781 | WREG32(index_reg, 0x30200); |
||
782 | WREG32(data_reg, 0x8F60BF40); |
||
783 | WREG32(index_reg, 0x30201); |
||
784 | WREG32(data_reg, 0xBFE88180); |
||
785 | WREG32(index_reg, 0x30300); |
||
786 | WREG32(data_reg, 0x8EC0BF00); |
||
787 | WREG32(index_reg, 0x30301); |
||
788 | WREG32(data_reg, 0xBFC88280); |
||
789 | WREG32(index_reg, 0x30400); |
||
790 | WREG32(data_reg, 0x8DE0BEE0); |
||
791 | WREG32(index_reg, 0x30401); |
||
792 | WREG32(data_reg, 0xBFA083A0); |
||
793 | WREG32(index_reg, 0x30500); |
||
794 | WREG32(data_reg, 0x8CE0BED0); |
||
795 | WREG32(index_reg, 0x30501); |
||
796 | WREG32(data_reg, 0xBF7884E0); |
||
797 | WREG32(index_reg, 0x30600); |
||
798 | WREG32(data_reg, 0x8BA0BED8); |
||
799 | WREG32(index_reg, 0x30601); |
||
800 | WREG32(data_reg, 0xBF508640); |
||
801 | WREG32(index_reg, 0x30700); |
||
802 | WREG32(data_reg, 0x8A60BEE8); |
||
803 | WREG32(index_reg, 0x30701); |
||
804 | WREG32(data_reg, 0xBF2087A0); |
||
805 | WREG32(index_reg, 0x30800); |
||
806 | WREG32(data_reg, 0x8900BF00); |
||
807 | WREG32(index_reg, 0x30801); |
||
808 | WREG32(data_reg, 0xBF008900); |
||
809 | } |
||
810 | |||
811 | struct rv515_watermark { |
||
812 | u32 lb_request_fifo_depth; |
||
813 | fixed20_12 num_line_pair; |
||
814 | fixed20_12 estimated_width; |
||
815 | fixed20_12 worst_case_latency; |
||
816 | fixed20_12 consumption_rate; |
||
817 | fixed20_12 active_time; |
||
818 | fixed20_12 dbpp; |
||
819 | fixed20_12 priority_mark_max; |
||
820 | fixed20_12 priority_mark; |
||
821 | fixed20_12 sclk; |
||
1117 | serge | 822 | }; |
823 | |||
2997 | Serge | 824 | static void rv515_crtc_bandwidth_compute(struct radeon_device *rdev, |
1179 | serge | 825 | struct radeon_crtc *crtc, |
826 | struct rv515_watermark *wm) |
||
827 | { |
||
828 | struct drm_display_mode *mode = &crtc->base.mode; |
||
829 | fixed20_12 a, b, c; |
||
830 | fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width; |
||
831 | fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency; |
||
1117 | serge | 832 | |
1179 | serge | 833 | if (!crtc->base.enabled) { |
834 | /* FIXME: wouldn't it better to set priority mark to maximum */ |
||
835 | wm->lb_request_fifo_depth = 4; |
||
836 | return; |
||
837 | } |
||
1117 | serge | 838 | |
1963 | serge | 839 | if (crtc->vsc.full > dfixed_const(2)) |
840 | wm->num_line_pair.full = dfixed_const(2); |
||
1179 | serge | 841 | else |
1963 | serge | 842 | wm->num_line_pair.full = dfixed_const(1); |
1179 | serge | 843 | |
1963 | serge | 844 | b.full = dfixed_const(mode->crtc_hdisplay); |
845 | c.full = dfixed_const(256); |
||
846 | a.full = dfixed_div(b, c); |
||
847 | request_fifo_depth.full = dfixed_mul(a, wm->num_line_pair); |
||
848 | request_fifo_depth.full = dfixed_ceil(request_fifo_depth); |
||
849 | if (a.full < dfixed_const(4)) { |
||
1179 | serge | 850 | wm->lb_request_fifo_depth = 4; |
851 | } else { |
||
1963 | serge | 852 | wm->lb_request_fifo_depth = dfixed_trunc(request_fifo_depth); |
1179 | serge | 853 | } |
854 | |||
855 | /* Determine consumption rate |
||
856 | * pclk = pixel clock period(ns) = 1000 / (mode.clock / 1000) |
||
857 | * vtaps = number of vertical taps, |
||
858 | * vsc = vertical scaling ratio, defined as source/destination |
||
859 | * hsc = horizontal scaling ration, defined as source/destination |
||
860 | */ |
||
1963 | serge | 861 | a.full = dfixed_const(mode->clock); |
862 | b.full = dfixed_const(1000); |
||
863 | a.full = dfixed_div(a, b); |
||
864 | pclk.full = dfixed_div(b, a); |
||
1179 | serge | 865 | if (crtc->rmx_type != RMX_OFF) { |
1963 | serge | 866 | b.full = dfixed_const(2); |
1179 | serge | 867 | if (crtc->vsc.full > b.full) |
868 | b.full = crtc->vsc.full; |
||
1963 | serge | 869 | b.full = dfixed_mul(b, crtc->hsc); |
870 | c.full = dfixed_const(2); |
||
871 | b.full = dfixed_div(b, c); |
||
872 | consumption_time.full = dfixed_div(pclk, b); |
||
1179 | serge | 873 | } else { |
874 | consumption_time.full = pclk.full; |
||
875 | } |
||
1963 | serge | 876 | a.full = dfixed_const(1); |
877 | wm->consumption_rate.full = dfixed_div(a, consumption_time); |
||
1179 | serge | 878 | |
879 | |||
880 | /* Determine line time |
||
881 | * LineTime = total time for one line of displayhtotal |
||
882 | * LineTime = total number of horizontal pixels |
||
883 | * pclk = pixel clock period(ns) |
||
884 | */ |
||
1963 | serge | 885 | a.full = dfixed_const(crtc->base.mode.crtc_htotal); |
886 | line_time.full = dfixed_mul(a, pclk); |
||
1179 | serge | 887 | |
888 | /* Determine active time |
||
889 | * ActiveTime = time of active region of display within one line, |
||
890 | * hactive = total number of horizontal active pixels |
||
891 | * htotal = total number of horizontal pixels |
||
892 | */ |
||
1963 | serge | 893 | a.full = dfixed_const(crtc->base.mode.crtc_htotal); |
894 | b.full = dfixed_const(crtc->base.mode.crtc_hdisplay); |
||
895 | wm->active_time.full = dfixed_mul(line_time, b); |
||
896 | wm->active_time.full = dfixed_div(wm->active_time, a); |
||
1179 | serge | 897 | |
898 | /* Determine chunk time |
||
899 | * ChunkTime = the time it takes the DCP to send one chunk of data |
||
900 | * to the LB which consists of pipeline delay and inter chunk gap |
||
901 | * sclk = system clock(Mhz) |
||
902 | */ |
||
1963 | serge | 903 | a.full = dfixed_const(600 * 1000); |
904 | chunk_time.full = dfixed_div(a, rdev->pm.sclk); |
||
905 | read_delay_latency.full = dfixed_const(1000); |
||
1179 | serge | 906 | |
907 | /* Determine the worst case latency |
||
908 | * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines) |
||
909 | * WorstCaseLatency = worst case time from urgent to when the MC starts |
||
910 | * to return data |
||
911 | * READ_DELAY_IDLE_MAX = constant of 1us |
||
912 | * ChunkTime = time it takes the DCP to send one chunk of data to the LB |
||
913 | * which consists of pipeline delay and inter chunk gap |
||
914 | */ |
||
1963 | serge | 915 | if (dfixed_trunc(wm->num_line_pair) > 1) { |
916 | a.full = dfixed_const(3); |
||
917 | wm->worst_case_latency.full = dfixed_mul(a, chunk_time); |
||
1179 | serge | 918 | wm->worst_case_latency.full += read_delay_latency.full; |
919 | } else { |
||
920 | wm->worst_case_latency.full = chunk_time.full + read_delay_latency.full; |
||
921 | } |
||
922 | |||
923 | /* Determine the tolerable latency |
||
924 | * TolerableLatency = Any given request has only 1 line time |
||
925 | * for the data to be returned |
||
926 | * LBRequestFifoDepth = Number of chunk requests the LB can |
||
927 | * put into the request FIFO for a display |
||
928 | * LineTime = total time for one line of display |
||
929 | * ChunkTime = the time it takes the DCP to send one chunk |
||
930 | * of data to the LB which consists of |
||
931 | * pipeline delay and inter chunk gap |
||
932 | */ |
||
1963 | serge | 933 | if ((2+wm->lb_request_fifo_depth) >= dfixed_trunc(request_fifo_depth)) { |
1179 | serge | 934 | tolerable_latency.full = line_time.full; |
935 | } else { |
||
1963 | serge | 936 | tolerable_latency.full = dfixed_const(wm->lb_request_fifo_depth - 2); |
1179 | serge | 937 | tolerable_latency.full = request_fifo_depth.full - tolerable_latency.full; |
1963 | serge | 938 | tolerable_latency.full = dfixed_mul(tolerable_latency, chunk_time); |
1179 | serge | 939 | tolerable_latency.full = line_time.full - tolerable_latency.full; |
940 | } |
||
941 | /* We assume worst case 32bits (4 bytes) */ |
||
1963 | serge | 942 | wm->dbpp.full = dfixed_const(2 * 16); |
1179 | serge | 943 | |
944 | /* Determine the maximum priority mark |
||
945 | * width = viewport width in pixels |
||
946 | */ |
||
1963 | serge | 947 | a.full = dfixed_const(16); |
948 | wm->priority_mark_max.full = dfixed_const(crtc->base.mode.crtc_hdisplay); |
||
949 | wm->priority_mark_max.full = dfixed_div(wm->priority_mark_max, a); |
||
950 | wm->priority_mark_max.full = dfixed_ceil(wm->priority_mark_max); |
||
1179 | serge | 951 | |
952 | /* Determine estimated width */ |
||
953 | estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full; |
||
1963 | serge | 954 | estimated_width.full = dfixed_div(estimated_width, consumption_time); |
955 | if (dfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) { |
||
1403 | serge | 956 | wm->priority_mark.full = wm->priority_mark_max.full; |
1179 | serge | 957 | } else { |
1963 | serge | 958 | a.full = dfixed_const(16); |
959 | wm->priority_mark.full = dfixed_div(estimated_width, a); |
||
960 | wm->priority_mark.full = dfixed_ceil(wm->priority_mark); |
||
1179 | serge | 961 | wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full; |
962 | } |
||
963 | } |
||
964 | |||
965 | void rv515_bandwidth_avivo_update(struct radeon_device *rdev) |
||
1117 | serge | 966 | { |
1179 | serge | 967 | struct drm_display_mode *mode0 = NULL; |
968 | struct drm_display_mode *mode1 = NULL; |
||
969 | struct rv515_watermark wm0; |
||
970 | struct rv515_watermark wm1; |
||
971 | u32 tmp; |
||
1963 | serge | 972 | u32 d1mode_priority_a_cnt = MODE_PRIORITY_OFF; |
973 | u32 d2mode_priority_a_cnt = MODE_PRIORITY_OFF; |
||
1179 | serge | 974 | fixed20_12 priority_mark02, priority_mark12, fill_rate; |
975 | fixed20_12 a, b; |
||
1117 | serge | 976 | |
1179 | serge | 977 | if (rdev->mode_info.crtcs[0]->base.enabled) |
978 | mode0 = &rdev->mode_info.crtcs[0]->base.mode; |
||
979 | if (rdev->mode_info.crtcs[1]->base.enabled) |
||
980 | mode1 = &rdev->mode_info.crtcs[1]->base.mode; |
||
981 | rs690_line_buffer_adjust(rdev, mode0, mode1); |
||
982 | |||
983 | rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0); |
||
984 | rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1); |
||
985 | |||
986 | tmp = wm0.lb_request_fifo_depth; |
||
987 | tmp |= wm1.lb_request_fifo_depth << 16; |
||
988 | WREG32(LB_MAX_REQ_OUTSTANDING, tmp); |
||
989 | |||
990 | if (mode0 && mode1) { |
||
1963 | serge | 991 | if (dfixed_trunc(wm0.dbpp) > 64) |
992 | a.full = dfixed_div(wm0.dbpp, wm0.num_line_pair); |
||
1179 | serge | 993 | else |
994 | a.full = wm0.num_line_pair.full; |
||
1963 | serge | 995 | if (dfixed_trunc(wm1.dbpp) > 64) |
996 | b.full = dfixed_div(wm1.dbpp, wm1.num_line_pair); |
||
1179 | serge | 997 | else |
998 | b.full = wm1.num_line_pair.full; |
||
999 | a.full += b.full; |
||
1963 | serge | 1000 | fill_rate.full = dfixed_div(wm0.sclk, a); |
1179 | serge | 1001 | if (wm0.consumption_rate.full > fill_rate.full) { |
1002 | b.full = wm0.consumption_rate.full - fill_rate.full; |
||
1963 | serge | 1003 | b.full = dfixed_mul(b, wm0.active_time); |
1004 | a.full = dfixed_const(16); |
||
1005 | b.full = dfixed_div(b, a); |
||
1006 | a.full = dfixed_mul(wm0.worst_case_latency, |
||
1179 | serge | 1007 | wm0.consumption_rate); |
1008 | priority_mark02.full = a.full + b.full; |
||
1009 | } else { |
||
1963 | serge | 1010 | a.full = dfixed_mul(wm0.worst_case_latency, |
1179 | serge | 1011 | wm0.consumption_rate); |
1963 | serge | 1012 | b.full = dfixed_const(16 * 1000); |
1013 | priority_mark02.full = dfixed_div(a, b); |
||
1179 | serge | 1014 | } |
1015 | if (wm1.consumption_rate.full > fill_rate.full) { |
||
1016 | b.full = wm1.consumption_rate.full - fill_rate.full; |
||
1963 | serge | 1017 | b.full = dfixed_mul(b, wm1.active_time); |
1018 | a.full = dfixed_const(16); |
||
1019 | b.full = dfixed_div(b, a); |
||
1020 | a.full = dfixed_mul(wm1.worst_case_latency, |
||
1179 | serge | 1021 | wm1.consumption_rate); |
1022 | priority_mark12.full = a.full + b.full; |
||
1023 | } else { |
||
1963 | serge | 1024 | a.full = dfixed_mul(wm1.worst_case_latency, |
1179 | serge | 1025 | wm1.consumption_rate); |
1963 | serge | 1026 | b.full = dfixed_const(16 * 1000); |
1027 | priority_mark12.full = dfixed_div(a, b); |
||
1179 | serge | 1028 | } |
1029 | if (wm0.priority_mark.full > priority_mark02.full) |
||
1030 | priority_mark02.full = wm0.priority_mark.full; |
||
1963 | serge | 1031 | if (dfixed_trunc(priority_mark02) < 0) |
1179 | serge | 1032 | priority_mark02.full = 0; |
1033 | if (wm0.priority_mark_max.full > priority_mark02.full) |
||
1034 | priority_mark02.full = wm0.priority_mark_max.full; |
||
1035 | if (wm1.priority_mark.full > priority_mark12.full) |
||
1036 | priority_mark12.full = wm1.priority_mark.full; |
||
1963 | serge | 1037 | if (dfixed_trunc(priority_mark12) < 0) |
1179 | serge | 1038 | priority_mark12.full = 0; |
1039 | if (wm1.priority_mark_max.full > priority_mark12.full) |
||
1040 | priority_mark12.full = wm1.priority_mark_max.full; |
||
1963 | serge | 1041 | d1mode_priority_a_cnt = dfixed_trunc(priority_mark02); |
1042 | d2mode_priority_a_cnt = dfixed_trunc(priority_mark12); |
||
1043 | if (rdev->disp_priority == 2) { |
||
1044 | d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; |
||
1045 | d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; |
||
1046 | } |
||
1179 | serge | 1047 | } else if (mode0) { |
1963 | serge | 1048 | if (dfixed_trunc(wm0.dbpp) > 64) |
1049 | a.full = dfixed_div(wm0.dbpp, wm0.num_line_pair); |
||
1179 | serge | 1050 | else |
1051 | a.full = wm0.num_line_pair.full; |
||
1963 | serge | 1052 | fill_rate.full = dfixed_div(wm0.sclk, a); |
1179 | serge | 1053 | if (wm0.consumption_rate.full > fill_rate.full) { |
1054 | b.full = wm0.consumption_rate.full - fill_rate.full; |
||
1963 | serge | 1055 | b.full = dfixed_mul(b, wm0.active_time); |
1056 | a.full = dfixed_const(16); |
||
1057 | b.full = dfixed_div(b, a); |
||
1058 | a.full = dfixed_mul(wm0.worst_case_latency, |
||
1179 | serge | 1059 | wm0.consumption_rate); |
1060 | priority_mark02.full = a.full + b.full; |
||
1061 | } else { |
||
1963 | serge | 1062 | a.full = dfixed_mul(wm0.worst_case_latency, |
1179 | serge | 1063 | wm0.consumption_rate); |
1963 | serge | 1064 | b.full = dfixed_const(16); |
1065 | priority_mark02.full = dfixed_div(a, b); |
||
1179 | serge | 1066 | } |
1067 | if (wm0.priority_mark.full > priority_mark02.full) |
||
1068 | priority_mark02.full = wm0.priority_mark.full; |
||
1963 | serge | 1069 | if (dfixed_trunc(priority_mark02) < 0) |
1179 | serge | 1070 | priority_mark02.full = 0; |
1071 | if (wm0.priority_mark_max.full > priority_mark02.full) |
||
1072 | priority_mark02.full = wm0.priority_mark_max.full; |
||
1963 | serge | 1073 | d1mode_priority_a_cnt = dfixed_trunc(priority_mark02); |
1074 | if (rdev->disp_priority == 2) |
||
1075 | d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; |
||
1076 | } else if (mode1) { |
||
1077 | if (dfixed_trunc(wm1.dbpp) > 64) |
||
1078 | a.full = dfixed_div(wm1.dbpp, wm1.num_line_pair); |
||
1179 | serge | 1079 | else |
1080 | a.full = wm1.num_line_pair.full; |
||
1963 | serge | 1081 | fill_rate.full = dfixed_div(wm1.sclk, a); |
1179 | serge | 1082 | if (wm1.consumption_rate.full > fill_rate.full) { |
1083 | b.full = wm1.consumption_rate.full - fill_rate.full; |
||
1963 | serge | 1084 | b.full = dfixed_mul(b, wm1.active_time); |
1085 | a.full = dfixed_const(16); |
||
1086 | b.full = dfixed_div(b, a); |
||
1087 | a.full = dfixed_mul(wm1.worst_case_latency, |
||
1179 | serge | 1088 | wm1.consumption_rate); |
1089 | priority_mark12.full = a.full + b.full; |
||
1090 | } else { |
||
1963 | serge | 1091 | a.full = dfixed_mul(wm1.worst_case_latency, |
1179 | serge | 1092 | wm1.consumption_rate); |
1963 | serge | 1093 | b.full = dfixed_const(16 * 1000); |
1094 | priority_mark12.full = dfixed_div(a, b); |
||
1179 | serge | 1095 | } |
1096 | if (wm1.priority_mark.full > priority_mark12.full) |
||
1097 | priority_mark12.full = wm1.priority_mark.full; |
||
1963 | serge | 1098 | if (dfixed_trunc(priority_mark12) < 0) |
1179 | serge | 1099 | priority_mark12.full = 0; |
1100 | if (wm1.priority_mark_max.full > priority_mark12.full) |
||
1101 | priority_mark12.full = wm1.priority_mark_max.full; |
||
1963 | serge | 1102 | d2mode_priority_a_cnt = dfixed_trunc(priority_mark12); |
1103 | if (rdev->disp_priority == 2) |
||
1104 | d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; |
||
1179 | serge | 1105 | } |
1963 | serge | 1106 | |
1107 | WREG32(D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt); |
||
1108 | WREG32(D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt); |
||
1109 | WREG32(D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt); |
||
1110 | WREG32(D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt); |
||
1117 | serge | 1111 | } |
1179 | serge | 1112 | |
1113 | void rv515_bandwidth_update(struct radeon_device *rdev) |
||
1114 | { |
||
1115 | uint32_t tmp; |
||
1116 | struct drm_display_mode *mode0 = NULL; |
||
1117 | struct drm_display_mode *mode1 = NULL; |
||
1118 | |||
1963 | serge | 1119 | radeon_update_display_priority(rdev); |
1120 | |||
1179 | serge | 1121 | if (rdev->mode_info.crtcs[0]->base.enabled) |
1122 | mode0 = &rdev->mode_info.crtcs[0]->base.mode; |
||
1123 | if (rdev->mode_info.crtcs[1]->base.enabled) |
||
1124 | mode1 = &rdev->mode_info.crtcs[1]->base.mode; |
||
1125 | /* |
||
1126 | * Set display0/1 priority up in the memory controller for |
||
1127 | * modes if the user specifies HIGH for displaypriority |
||
1128 | * option. |
||
1129 | */ |
||
1963 | serge | 1130 | if ((rdev->disp_priority == 2) && |
1131 | (rdev->family == CHIP_RV515)) { |
||
1179 | serge | 1132 | tmp = RREG32_MC(MC_MISC_LAT_TIMER); |
1133 | tmp &= ~MC_DISP1R_INIT_LAT_MASK; |
||
1134 | tmp &= ~MC_DISP0R_INIT_LAT_MASK; |
||
1135 | if (mode1) |
||
1136 | tmp |= (1 << MC_DISP1R_INIT_LAT_SHIFT); |
||
1137 | if (mode0) |
||
1138 | tmp |= (1 << MC_DISP0R_INIT_LAT_SHIFT); |
||
1139 | WREG32_MC(MC_MISC_LAT_TIMER, tmp); |
||
1140 | } |
||
1141 | rv515_bandwidth_avivo_update(rdev); |
||
1142 | }><>><>>>>>><>>>>>>>><>><>>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><> |