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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 1117 | serge | 1 | /* |
| 2 | * Copyright 2008 Advanced Micro Devices, Inc. |
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| 3 | * Copyright 2008 Red Hat Inc. |
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| 4 | * Copyright 2009 Jerome Glisse. |
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| 5 | * |
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| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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| 7 | * copy of this software and associated documentation files (the "Software"), |
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| 8 | * to deal in the Software without restriction, including without limitation |
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| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
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| 11 | * Software is furnished to do so, subject to the following conditions: |
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| 12 | * |
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| 13 | * The above copyright notice and this permission notice shall be included in |
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| 14 | * all copies or substantial portions of the Software. |
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| 15 | * |
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| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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| 19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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| 20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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| 21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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| 22 | * OTHER DEALINGS IN THE SOFTWARE. |
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| 23 | * |
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| 24 | * Authors: Dave Airlie |
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| 25 | * Alex Deucher |
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| 26 | * Jerome Glisse |
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| 27 | */ |
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| 1179 | serge | 28 | #include |
| 1125 | serge | 29 | #include "drmP.h" |
| 1179 | serge | 30 | #include "rv515d.h" |
| 1117 | serge | 31 | #include "radeon.h" |
| 32 | |||
| 1179 | serge | 33 | #include "rv515_reg_safe.h" |
| 1117 | serge | 34 | /* rv515 depends on : */ |
| 35 | void r100_hdp_reset(struct radeon_device *rdev); |
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| 36 | int r100_cp_reset(struct radeon_device *rdev); |
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| 37 | int r100_rb2d_reset(struct radeon_device *rdev); |
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| 38 | int r100_gui_wait_for_idle(struct radeon_device *rdev); |
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| 39 | int r100_cp_init(struct radeon_device *rdev, unsigned ring_size); |
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| 40 | void r420_pipes_init(struct radeon_device *rdev); |
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| 41 | void rs600_mc_disable_clients(struct radeon_device *rdev); |
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| 42 | void rs600_disable_vga(struct radeon_device *rdev); |
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| 43 | |||
| 44 | /* This files gather functions specifics to: |
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| 45 | * rv515 |
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| 46 | * |
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| 47 | * Some of these functions might be used by newer ASICs. |
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| 48 | */ |
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| 49 | int rv515_debugfs_pipes_info_init(struct radeon_device *rdev); |
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| 50 | int rv515_debugfs_ga_info_init(struct radeon_device *rdev); |
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| 51 | void rv515_gpu_init(struct radeon_device *rdev); |
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| 52 | int rv515_mc_wait_for_idle(struct radeon_device *rdev); |
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| 53 | |||
| 1179 | serge | 54 | |
| 1117 | serge | 55 | /* |
| 56 | * MC |
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| 57 | */ |
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| 58 | int rv515_mc_init(struct radeon_device *rdev) |
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| 59 | { |
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| 60 | uint32_t tmp; |
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| 61 | int r; |
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| 62 | |||
| 1129 | serge | 63 | if (r100_debugfs_rbbm_init(rdev)) { |
| 64 | DRM_ERROR("Failed to register debugfs file for RBBM !\n"); |
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| 65 | } |
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| 66 | if (rv515_debugfs_pipes_info_init(rdev)) { |
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| 67 | DRM_ERROR("Failed to register debugfs file for pipes !\n"); |
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| 68 | } |
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| 69 | if (rv515_debugfs_ga_info_init(rdev)) { |
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| 70 | DRM_ERROR("Failed to register debugfs file for pipes !\n"); |
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| 71 | } |
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| 1117 | serge | 72 | |
| 73 | rv515_gpu_init(rdev); |
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| 74 | rv370_pcie_gart_disable(rdev); |
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| 75 | |||
| 76 | /* Setup GPU memory space */ |
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| 77 | rdev->mc.vram_location = 0xFFFFFFFFUL; |
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| 78 | rdev->mc.gtt_location = 0xFFFFFFFFUL; |
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| 1179 | serge | 79 | // if (rdev->flags & RADEON_IS_AGP) { |
| 80 | // r = radeon_agp_init(rdev); |
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| 81 | // if (r) { |
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| 82 | // printk(KERN_WARNING "[drm] Disabling AGP\n"); |
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| 83 | // rdev->flags &= ~RADEON_IS_AGP; |
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| 84 | // rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; |
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| 85 | // } else { |
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| 86 | // rdev->mc.gtt_location = rdev->mc.agp_base; |
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| 87 | // } |
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| 88 | // } |
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| 1117 | serge | 89 | r = radeon_mc_setup(rdev); |
| 90 | if (r) { |
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| 91 | return r; |
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| 92 | } |
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| 93 | |||
| 94 | /* Program GPU memory space */ |
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| 95 | rs600_mc_disable_clients(rdev); |
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| 96 | if (rv515_mc_wait_for_idle(rdev)) { |
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| 97 | printk(KERN_WARNING "Failed to wait MC idle while " |
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| 98 | "programming pipes. Bad things might happen.\n"); |
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| 99 | } |
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| 100 | /* Write VRAM size in case we are limiting it */ |
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| 1179 | serge | 101 | WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size); |
| 102 | tmp = REG_SET(MC_FB_START, rdev->mc.vram_location >> 16); |
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| 1117 | serge | 103 | WREG32(0x134, tmp); |
| 1179 | serge | 104 | tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1; |
| 105 | tmp = REG_SET(MC_FB_TOP, tmp >> 16); |
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| 106 | tmp |= REG_SET(MC_FB_START, rdev->mc.vram_location >> 16); |
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| 107 | WREG32_MC(MC_FB_LOCATION, tmp); |
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| 108 | WREG32(HDP_FB_LOCATION, rdev->mc.vram_location >> 16); |
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| 1117 | serge | 109 | WREG32(0x310, rdev->mc.vram_location); |
| 110 | if (rdev->flags & RADEON_IS_AGP) { |
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| 111 | tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1; |
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| 1179 | serge | 112 | tmp = REG_SET(MC_AGP_TOP, tmp >> 16); |
| 113 | tmp |= REG_SET(MC_AGP_START, rdev->mc.gtt_location >> 16); |
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| 114 | WREG32_MC(MC_AGP_LOCATION, tmp); |
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| 115 | WREG32_MC(MC_AGP_BASE, rdev->mc.agp_base); |
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| 116 | WREG32_MC(MC_AGP_BASE_2, 0); |
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| 1117 | serge | 117 | } else { |
| 1179 | serge | 118 | WREG32_MC(MC_AGP_LOCATION, 0x0FFFFFFF); |
| 119 | WREG32_MC(MC_AGP_BASE, 0); |
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| 120 | WREG32_MC(MC_AGP_BASE_2, 0); |
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| 1117 | serge | 121 | } |
| 122 | return 0; |
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| 123 | } |
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| 124 | |||
| 125 | void rv515_mc_fini(struct radeon_device *rdev) |
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| 126 | { |
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| 127 | } |
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| 128 | |||
| 129 | |||
| 130 | /* |
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| 131 | * Global GPU functions |
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| 132 | */ |
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| 133 | void rv515_ring_start(struct radeon_device *rdev) |
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| 134 | { |
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| 135 | int r; |
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| 136 | |||
| 1179 | serge | 137 | ENTER(); |
| 1117 | serge | 138 | |
| 139 | r = radeon_ring_lock(rdev, 64); |
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| 140 | if (r) { |
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| 141 | return; |
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| 142 | } |
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| 1179 | serge | 143 | radeon_ring_write(rdev, PACKET0(ISYNC_CNTL, 0)); |
| 1117 | serge | 144 | radeon_ring_write(rdev, |
| 1179 | serge | 145 | ISYNC_ANY2D_IDLE3D | |
| 146 | ISYNC_ANY3D_IDLE2D | |
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| 147 | ISYNC_WAIT_IDLEGUI | |
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| 148 | ISYNC_CPSCRATCH_IDLEGUI); |
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| 149 | radeon_ring_write(rdev, PACKET0(WAIT_UNTIL, 0)); |
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| 150 | radeon_ring_write(rdev, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN); |
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| 1117 | serge | 151 | radeon_ring_write(rdev, PACKET0(0x170C, 0)); |
| 152 | radeon_ring_write(rdev, 1 << 31); |
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| 1179 | serge | 153 | radeon_ring_write(rdev, PACKET0(GB_SELECT, 0)); |
| 1117 | serge | 154 | radeon_ring_write(rdev, 0); |
| 1179 | serge | 155 | radeon_ring_write(rdev, PACKET0(GB_ENABLE, 0)); |
| 1117 | serge | 156 | radeon_ring_write(rdev, 0); |
| 157 | radeon_ring_write(rdev, PACKET0(0x42C8, 0)); |
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| 158 | radeon_ring_write(rdev, (1 << rdev->num_gb_pipes) - 1); |
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| 1179 | serge | 159 | radeon_ring_write(rdev, PACKET0(VAP_INDEX_OFFSET, 0)); |
| 1117 | serge | 160 | radeon_ring_write(rdev, 0); |
| 1179 | serge | 161 | radeon_ring_write(rdev, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0)); |
| 162 | radeon_ring_write(rdev, RB3D_DC_FLUSH | RB3D_DC_FREE); |
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| 163 | radeon_ring_write(rdev, PACKET0(ZB_ZCACHE_CTLSTAT, 0)); |
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| 164 | radeon_ring_write(rdev, ZC_FLUSH | ZC_FREE); |
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| 165 | radeon_ring_write(rdev, PACKET0(WAIT_UNTIL, 0)); |
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| 166 | radeon_ring_write(rdev, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN); |
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| 167 | radeon_ring_write(rdev, PACKET0(GB_AA_CONFIG, 0)); |
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| 1117 | serge | 168 | radeon_ring_write(rdev, 0); |
| 1179 | serge | 169 | radeon_ring_write(rdev, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0)); |
| 170 | radeon_ring_write(rdev, RB3D_DC_FLUSH | RB3D_DC_FREE); |
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| 171 | radeon_ring_write(rdev, PACKET0(ZB_ZCACHE_CTLSTAT, 0)); |
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| 172 | radeon_ring_write(rdev, ZC_FLUSH | ZC_FREE); |
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| 173 | radeon_ring_write(rdev, PACKET0(GB_MSPOS0, 0)); |
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| 1117 | serge | 174 | radeon_ring_write(rdev, |
| 1179 | serge | 175 | ((6 << MS_X0_SHIFT) | |
| 176 | (6 << MS_Y0_SHIFT) | |
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| 177 | (6 << MS_X1_SHIFT) | |
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| 178 | (6 << MS_Y1_SHIFT) | |
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| 179 | (6 << MS_X2_SHIFT) | |
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| 180 | (6 << MS_Y2_SHIFT) | |
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| 181 | (6 << MSBD0_Y_SHIFT) | |
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| 182 | (6 << MSBD0_X_SHIFT))); |
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| 183 | radeon_ring_write(rdev, PACKET0(GB_MSPOS1, 0)); |
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| 1117 | serge | 184 | radeon_ring_write(rdev, |
| 1179 | serge | 185 | ((6 << MS_X3_SHIFT) | |
| 186 | (6 << MS_Y3_SHIFT) | |
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| 187 | (6 << MS_X4_SHIFT) | |
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| 188 | (6 << MS_Y4_SHIFT) | |
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| 189 | (6 << MS_X5_SHIFT) | |
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| 190 | (6 << MS_Y5_SHIFT) | |
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| 191 | (6 << MSBD1_SHIFT))); |
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| 192 | radeon_ring_write(rdev, PACKET0(GA_ENHANCE, 0)); |
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| 193 | radeon_ring_write(rdev, GA_DEADLOCK_CNTL | GA_FASTSYNC_CNTL); |
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| 194 | radeon_ring_write(rdev, PACKET0(GA_POLY_MODE, 0)); |
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| 195 | radeon_ring_write(rdev, FRONT_PTYPE_TRIANGE | BACK_PTYPE_TRIANGE); |
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| 196 | radeon_ring_write(rdev, PACKET0(GA_ROUND_MODE, 0)); |
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| 197 | radeon_ring_write(rdev, GEOMETRY_ROUND_NEAREST | COLOR_ROUND_NEAREST); |
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| 1117 | serge | 198 | radeon_ring_write(rdev, PACKET0(0x20C8, 0)); |
| 199 | radeon_ring_write(rdev, 0); |
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| 200 | radeon_ring_unlock_commit(rdev); |
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| 1119 | serge | 201 | |
| 1179 | serge | 202 | LEAVE(); |
| 1119 | serge | 203 | |
| 1117 | serge | 204 | } |
| 205 | |||
| 206 | void rv515_errata(struct radeon_device *rdev) |
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| 207 | { |
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| 208 | rdev->pll_errata = 0; |
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| 209 | } |
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| 210 | |||
| 211 | int rv515_mc_wait_for_idle(struct radeon_device *rdev) |
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| 212 | { |
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| 213 | unsigned i; |
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| 214 | uint32_t tmp; |
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| 215 | |||
| 216 | for (i = 0; i < rdev->usec_timeout; i++) { |
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| 217 | /* read MC_STATUS */ |
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| 1179 | serge | 218 | tmp = RREG32_MC(MC_STATUS); |
| 219 | if (tmp & MC_STATUS_IDLE) { |
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| 1117 | serge | 220 | return 0; |
| 221 | } |
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| 222 | DRM_UDELAY(1); |
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| 223 | } |
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| 224 | return -1; |
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| 225 | } |
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| 226 | |||
| 227 | void rv515_gpu_init(struct radeon_device *rdev) |
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| 228 | { |
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| 229 | unsigned pipe_select_current, gb_pipe_select, tmp; |
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| 230 | |||
| 231 | r100_hdp_reset(rdev); |
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| 232 | r100_rb2d_reset(rdev); |
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| 233 | |||
| 234 | if (r100_gui_wait_for_idle(rdev)) { |
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| 235 | printk(KERN_WARNING "Failed to wait GUI idle while " |
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| 236 | "reseting GPU. Bad things might happen.\n"); |
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| 237 | } |
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| 238 | |||
| 239 | rs600_disable_vga(rdev); |
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| 240 | |||
| 241 | r420_pipes_init(rdev); |
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| 242 | gb_pipe_select = RREG32(0x402C); |
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| 243 | tmp = RREG32(0x170C); |
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| 244 | pipe_select_current = (tmp >> 2) & 3; |
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| 245 | tmp = (1 << pipe_select_current) | |
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| 246 | (((gb_pipe_select >> 8) & 0xF) << 4); |
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| 247 | WREG32_PLL(0x000D, tmp); |
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| 248 | if (r100_gui_wait_for_idle(rdev)) { |
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| 249 | printk(KERN_WARNING "Failed to wait GUI idle while " |
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| 250 | "reseting GPU. Bad things might happen.\n"); |
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| 251 | } |
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| 252 | if (rv515_mc_wait_for_idle(rdev)) { |
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| 253 | printk(KERN_WARNING "Failed to wait MC idle while " |
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| 254 | "programming pipes. Bad things might happen.\n"); |
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| 255 | } |
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| 256 | } |
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| 257 | |||
| 258 | int rv515_ga_reset(struct radeon_device *rdev) |
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| 259 | { |
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| 260 | uint32_t tmp; |
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| 261 | bool reinit_cp; |
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| 262 | int i; |
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| 263 | |||
| 1179 | serge | 264 | ENTER(); |
| 1117 | serge | 265 | |
| 266 | reinit_cp = rdev->cp.ready; |
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| 267 | rdev->cp.ready = false; |
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| 268 | for (i = 0; i < rdev->usec_timeout; i++) { |
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| 1179 | serge | 269 | WREG32(CP_CSQ_MODE, 0); |
| 270 | WREG32(CP_CSQ_CNTL, 0); |
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| 271 | WREG32(RBBM_SOFT_RESET, 0x32005); |
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| 272 | (void)RREG32(RBBM_SOFT_RESET); |
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| 1117 | serge | 273 | udelay(200); |
| 1179 | serge | 274 | WREG32(RBBM_SOFT_RESET, 0); |
| 1117 | serge | 275 | /* Wait to prevent race in RBBM_STATUS */ |
| 276 | mdelay(1); |
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| 1179 | serge | 277 | tmp = RREG32(RBBM_STATUS); |
| 1117 | serge | 278 | if (tmp & ((1 << 20) | (1 << 26))) { |
| 279 | DRM_ERROR("VAP & CP still busy (RBBM_STATUS=0x%08X)\n", tmp); |
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| 280 | /* GA still busy soft reset it */ |
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| 281 | WREG32(0x429C, 0x200); |
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| 1179 | serge | 282 | WREG32(VAP_PVS_STATE_FLUSH_REG, 0); |
| 1117 | serge | 283 | WREG32(0x43E0, 0); |
| 284 | WREG32(0x43E4, 0); |
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| 285 | WREG32(0x24AC, 0); |
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| 286 | } |
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| 287 | /* Wait to prevent race in RBBM_STATUS */ |
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| 288 | mdelay(1); |
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| 1179 | serge | 289 | tmp = RREG32(RBBM_STATUS); |
| 1117 | serge | 290 | if (!(tmp & ((1 << 20) | (1 << 26)))) { |
| 291 | break; |
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| 292 | } |
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| 293 | } |
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| 294 | for (i = 0; i < rdev->usec_timeout; i++) { |
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| 1179 | serge | 295 | tmp = RREG32(RBBM_STATUS); |
| 1117 | serge | 296 | if (!(tmp & ((1 << 20) | (1 << 26)))) { |
| 297 | DRM_INFO("GA reset succeed (RBBM_STATUS=0x%08X)\n", |
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| 298 | tmp); |
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| 299 | DRM_INFO("GA_IDLE=0x%08X\n", RREG32(0x425C)); |
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| 300 | DRM_INFO("RB3D_RESET_STATUS=0x%08X\n", RREG32(0x46f0)); |
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| 301 | DRM_INFO("ISYNC_CNTL=0x%08X\n", RREG32(0x1724)); |
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| 302 | if (reinit_cp) { |
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| 303 | return r100_cp_init(rdev, rdev->cp.ring_size); |
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| 304 | } |
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| 305 | return 0; |
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| 306 | } |
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| 307 | DRM_UDELAY(1); |
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| 308 | } |
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| 1179 | serge | 309 | tmp = RREG32(RBBM_STATUS); |
| 1117 | serge | 310 | DRM_ERROR("Failed to reset GA ! (RBBM_STATUS=0x%08X)\n", tmp); |
| 311 | return -1; |
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| 312 | } |
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| 313 | |||
| 314 | int rv515_gpu_reset(struct radeon_device *rdev) |
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| 315 | { |
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| 316 | uint32_t status; |
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| 317 | |||
| 1179 | serge | 318 | ENTER(); |
| 1117 | serge | 319 | |
| 320 | /* reset order likely matter */ |
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| 1179 | serge | 321 | status = RREG32(RBBM_STATUS); |
| 1117 | serge | 322 | /* reset HDP */ |
| 323 | r100_hdp_reset(rdev); |
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| 324 | /* reset rb2d */ |
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| 325 | if (status & ((1 << 17) | (1 << 18) | (1 << 27))) { |
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| 326 | r100_rb2d_reset(rdev); |
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| 327 | } |
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| 328 | /* reset GA */ |
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| 329 | if (status & ((1 << 20) | (1 << 26))) { |
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| 330 | rv515_ga_reset(rdev); |
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| 331 | } |
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| 332 | /* reset CP */ |
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| 1179 | serge | 333 | status = RREG32(RBBM_STATUS); |
| 1117 | serge | 334 | if (status & (1 << 16)) { |
| 335 | r100_cp_reset(rdev); |
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| 336 | } |
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| 337 | /* Check if GPU is idle */ |
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| 1179 | serge | 338 | status = RREG32(RBBM_STATUS); |
| 1117 | serge | 339 | if (status & (1 << 31)) { |
| 340 | DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status); |
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| 341 | return -1; |
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| 342 | } |
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| 343 | DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status); |
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| 344 | return 0; |
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| 345 | } |
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| 346 | |||
| 347 | |||
| 348 | /* |
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| 349 | * VRAM info |
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| 350 | */ |
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| 351 | static void rv515_vram_get_type(struct radeon_device *rdev) |
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| 352 | { |
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| 353 | uint32_t tmp; |
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| 354 | |||
| 355 | rdev->mc.vram_width = 128; |
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| 356 | rdev->mc.vram_is_ddr = true; |
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| 1179 | serge | 357 | tmp = RREG32_MC(RV515_MC_CNTL) & MEM_NUM_CHANNELS_MASK; |
| 1117 | serge | 358 | switch (tmp) { |
| 359 | case 0: |
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| 360 | rdev->mc.vram_width = 64; |
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| 361 | break; |
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| 362 | case 1: |
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| 363 | rdev->mc.vram_width = 128; |
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| 364 | break; |
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| 365 | default: |
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| 366 | rdev->mc.vram_width = 128; |
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| 367 | break; |
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| 368 | } |
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| 369 | } |
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| 370 | |||
| 371 | void rv515_vram_info(struct radeon_device *rdev) |
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| 372 | { |
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| 1179 | serge | 373 | fixed20_12 a; |
| 374 | |||
| 1117 | serge | 375 | rv515_vram_get_type(rdev); |
| 376 | |||
| 1179 | serge | 377 | r100_vram_init_sizes(rdev); |
| 378 | /* FIXME: we should enforce default clock in case GPU is not in |
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| 379 | * default setup |
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| 380 | */ |
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| 381 | a.full = rfixed_const(100); |
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| 382 | rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk); |
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| 383 | rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a); |
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| 1117 | serge | 384 | } |
| 385 | |||
| 386 | |||
| 387 | /* |
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| 388 | * Indirect registers accessor |
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| 389 | */ |
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| 390 | uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg) |
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| 391 | { |
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| 392 | uint32_t r; |
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| 393 | |||
| 1179 | serge | 394 | WREG32(MC_IND_INDEX, 0x7f0000 | (reg & 0xffff)); |
| 395 | r = RREG32(MC_IND_DATA); |
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| 396 | WREG32(MC_IND_INDEX, 0); |
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| 1117 | serge | 397 | return r; |
| 398 | } |
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| 399 | |||
| 400 | void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
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| 401 | { |
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| 1179 | serge | 402 | WREG32(MC_IND_INDEX, 0xff0000 | ((reg) & 0xffff)); |
| 403 | WREG32(MC_IND_DATA, (v)); |
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| 404 | WREG32(MC_IND_INDEX, 0); |
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| 1117 | serge | 405 | } |
| 406 | |||
| 407 | /* |
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| 408 | * Debugfs info |
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| 409 | */ |
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| 410 | #if defined(CONFIG_DEBUG_FS) |
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| 411 | static int rv515_debugfs_pipes_info(struct seq_file *m, void *data) |
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| 412 | { |
||
| 413 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
||
| 414 | struct drm_device *dev = node->minor->dev; |
||
| 415 | struct radeon_device *rdev = dev->dev_private; |
||
| 416 | uint32_t tmp; |
||
| 417 | |||
| 1179 | serge | 418 | tmp = RREG32(GB_PIPE_SELECT); |
| 1117 | serge | 419 | seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp); |
| 1179 | serge | 420 | tmp = RREG32(SU_REG_DEST); |
| 1117 | serge | 421 | seq_printf(m, "SU_REG_DEST 0x%08x\n", tmp); |
| 1179 | serge | 422 | tmp = RREG32(GB_TILE_CONFIG); |
| 1117 | serge | 423 | seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp); |
| 1179 | serge | 424 | tmp = RREG32(DST_PIPE_CONFIG); |
| 1117 | serge | 425 | seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp); |
| 426 | return 0; |
||
| 427 | } |
||
| 428 | |||
| 429 | static int rv515_debugfs_ga_info(struct seq_file *m, void *data) |
||
| 430 | { |
||
| 431 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
||
| 432 | struct drm_device *dev = node->minor->dev; |
||
| 433 | struct radeon_device *rdev = dev->dev_private; |
||
| 434 | uint32_t tmp; |
||
| 435 | |||
| 436 | tmp = RREG32(0x2140); |
||
| 437 | seq_printf(m, "VAP_CNTL_STATUS 0x%08x\n", tmp); |
||
| 438 | radeon_gpu_reset(rdev); |
||
| 439 | tmp = RREG32(0x425C); |
||
| 440 | seq_printf(m, "GA_IDLE 0x%08x\n", tmp); |
||
| 441 | return 0; |
||
| 442 | } |
||
| 443 | |||
| 444 | static struct drm_info_list rv515_pipes_info_list[] = { |
||
| 445 | {"rv515_pipes_info", rv515_debugfs_pipes_info, 0, NULL}, |
||
| 446 | }; |
||
| 447 | |||
| 448 | static struct drm_info_list rv515_ga_info_list[] = { |
||
| 449 | {"rv515_ga_info", rv515_debugfs_ga_info, 0, NULL}, |
||
| 450 | }; |
||
| 451 | #endif |
||
| 452 | |||
| 453 | int rv515_debugfs_pipes_info_init(struct radeon_device *rdev) |
||
| 454 | { |
||
| 455 | #if defined(CONFIG_DEBUG_FS) |
||
| 456 | return radeon_debugfs_add_files(rdev, rv515_pipes_info_list, 1); |
||
| 457 | #else |
||
| 458 | return 0; |
||
| 459 | #endif |
||
| 460 | } |
||
| 461 | |||
| 462 | int rv515_debugfs_ga_info_init(struct radeon_device *rdev) |
||
| 463 | { |
||
| 464 | #if defined(CONFIG_DEBUG_FS) |
||
| 465 | return radeon_debugfs_add_files(rdev, rv515_ga_info_list, 1); |
||
| 466 | #else |
||
| 467 | return 0; |
||
| 468 | #endif |
||
| 469 | } |
||
| 470 | |||
| 471 | /* |
||
| 472 | * Asic initialization |
||
| 473 | */ |
||
| 1179 | serge | 474 | int rv515_init(struct radeon_device *rdev) |
| 475 | { |
||
| 476 | ENTER(); |
||
| 477 | |||
| 478 | rdev->config.r300.reg_safe_bm = rv515_reg_safe_bm; |
||
| 479 | rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rv515_reg_safe_bm); |
||
| 480 | return 0; |
||
| 481 | } |
||
| 482 | |||
| 483 | void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *crtc) |
||
| 484 | { |
||
| 485 | int index_reg = 0x6578 + crtc->crtc_offset; |
||
| 486 | int data_reg = 0x657c + crtc->crtc_offset; |
||
| 487 | |||
| 488 | WREG32(0x659C + crtc->crtc_offset, 0x0); |
||
| 489 | WREG32(0x6594 + crtc->crtc_offset, 0x705); |
||
| 490 | WREG32(0x65A4 + crtc->crtc_offset, 0x10001); |
||
| 491 | WREG32(0x65D8 + crtc->crtc_offset, 0x0); |
||
| 492 | WREG32(0x65B0 + crtc->crtc_offset, 0x0); |
||
| 493 | WREG32(0x65C0 + crtc->crtc_offset, 0x0); |
||
| 494 | WREG32(0x65D4 + crtc->crtc_offset, 0x0); |
||
| 495 | WREG32(index_reg, 0x0); |
||
| 496 | WREG32(data_reg, 0x841880A8); |
||
| 497 | WREG32(index_reg, 0x1); |
||
| 498 | WREG32(data_reg, 0x84208680); |
||
| 499 | WREG32(index_reg, 0x2); |
||
| 500 | WREG32(data_reg, 0xBFF880B0); |
||
| 501 | WREG32(index_reg, 0x100); |
||
| 502 | WREG32(data_reg, 0x83D88088); |
||
| 503 | WREG32(index_reg, 0x101); |
||
| 504 | WREG32(data_reg, 0x84608680); |
||
| 505 | WREG32(index_reg, 0x102); |
||
| 506 | WREG32(data_reg, 0xBFF080D0); |
||
| 507 | WREG32(index_reg, 0x200); |
||
| 508 | WREG32(data_reg, 0x83988068); |
||
| 509 | WREG32(index_reg, 0x201); |
||
| 510 | WREG32(data_reg, 0x84A08680); |
||
| 511 | WREG32(index_reg, 0x202); |
||
| 512 | WREG32(data_reg, 0xBFF080F8); |
||
| 513 | WREG32(index_reg, 0x300); |
||
| 514 | WREG32(data_reg, 0x83588058); |
||
| 515 | WREG32(index_reg, 0x301); |
||
| 516 | WREG32(data_reg, 0x84E08660); |
||
| 517 | WREG32(index_reg, 0x302); |
||
| 518 | WREG32(data_reg, 0xBFF88120); |
||
| 519 | WREG32(index_reg, 0x400); |
||
| 520 | WREG32(data_reg, 0x83188040); |
||
| 521 | WREG32(index_reg, 0x401); |
||
| 522 | WREG32(data_reg, 0x85008660); |
||
| 523 | WREG32(index_reg, 0x402); |
||
| 524 | WREG32(data_reg, 0xBFF88150); |
||
| 525 | WREG32(index_reg, 0x500); |
||
| 526 | WREG32(data_reg, 0x82D88030); |
||
| 527 | WREG32(index_reg, 0x501); |
||
| 528 | WREG32(data_reg, 0x85408640); |
||
| 529 | WREG32(index_reg, 0x502); |
||
| 530 | WREG32(data_reg, 0xBFF88180); |
||
| 531 | WREG32(index_reg, 0x600); |
||
| 532 | WREG32(data_reg, 0x82A08018); |
||
| 533 | WREG32(index_reg, 0x601); |
||
| 534 | WREG32(data_reg, 0x85808620); |
||
| 535 | WREG32(index_reg, 0x602); |
||
| 536 | WREG32(data_reg, 0xBFF081B8); |
||
| 537 | WREG32(index_reg, 0x700); |
||
| 538 | WREG32(data_reg, 0x82608010); |
||
| 539 | WREG32(index_reg, 0x701); |
||
| 540 | WREG32(data_reg, 0x85A08600); |
||
| 541 | WREG32(index_reg, 0x702); |
||
| 542 | WREG32(data_reg, 0x800081F0); |
||
| 543 | WREG32(index_reg, 0x800); |
||
| 544 | WREG32(data_reg, 0x8228BFF8); |
||
| 545 | WREG32(index_reg, 0x801); |
||
| 546 | WREG32(data_reg, 0x85E085E0); |
||
| 547 | WREG32(index_reg, 0x802); |
||
| 548 | WREG32(data_reg, 0xBFF88228); |
||
| 549 | WREG32(index_reg, 0x10000); |
||
| 550 | WREG32(data_reg, 0x82A8BF00); |
||
| 551 | WREG32(index_reg, 0x10001); |
||
| 552 | WREG32(data_reg, 0x82A08CC0); |
||
| 553 | WREG32(index_reg, 0x10002); |
||
| 554 | WREG32(data_reg, 0x8008BEF8); |
||
| 555 | WREG32(index_reg, 0x10100); |
||
| 556 | WREG32(data_reg, 0x81F0BF28); |
||
| 557 | WREG32(index_reg, 0x10101); |
||
| 558 | WREG32(data_reg, 0x83608CA0); |
||
| 559 | WREG32(index_reg, 0x10102); |
||
| 560 | WREG32(data_reg, 0x8018BED0); |
||
| 561 | WREG32(index_reg, 0x10200); |
||
| 562 | WREG32(data_reg, 0x8148BF38); |
||
| 563 | WREG32(index_reg, 0x10201); |
||
| 564 | WREG32(data_reg, 0x84408C80); |
||
| 565 | WREG32(index_reg, 0x10202); |
||
| 566 | WREG32(data_reg, 0x8008BEB8); |
||
| 567 | WREG32(index_reg, 0x10300); |
||
| 568 | WREG32(data_reg, 0x80B0BF78); |
||
| 569 | WREG32(index_reg, 0x10301); |
||
| 570 | WREG32(data_reg, 0x85008C20); |
||
| 571 | WREG32(index_reg, 0x10302); |
||
| 572 | WREG32(data_reg, 0x8020BEA0); |
||
| 573 | WREG32(index_reg, 0x10400); |
||
| 574 | WREG32(data_reg, 0x8028BF90); |
||
| 575 | WREG32(index_reg, 0x10401); |
||
| 576 | WREG32(data_reg, 0x85E08BC0); |
||
| 577 | WREG32(index_reg, 0x10402); |
||
| 578 | WREG32(data_reg, 0x8018BE90); |
||
| 579 | WREG32(index_reg, 0x10500); |
||
| 580 | WREG32(data_reg, 0xBFB8BFB0); |
||
| 581 | WREG32(index_reg, 0x10501); |
||
| 582 | WREG32(data_reg, 0x86C08B40); |
||
| 583 | WREG32(index_reg, 0x10502); |
||
| 584 | WREG32(data_reg, 0x8010BE90); |
||
| 585 | WREG32(index_reg, 0x10600); |
||
| 586 | WREG32(data_reg, 0xBF58BFC8); |
||
| 587 | WREG32(index_reg, 0x10601); |
||
| 588 | WREG32(data_reg, 0x87A08AA0); |
||
| 589 | WREG32(index_reg, 0x10602); |
||
| 590 | WREG32(data_reg, 0x8010BE98); |
||
| 591 | WREG32(index_reg, 0x10700); |
||
| 592 | WREG32(data_reg, 0xBF10BFF0); |
||
| 593 | WREG32(index_reg, 0x10701); |
||
| 594 | WREG32(data_reg, 0x886089E0); |
||
| 595 | WREG32(index_reg, 0x10702); |
||
| 596 | WREG32(data_reg, 0x8018BEB0); |
||
| 597 | WREG32(index_reg, 0x10800); |
||
| 598 | WREG32(data_reg, 0xBED8BFE8); |
||
| 599 | WREG32(index_reg, 0x10801); |
||
| 600 | WREG32(data_reg, 0x89408940); |
||
| 601 | WREG32(index_reg, 0x10802); |
||
| 602 | WREG32(data_reg, 0xBFE8BED8); |
||
| 603 | WREG32(index_reg, 0x20000); |
||
| 604 | WREG32(data_reg, 0x80008000); |
||
| 605 | WREG32(index_reg, 0x20001); |
||
| 606 | WREG32(data_reg, 0x90008000); |
||
| 607 | WREG32(index_reg, 0x20002); |
||
| 608 | WREG32(data_reg, 0x80008000); |
||
| 609 | WREG32(index_reg, 0x20003); |
||
| 610 | WREG32(data_reg, 0x80008000); |
||
| 611 | WREG32(index_reg, 0x20100); |
||
| 612 | WREG32(data_reg, 0x80108000); |
||
| 613 | WREG32(index_reg, 0x20101); |
||
| 614 | WREG32(data_reg, 0x8FE0BF70); |
||
| 615 | WREG32(index_reg, 0x20102); |
||
| 616 | WREG32(data_reg, 0xBFE880C0); |
||
| 617 | WREG32(index_reg, 0x20103); |
||
| 618 | WREG32(data_reg, 0x80008000); |
||
| 619 | WREG32(index_reg, 0x20200); |
||
| 620 | WREG32(data_reg, 0x8018BFF8); |
||
| 621 | WREG32(index_reg, 0x20201); |
||
| 622 | WREG32(data_reg, 0x8F80BF08); |
||
| 623 | WREG32(index_reg, 0x20202); |
||
| 624 | WREG32(data_reg, 0xBFD081A0); |
||
| 625 | WREG32(index_reg, 0x20203); |
||
| 626 | WREG32(data_reg, 0xBFF88000); |
||
| 627 | WREG32(index_reg, 0x20300); |
||
| 628 | WREG32(data_reg, 0x80188000); |
||
| 629 | WREG32(index_reg, 0x20301); |
||
| 630 | WREG32(data_reg, 0x8EE0BEC0); |
||
| 631 | WREG32(index_reg, 0x20302); |
||
| 632 | WREG32(data_reg, 0xBFB082A0); |
||
| 633 | WREG32(index_reg, 0x20303); |
||
| 634 | WREG32(data_reg, 0x80008000); |
||
| 635 | WREG32(index_reg, 0x20400); |
||
| 636 | WREG32(data_reg, 0x80188000); |
||
| 637 | WREG32(index_reg, 0x20401); |
||
| 638 | WREG32(data_reg, 0x8E00BEA0); |
||
| 639 | WREG32(index_reg, 0x20402); |
||
| 640 | WREG32(data_reg, 0xBF8883C0); |
||
| 641 | WREG32(index_reg, 0x20403); |
||
| 642 | WREG32(data_reg, 0x80008000); |
||
| 643 | WREG32(index_reg, 0x20500); |
||
| 644 | WREG32(data_reg, 0x80188000); |
||
| 645 | WREG32(index_reg, 0x20501); |
||
| 646 | WREG32(data_reg, 0x8D00BE90); |
||
| 647 | WREG32(index_reg, 0x20502); |
||
| 648 | WREG32(data_reg, 0xBF588500); |
||
| 649 | WREG32(index_reg, 0x20503); |
||
| 650 | WREG32(data_reg, 0x80008008); |
||
| 651 | WREG32(index_reg, 0x20600); |
||
| 652 | WREG32(data_reg, 0x80188000); |
||
| 653 | WREG32(index_reg, 0x20601); |
||
| 654 | WREG32(data_reg, 0x8BC0BE98); |
||
| 655 | WREG32(index_reg, 0x20602); |
||
| 656 | WREG32(data_reg, 0xBF308660); |
||
| 657 | WREG32(index_reg, 0x20603); |
||
| 658 | WREG32(data_reg, 0x80008008); |
||
| 659 | WREG32(index_reg, 0x20700); |
||
| 660 | WREG32(data_reg, 0x80108000); |
||
| 661 | WREG32(index_reg, 0x20701); |
||
| 662 | WREG32(data_reg, 0x8A80BEB0); |
||
| 663 | WREG32(index_reg, 0x20702); |
||
| 664 | WREG32(data_reg, 0xBF0087C0); |
||
| 665 | WREG32(index_reg, 0x20703); |
||
| 666 | WREG32(data_reg, 0x80008008); |
||
| 667 | WREG32(index_reg, 0x20800); |
||
| 668 | WREG32(data_reg, 0x80108000); |
||
| 669 | WREG32(index_reg, 0x20801); |
||
| 670 | WREG32(data_reg, 0x8920BED0); |
||
| 671 | WREG32(index_reg, 0x20802); |
||
| 672 | WREG32(data_reg, 0xBED08920); |
||
| 673 | WREG32(index_reg, 0x20803); |
||
| 674 | WREG32(data_reg, 0x80008010); |
||
| 675 | WREG32(index_reg, 0x30000); |
||
| 676 | WREG32(data_reg, 0x90008000); |
||
| 677 | WREG32(index_reg, 0x30001); |
||
| 678 | WREG32(data_reg, 0x80008000); |
||
| 679 | WREG32(index_reg, 0x30100); |
||
| 680 | WREG32(data_reg, 0x8FE0BF90); |
||
| 681 | WREG32(index_reg, 0x30101); |
||
| 682 | WREG32(data_reg, 0xBFF880A0); |
||
| 683 | WREG32(index_reg, 0x30200); |
||
| 684 | WREG32(data_reg, 0x8F60BF40); |
||
| 685 | WREG32(index_reg, 0x30201); |
||
| 686 | WREG32(data_reg, 0xBFE88180); |
||
| 687 | WREG32(index_reg, 0x30300); |
||
| 688 | WREG32(data_reg, 0x8EC0BF00); |
||
| 689 | WREG32(index_reg, 0x30301); |
||
| 690 | WREG32(data_reg, 0xBFC88280); |
||
| 691 | WREG32(index_reg, 0x30400); |
||
| 692 | WREG32(data_reg, 0x8DE0BEE0); |
||
| 693 | WREG32(index_reg, 0x30401); |
||
| 694 | WREG32(data_reg, 0xBFA083A0); |
||
| 695 | WREG32(index_reg, 0x30500); |
||
| 696 | WREG32(data_reg, 0x8CE0BED0); |
||
| 697 | WREG32(index_reg, 0x30501); |
||
| 698 | WREG32(data_reg, 0xBF7884E0); |
||
| 699 | WREG32(index_reg, 0x30600); |
||
| 700 | WREG32(data_reg, 0x8BA0BED8); |
||
| 701 | WREG32(index_reg, 0x30601); |
||
| 702 | WREG32(data_reg, 0xBF508640); |
||
| 703 | WREG32(index_reg, 0x30700); |
||
| 704 | WREG32(data_reg, 0x8A60BEE8); |
||
| 705 | WREG32(index_reg, 0x30701); |
||
| 706 | WREG32(data_reg, 0xBF2087A0); |
||
| 707 | WREG32(index_reg, 0x30800); |
||
| 708 | WREG32(data_reg, 0x8900BF00); |
||
| 709 | WREG32(index_reg, 0x30801); |
||
| 710 | WREG32(data_reg, 0xBF008900); |
||
| 711 | } |
||
| 712 | |||
| 713 | struct rv515_watermark { |
||
| 714 | u32 lb_request_fifo_depth; |
||
| 715 | fixed20_12 num_line_pair; |
||
| 716 | fixed20_12 estimated_width; |
||
| 717 | fixed20_12 worst_case_latency; |
||
| 718 | fixed20_12 consumption_rate; |
||
| 719 | fixed20_12 active_time; |
||
| 720 | fixed20_12 dbpp; |
||
| 721 | fixed20_12 priority_mark_max; |
||
| 722 | fixed20_12 priority_mark; |
||
| 723 | fixed20_12 sclk; |
||
| 1117 | serge | 724 | }; |
| 725 | |||
| 1179 | serge | 726 | void rv515_crtc_bandwidth_compute(struct radeon_device *rdev, |
| 727 | struct radeon_crtc *crtc, |
||
| 728 | struct rv515_watermark *wm) |
||
| 729 | { |
||
| 730 | struct drm_display_mode *mode = &crtc->base.mode; |
||
| 731 | fixed20_12 a, b, c; |
||
| 732 | fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width; |
||
| 733 | fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency; |
||
| 1117 | serge | 734 | |
| 1179 | serge | 735 | if (!crtc->base.enabled) { |
| 736 | /* FIXME: wouldn't it better to set priority mark to maximum */ |
||
| 737 | wm->lb_request_fifo_depth = 4; |
||
| 738 | return; |
||
| 739 | } |
||
| 1117 | serge | 740 | |
| 1179 | serge | 741 | if (crtc->vsc.full > rfixed_const(2)) |
| 742 | wm->num_line_pair.full = rfixed_const(2); |
||
| 743 | else |
||
| 744 | wm->num_line_pair.full = rfixed_const(1); |
||
| 745 | |||
| 746 | b.full = rfixed_const(mode->crtc_hdisplay); |
||
| 747 | c.full = rfixed_const(256); |
||
| 748 | a.full = rfixed_mul(wm->num_line_pair, b); |
||
| 749 | request_fifo_depth.full = rfixed_div(a, c); |
||
| 750 | if (a.full < rfixed_const(4)) { |
||
| 751 | wm->lb_request_fifo_depth = 4; |
||
| 752 | } else { |
||
| 753 | wm->lb_request_fifo_depth = rfixed_trunc(request_fifo_depth); |
||
| 754 | } |
||
| 755 | |||
| 756 | /* Determine consumption rate |
||
| 757 | * pclk = pixel clock period(ns) = 1000 / (mode.clock / 1000) |
||
| 758 | * vtaps = number of vertical taps, |
||
| 759 | * vsc = vertical scaling ratio, defined as source/destination |
||
| 760 | * hsc = horizontal scaling ration, defined as source/destination |
||
| 761 | */ |
||
| 762 | a.full = rfixed_const(mode->clock); |
||
| 763 | b.full = rfixed_const(1000); |
||
| 764 | a.full = rfixed_div(a, b); |
||
| 765 | pclk.full = rfixed_div(b, a); |
||
| 766 | if (crtc->rmx_type != RMX_OFF) { |
||
| 767 | b.full = rfixed_const(2); |
||
| 768 | if (crtc->vsc.full > b.full) |
||
| 769 | b.full = crtc->vsc.full; |
||
| 770 | b.full = rfixed_mul(b, crtc->hsc); |
||
| 771 | c.full = rfixed_const(2); |
||
| 772 | b.full = rfixed_div(b, c); |
||
| 773 | consumption_time.full = rfixed_div(pclk, b); |
||
| 774 | } else { |
||
| 775 | consumption_time.full = pclk.full; |
||
| 776 | } |
||
| 777 | a.full = rfixed_const(1); |
||
| 778 | wm->consumption_rate.full = rfixed_div(a, consumption_time); |
||
| 779 | |||
| 780 | |||
| 781 | /* Determine line time |
||
| 782 | * LineTime = total time for one line of displayhtotal |
||
| 783 | * LineTime = total number of horizontal pixels |
||
| 784 | * pclk = pixel clock period(ns) |
||
| 785 | */ |
||
| 786 | a.full = rfixed_const(crtc->base.mode.crtc_htotal); |
||
| 787 | line_time.full = rfixed_mul(a, pclk); |
||
| 788 | |||
| 789 | /* Determine active time |
||
| 790 | * ActiveTime = time of active region of display within one line, |
||
| 791 | * hactive = total number of horizontal active pixels |
||
| 792 | * htotal = total number of horizontal pixels |
||
| 793 | */ |
||
| 794 | a.full = rfixed_const(crtc->base.mode.crtc_htotal); |
||
| 795 | b.full = rfixed_const(crtc->base.mode.crtc_hdisplay); |
||
| 796 | wm->active_time.full = rfixed_mul(line_time, b); |
||
| 797 | wm->active_time.full = rfixed_div(wm->active_time, a); |
||
| 798 | |||
| 799 | /* Determine chunk time |
||
| 800 | * ChunkTime = the time it takes the DCP to send one chunk of data |
||
| 801 | * to the LB which consists of pipeline delay and inter chunk gap |
||
| 802 | * sclk = system clock(Mhz) |
||
| 803 | */ |
||
| 804 | a.full = rfixed_const(600 * 1000); |
||
| 805 | chunk_time.full = rfixed_div(a, rdev->pm.sclk); |
||
| 806 | read_delay_latency.full = rfixed_const(1000); |
||
| 807 | |||
| 808 | /* Determine the worst case latency |
||
| 809 | * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines) |
||
| 810 | * WorstCaseLatency = worst case time from urgent to when the MC starts |
||
| 811 | * to return data |
||
| 812 | * READ_DELAY_IDLE_MAX = constant of 1us |
||
| 813 | * ChunkTime = time it takes the DCP to send one chunk of data to the LB |
||
| 814 | * which consists of pipeline delay and inter chunk gap |
||
| 815 | */ |
||
| 816 | if (rfixed_trunc(wm->num_line_pair) > 1) { |
||
| 817 | a.full = rfixed_const(3); |
||
| 818 | wm->worst_case_latency.full = rfixed_mul(a, chunk_time); |
||
| 819 | wm->worst_case_latency.full += read_delay_latency.full; |
||
| 820 | } else { |
||
| 821 | wm->worst_case_latency.full = chunk_time.full + read_delay_latency.full; |
||
| 822 | } |
||
| 823 | |||
| 824 | /* Determine the tolerable latency |
||
| 825 | * TolerableLatency = Any given request has only 1 line time |
||
| 826 | * for the data to be returned |
||
| 827 | * LBRequestFifoDepth = Number of chunk requests the LB can |
||
| 828 | * put into the request FIFO for a display |
||
| 829 | * LineTime = total time for one line of display |
||
| 830 | * ChunkTime = the time it takes the DCP to send one chunk |
||
| 831 | * of data to the LB which consists of |
||
| 832 | * pipeline delay and inter chunk gap |
||
| 833 | */ |
||
| 834 | if ((2+wm->lb_request_fifo_depth) >= rfixed_trunc(request_fifo_depth)) { |
||
| 835 | tolerable_latency.full = line_time.full; |
||
| 836 | } else { |
||
| 837 | tolerable_latency.full = rfixed_const(wm->lb_request_fifo_depth - 2); |
||
| 838 | tolerable_latency.full = request_fifo_depth.full - tolerable_latency.full; |
||
| 839 | tolerable_latency.full = rfixed_mul(tolerable_latency, chunk_time); |
||
| 840 | tolerable_latency.full = line_time.full - tolerable_latency.full; |
||
| 841 | } |
||
| 842 | /* We assume worst case 32bits (4 bytes) */ |
||
| 843 | wm->dbpp.full = rfixed_const(2 * 16); |
||
| 844 | |||
| 845 | /* Determine the maximum priority mark |
||
| 846 | * width = viewport width in pixels |
||
| 847 | */ |
||
| 848 | a.full = rfixed_const(16); |
||
| 849 | wm->priority_mark_max.full = rfixed_const(crtc->base.mode.crtc_hdisplay); |
||
| 850 | wm->priority_mark_max.full = rfixed_div(wm->priority_mark_max, a); |
||
| 851 | |||
| 852 | /* Determine estimated width */ |
||
| 853 | estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full; |
||
| 854 | estimated_width.full = rfixed_div(estimated_width, consumption_time); |
||
| 855 | if (rfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) { |
||
| 856 | wm->priority_mark.full = rfixed_const(10); |
||
| 857 | } else { |
||
| 858 | a.full = rfixed_const(16); |
||
| 859 | wm->priority_mark.full = rfixed_div(estimated_width, a); |
||
| 860 | wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full; |
||
| 861 | } |
||
| 862 | } |
||
| 863 | |||
| 864 | void rv515_bandwidth_avivo_update(struct radeon_device *rdev) |
||
| 1117 | serge | 865 | { |
| 1179 | serge | 866 | struct drm_display_mode *mode0 = NULL; |
| 867 | struct drm_display_mode *mode1 = NULL; |
||
| 868 | struct rv515_watermark wm0; |
||
| 869 | struct rv515_watermark wm1; |
||
| 870 | u32 tmp; |
||
| 871 | fixed20_12 priority_mark02, priority_mark12, fill_rate; |
||
| 872 | fixed20_12 a, b; |
||
| 1117 | serge | 873 | |
| 1179 | serge | 874 | if (rdev->mode_info.crtcs[0]->base.enabled) |
| 875 | mode0 = &rdev->mode_info.crtcs[0]->base.mode; |
||
| 876 | if (rdev->mode_info.crtcs[1]->base.enabled) |
||
| 877 | mode1 = &rdev->mode_info.crtcs[1]->base.mode; |
||
| 878 | rs690_line_buffer_adjust(rdev, mode0, mode1); |
||
| 879 | |||
| 880 | rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0); |
||
| 881 | rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1); |
||
| 882 | |||
| 883 | tmp = wm0.lb_request_fifo_depth; |
||
| 884 | tmp |= wm1.lb_request_fifo_depth << 16; |
||
| 885 | WREG32(LB_MAX_REQ_OUTSTANDING, tmp); |
||
| 886 | |||
| 887 | if (mode0 && mode1) { |
||
| 888 | if (rfixed_trunc(wm0.dbpp) > 64) |
||
| 889 | a.full = rfixed_div(wm0.dbpp, wm0.num_line_pair); |
||
| 890 | else |
||
| 891 | a.full = wm0.num_line_pair.full; |
||
| 892 | if (rfixed_trunc(wm1.dbpp) > 64) |
||
| 893 | b.full = rfixed_div(wm1.dbpp, wm1.num_line_pair); |
||
| 894 | else |
||
| 895 | b.full = wm1.num_line_pair.full; |
||
| 896 | a.full += b.full; |
||
| 897 | fill_rate.full = rfixed_div(wm0.sclk, a); |
||
| 898 | if (wm0.consumption_rate.full > fill_rate.full) { |
||
| 899 | b.full = wm0.consumption_rate.full - fill_rate.full; |
||
| 900 | b.full = rfixed_mul(b, wm0.active_time); |
||
| 901 | a.full = rfixed_const(16); |
||
| 902 | b.full = rfixed_div(b, a); |
||
| 903 | a.full = rfixed_mul(wm0.worst_case_latency, |
||
| 904 | wm0.consumption_rate); |
||
| 905 | priority_mark02.full = a.full + b.full; |
||
| 906 | } else { |
||
| 907 | a.full = rfixed_mul(wm0.worst_case_latency, |
||
| 908 | wm0.consumption_rate); |
||
| 909 | b.full = rfixed_const(16 * 1000); |
||
| 910 | priority_mark02.full = rfixed_div(a, b); |
||
| 911 | } |
||
| 912 | if (wm1.consumption_rate.full > fill_rate.full) { |
||
| 913 | b.full = wm1.consumption_rate.full - fill_rate.full; |
||
| 914 | b.full = rfixed_mul(b, wm1.active_time); |
||
| 915 | a.full = rfixed_const(16); |
||
| 916 | b.full = rfixed_div(b, a); |
||
| 917 | a.full = rfixed_mul(wm1.worst_case_latency, |
||
| 918 | wm1.consumption_rate); |
||
| 919 | priority_mark12.full = a.full + b.full; |
||
| 920 | } else { |
||
| 921 | a.full = rfixed_mul(wm1.worst_case_latency, |
||
| 922 | wm1.consumption_rate); |
||
| 923 | b.full = rfixed_const(16 * 1000); |
||
| 924 | priority_mark12.full = rfixed_div(a, b); |
||
| 925 | } |
||
| 926 | if (wm0.priority_mark.full > priority_mark02.full) |
||
| 927 | priority_mark02.full = wm0.priority_mark.full; |
||
| 928 | if (rfixed_trunc(priority_mark02) < 0) |
||
| 929 | priority_mark02.full = 0; |
||
| 930 | if (wm0.priority_mark_max.full > priority_mark02.full) |
||
| 931 | priority_mark02.full = wm0.priority_mark_max.full; |
||
| 932 | if (wm1.priority_mark.full > priority_mark12.full) |
||
| 933 | priority_mark12.full = wm1.priority_mark.full; |
||
| 934 | if (rfixed_trunc(priority_mark12) < 0) |
||
| 935 | priority_mark12.full = 0; |
||
| 936 | if (wm1.priority_mark_max.full > priority_mark12.full) |
||
| 937 | priority_mark12.full = wm1.priority_mark_max.full; |
||
| 938 | WREG32(D1MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark02)); |
||
| 939 | WREG32(D1MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark02)); |
||
| 940 | WREG32(D2MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark12)); |
||
| 941 | WREG32(D2MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark12)); |
||
| 942 | } else if (mode0) { |
||
| 943 | if (rfixed_trunc(wm0.dbpp) > 64) |
||
| 944 | a.full = rfixed_div(wm0.dbpp, wm0.num_line_pair); |
||
| 945 | else |
||
| 946 | a.full = wm0.num_line_pair.full; |
||
| 947 | fill_rate.full = rfixed_div(wm0.sclk, a); |
||
| 948 | if (wm0.consumption_rate.full > fill_rate.full) { |
||
| 949 | b.full = wm0.consumption_rate.full - fill_rate.full; |
||
| 950 | b.full = rfixed_mul(b, wm0.active_time); |
||
| 951 | a.full = rfixed_const(16); |
||
| 952 | b.full = rfixed_div(b, a); |
||
| 953 | a.full = rfixed_mul(wm0.worst_case_latency, |
||
| 954 | wm0.consumption_rate); |
||
| 955 | priority_mark02.full = a.full + b.full; |
||
| 956 | } else { |
||
| 957 | a.full = rfixed_mul(wm0.worst_case_latency, |
||
| 958 | wm0.consumption_rate); |
||
| 959 | b.full = rfixed_const(16); |
||
| 960 | priority_mark02.full = rfixed_div(a, b); |
||
| 961 | } |
||
| 962 | if (wm0.priority_mark.full > priority_mark02.full) |
||
| 963 | priority_mark02.full = wm0.priority_mark.full; |
||
| 964 | if (rfixed_trunc(priority_mark02) < 0) |
||
| 965 | priority_mark02.full = 0; |
||
| 966 | if (wm0.priority_mark_max.full > priority_mark02.full) |
||
| 967 | priority_mark02.full = wm0.priority_mark_max.full; |
||
| 968 | WREG32(D1MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark02)); |
||
| 969 | WREG32(D1MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark02)); |
||
| 970 | WREG32(D2MODE_PRIORITY_A_CNT, MODE_PRIORITY_OFF); |
||
| 971 | WREG32(D2MODE_PRIORITY_B_CNT, MODE_PRIORITY_OFF); |
||
| 972 | } else { |
||
| 973 | if (rfixed_trunc(wm1.dbpp) > 64) |
||
| 974 | a.full = rfixed_div(wm1.dbpp, wm1.num_line_pair); |
||
| 975 | else |
||
| 976 | a.full = wm1.num_line_pair.full; |
||
| 977 | fill_rate.full = rfixed_div(wm1.sclk, a); |
||
| 978 | if (wm1.consumption_rate.full > fill_rate.full) { |
||
| 979 | b.full = wm1.consumption_rate.full - fill_rate.full; |
||
| 980 | b.full = rfixed_mul(b, wm1.active_time); |
||
| 981 | a.full = rfixed_const(16); |
||
| 982 | b.full = rfixed_div(b, a); |
||
| 983 | a.full = rfixed_mul(wm1.worst_case_latency, |
||
| 984 | wm1.consumption_rate); |
||
| 985 | priority_mark12.full = a.full + b.full; |
||
| 986 | } else { |
||
| 987 | a.full = rfixed_mul(wm1.worst_case_latency, |
||
| 988 | wm1.consumption_rate); |
||
| 989 | b.full = rfixed_const(16 * 1000); |
||
| 990 | priority_mark12.full = rfixed_div(a, b); |
||
| 991 | } |
||
| 992 | if (wm1.priority_mark.full > priority_mark12.full) |
||
| 993 | priority_mark12.full = wm1.priority_mark.full; |
||
| 994 | if (rfixed_trunc(priority_mark12) < 0) |
||
| 995 | priority_mark12.full = 0; |
||
| 996 | if (wm1.priority_mark_max.full > priority_mark12.full) |
||
| 997 | priority_mark12.full = wm1.priority_mark_max.full; |
||
| 998 | WREG32(D1MODE_PRIORITY_A_CNT, MODE_PRIORITY_OFF); |
||
| 999 | WREG32(D1MODE_PRIORITY_B_CNT, MODE_PRIORITY_OFF); |
||
| 1000 | WREG32(D2MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark12)); |
||
| 1001 | WREG32(D2MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark12)); |
||
| 1002 | } |
||
| 1117 | serge | 1003 | } |
| 1179 | serge | 1004 | |
| 1005 | void rv515_bandwidth_update(struct radeon_device *rdev) |
||
| 1006 | { |
||
| 1007 | uint32_t tmp; |
||
| 1008 | struct drm_display_mode *mode0 = NULL; |
||
| 1009 | struct drm_display_mode *mode1 = NULL; |
||
| 1010 | |||
| 1011 | if (rdev->mode_info.crtcs[0]->base.enabled) |
||
| 1012 | mode0 = &rdev->mode_info.crtcs[0]->base.mode; |
||
| 1013 | if (rdev->mode_info.crtcs[1]->base.enabled) |
||
| 1014 | mode1 = &rdev->mode_info.crtcs[1]->base.mode; |
||
| 1015 | /* |
||
| 1016 | * Set display0/1 priority up in the memory controller for |
||
| 1017 | * modes if the user specifies HIGH for displaypriority |
||
| 1018 | * option. |
||
| 1019 | */ |
||
| 1020 | if (rdev->disp_priority == 2) { |
||
| 1021 | tmp = RREG32_MC(MC_MISC_LAT_TIMER); |
||
| 1022 | tmp &= ~MC_DISP1R_INIT_LAT_MASK; |
||
| 1023 | tmp &= ~MC_DISP0R_INIT_LAT_MASK; |
||
| 1024 | if (mode1) |
||
| 1025 | tmp |= (1 << MC_DISP1R_INIT_LAT_SHIFT); |
||
| 1026 | if (mode0) |
||
| 1027 | tmp |= (1 << MC_DISP0R_INIT_LAT_SHIFT); |
||
| 1028 | WREG32_MC(MC_MISC_LAT_TIMER, tmp); |
||
| 1029 | } |
||
| 1030 | rv515_bandwidth_avivo_update(rdev); |
||
| 1031 | } |