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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 1117 | serge | 1 | /* |
| 2 | * Copyright 2008 Advanced Micro Devices, Inc. |
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| 3 | * Copyright 2008 Red Hat Inc. |
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| 4 | * Copyright 2009 Jerome Glisse. |
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| 5 | * |
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| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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| 7 | * copy of this software and associated documentation files (the "Software"), |
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| 8 | * to deal in the Software without restriction, including without limitation |
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| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
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| 11 | * Software is furnished to do so, subject to the following conditions: |
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| 12 | * |
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| 13 | * The above copyright notice and this permission notice shall be included in |
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| 14 | * all copies or substantial portions of the Software. |
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| 15 | * |
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| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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| 19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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| 20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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| 21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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| 22 | * OTHER DEALINGS IN THE SOFTWARE. |
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| 23 | * |
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| 24 | * Authors: Dave Airlie |
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| 25 | * Alex Deucher |
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| 26 | * Jerome Glisse |
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| 27 | */ |
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| 28 | //#include |
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| 29 | //#include "drmP.h" |
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| 30 | #include "radeon_reg.h" |
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| 31 | #include "radeon.h" |
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| 32 | |||
| 33 | /* rv515 depends on : */ |
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| 34 | void r100_hdp_reset(struct radeon_device *rdev); |
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| 35 | int r100_cp_reset(struct radeon_device *rdev); |
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| 36 | int r100_rb2d_reset(struct radeon_device *rdev); |
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| 37 | int r100_gui_wait_for_idle(struct radeon_device *rdev); |
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| 38 | int r100_cp_init(struct radeon_device *rdev, unsigned ring_size); |
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| 39 | int rv370_pcie_gart_enable(struct radeon_device *rdev); |
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| 40 | void rv370_pcie_gart_disable(struct radeon_device *rdev); |
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| 41 | void r420_pipes_init(struct radeon_device *rdev); |
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| 42 | void rs600_mc_disable_clients(struct radeon_device *rdev); |
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| 43 | void rs600_disable_vga(struct radeon_device *rdev); |
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| 44 | |||
| 45 | /* This files gather functions specifics to: |
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| 46 | * rv515 |
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| 47 | * |
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| 48 | * Some of these functions might be used by newer ASICs. |
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| 49 | */ |
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| 50 | int rv515_debugfs_pipes_info_init(struct radeon_device *rdev); |
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| 51 | int rv515_debugfs_ga_info_init(struct radeon_device *rdev); |
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| 52 | void rv515_gpu_init(struct radeon_device *rdev); |
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| 53 | int rv515_mc_wait_for_idle(struct radeon_device *rdev); |
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| 54 | |||
| 55 | #if 0 |
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| 56 | /* |
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| 57 | * MC |
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| 58 | */ |
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| 59 | int rv515_mc_init(struct radeon_device *rdev) |
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| 60 | { |
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| 61 | uint32_t tmp; |
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| 62 | int r; |
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| 63 | |||
| 64 | if (r100_debugfs_rbbm_init(rdev)) { |
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| 65 | DRM_ERROR("Failed to register debugfs file for RBBM !\n"); |
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| 66 | } |
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| 67 | if (rv515_debugfs_pipes_info_init(rdev)) { |
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| 68 | DRM_ERROR("Failed to register debugfs file for pipes !\n"); |
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| 69 | } |
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| 70 | if (rv515_debugfs_ga_info_init(rdev)) { |
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| 71 | DRM_ERROR("Failed to register debugfs file for pipes !\n"); |
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| 72 | } |
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| 73 | |||
| 74 | rv515_gpu_init(rdev); |
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| 75 | rv370_pcie_gart_disable(rdev); |
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| 76 | |||
| 77 | /* Setup GPU memory space */ |
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| 78 | rdev->mc.vram_location = 0xFFFFFFFFUL; |
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| 79 | rdev->mc.gtt_location = 0xFFFFFFFFUL; |
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| 80 | if (rdev->flags & RADEON_IS_AGP) { |
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| 81 | r = radeon_agp_init(rdev); |
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| 82 | if (r) { |
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| 83 | printk(KERN_WARNING "[drm] Disabling AGP\n"); |
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| 84 | rdev->flags &= ~RADEON_IS_AGP; |
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| 85 | rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; |
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| 86 | } else { |
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| 87 | rdev->mc.gtt_location = rdev->mc.agp_base; |
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| 88 | } |
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| 89 | } |
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| 90 | r = radeon_mc_setup(rdev); |
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| 91 | if (r) { |
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| 92 | return r; |
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| 93 | } |
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| 94 | |||
| 95 | /* Program GPU memory space */ |
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| 96 | rs600_mc_disable_clients(rdev); |
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| 97 | if (rv515_mc_wait_for_idle(rdev)) { |
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| 98 | printk(KERN_WARNING "Failed to wait MC idle while " |
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| 99 | "programming pipes. Bad things might happen.\n"); |
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| 100 | } |
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| 101 | /* Write VRAM size in case we are limiting it */ |
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| 102 | WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.vram_size); |
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| 103 | tmp = REG_SET(RV515_MC_FB_START, rdev->mc.vram_location >> 16); |
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| 104 | WREG32(0x134, tmp); |
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| 105 | tmp = rdev->mc.vram_location + rdev->mc.vram_size - 1; |
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| 106 | tmp = REG_SET(RV515_MC_FB_TOP, tmp >> 16); |
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| 107 | tmp |= REG_SET(RV515_MC_FB_START, rdev->mc.vram_location >> 16); |
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| 108 | WREG32_MC(RV515_MC_FB_LOCATION, tmp); |
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| 109 | WREG32(RS690_HDP_FB_LOCATION, rdev->mc.vram_location >> 16); |
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| 110 | WREG32(0x310, rdev->mc.vram_location); |
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| 111 | if (rdev->flags & RADEON_IS_AGP) { |
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| 112 | tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1; |
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| 113 | tmp = REG_SET(RV515_MC_AGP_TOP, tmp >> 16); |
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| 114 | tmp |= REG_SET(RV515_MC_AGP_START, rdev->mc.gtt_location >> 16); |
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| 115 | WREG32_MC(RV515_MC_AGP_LOCATION, tmp); |
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| 116 | WREG32_MC(RV515_MC_AGP_BASE, rdev->mc.agp_base); |
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| 117 | WREG32_MC(RV515_MC_AGP_BASE_2, 0); |
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| 118 | } else { |
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| 119 | WREG32_MC(RV515_MC_AGP_LOCATION, 0x0FFFFFFF); |
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| 120 | WREG32_MC(RV515_MC_AGP_BASE, 0); |
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| 121 | WREG32_MC(RV515_MC_AGP_BASE_2, 0); |
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| 122 | } |
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| 123 | return 0; |
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| 124 | } |
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| 125 | |||
| 126 | void rv515_mc_fini(struct radeon_device *rdev) |
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| 127 | { |
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| 128 | rv370_pcie_gart_disable(rdev); |
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| 129 | radeon_gart_table_vram_free(rdev); |
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| 130 | radeon_gart_fini(rdev); |
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| 131 | } |
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| 132 | |||
| 1119 | serge | 133 | #endif |
| 1117 | serge | 134 | |
| 135 | /* |
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| 136 | * Global GPU functions |
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| 137 | */ |
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| 138 | void rv515_ring_start(struct radeon_device *rdev) |
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| 139 | { |
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| 140 | unsigned gb_tile_config; |
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| 141 | int r; |
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| 142 | |||
| 1119 | serge | 143 | dbgprintf("%s\n\r",__FUNCTION__); |
| 1117 | serge | 144 | /* Sub pixel 1/12 so we can have 4K rendering according to doc */ |
| 145 | gb_tile_config = R300_ENABLE_TILING | R300_TILE_SIZE_16; |
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| 146 | switch (rdev->num_gb_pipes) { |
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| 147 | case 2: |
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| 148 | gb_tile_config |= R300_PIPE_COUNT_R300; |
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| 149 | break; |
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| 150 | case 3: |
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| 151 | gb_tile_config |= R300_PIPE_COUNT_R420_3P; |
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| 152 | break; |
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| 153 | case 4: |
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| 154 | gb_tile_config |= R300_PIPE_COUNT_R420; |
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| 155 | break; |
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| 156 | case 1: |
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| 157 | default: |
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| 158 | gb_tile_config |= R300_PIPE_COUNT_RV350; |
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| 159 | break; |
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| 160 | } |
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| 161 | |||
| 162 | r = radeon_ring_lock(rdev, 64); |
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| 163 | if (r) { |
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| 164 | return; |
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| 165 | } |
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| 166 | radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0)); |
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| 167 | radeon_ring_write(rdev, |
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| 168 | RADEON_ISYNC_ANY2D_IDLE3D | |
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| 169 | RADEON_ISYNC_ANY3D_IDLE2D | |
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| 170 | RADEON_ISYNC_WAIT_IDLEGUI | |
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| 171 | RADEON_ISYNC_CPSCRATCH_IDLEGUI); |
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| 172 | radeon_ring_write(rdev, PACKET0(R300_GB_TILE_CONFIG, 0)); |
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| 173 | radeon_ring_write(rdev, gb_tile_config); |
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| 174 | radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0)); |
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| 175 | radeon_ring_write(rdev, |
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| 176 | RADEON_WAIT_2D_IDLECLEAN | |
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| 177 | RADEON_WAIT_3D_IDLECLEAN); |
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| 178 | radeon_ring_write(rdev, PACKET0(0x170C, 0)); |
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| 179 | radeon_ring_write(rdev, 1 << 31); |
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| 180 | radeon_ring_write(rdev, PACKET0(R300_GB_SELECT, 0)); |
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| 181 | radeon_ring_write(rdev, 0); |
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| 182 | radeon_ring_write(rdev, PACKET0(R300_GB_ENABLE, 0)); |
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| 183 | radeon_ring_write(rdev, 0); |
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| 184 | radeon_ring_write(rdev, PACKET0(0x42C8, 0)); |
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| 185 | radeon_ring_write(rdev, (1 << rdev->num_gb_pipes) - 1); |
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| 186 | radeon_ring_write(rdev, PACKET0(R500_VAP_INDEX_OFFSET, 0)); |
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| 187 | radeon_ring_write(rdev, 0); |
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| 188 | radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); |
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| 189 | radeon_ring_write(rdev, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE); |
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| 190 | radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0)); |
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| 191 | radeon_ring_write(rdev, R300_ZC_FLUSH | R300_ZC_FREE); |
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| 192 | radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0)); |
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| 193 | radeon_ring_write(rdev, |
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| 194 | RADEON_WAIT_2D_IDLECLEAN | |
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| 195 | RADEON_WAIT_3D_IDLECLEAN); |
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| 196 | radeon_ring_write(rdev, PACKET0(R300_GB_AA_CONFIG, 0)); |
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| 197 | radeon_ring_write(rdev, 0); |
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| 198 | radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); |
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| 199 | radeon_ring_write(rdev, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE); |
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| 200 | radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0)); |
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| 201 | radeon_ring_write(rdev, R300_ZC_FLUSH | R300_ZC_FREE); |
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| 202 | radeon_ring_write(rdev, PACKET0(R300_GB_MSPOS0, 0)); |
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| 203 | radeon_ring_write(rdev, |
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| 204 | ((6 << R300_MS_X0_SHIFT) | |
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| 205 | (6 << R300_MS_Y0_SHIFT) | |
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| 206 | (6 << R300_MS_X1_SHIFT) | |
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| 207 | (6 << R300_MS_Y1_SHIFT) | |
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| 208 | (6 << R300_MS_X2_SHIFT) | |
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| 209 | (6 << R300_MS_Y2_SHIFT) | |
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| 210 | (6 << R300_MSBD0_Y_SHIFT) | |
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| 211 | (6 << R300_MSBD0_X_SHIFT))); |
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| 212 | radeon_ring_write(rdev, PACKET0(R300_GB_MSPOS1, 0)); |
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| 213 | radeon_ring_write(rdev, |
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| 214 | ((6 << R300_MS_X3_SHIFT) | |
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| 215 | (6 << R300_MS_Y3_SHIFT) | |
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| 216 | (6 << R300_MS_X4_SHIFT) | |
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| 217 | (6 << R300_MS_Y4_SHIFT) | |
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| 218 | (6 << R300_MS_X5_SHIFT) | |
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| 219 | (6 << R300_MS_Y5_SHIFT) | |
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| 220 | (6 << R300_MSBD1_SHIFT))); |
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| 221 | radeon_ring_write(rdev, PACKET0(R300_GA_ENHANCE, 0)); |
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| 222 | radeon_ring_write(rdev, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL); |
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| 223 | radeon_ring_write(rdev, PACKET0(R300_GA_POLY_MODE, 0)); |
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| 224 | radeon_ring_write(rdev, |
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| 225 | R300_FRONT_PTYPE_TRIANGE | R300_BACK_PTYPE_TRIANGE); |
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| 226 | radeon_ring_write(rdev, PACKET0(R300_GA_ROUND_MODE, 0)); |
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| 227 | radeon_ring_write(rdev, |
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| 228 | R300_GEOMETRY_ROUND_NEAREST | |
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| 229 | R300_COLOR_ROUND_NEAREST); |
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| 230 | radeon_ring_write(rdev, PACKET0(0x20C8, 0)); |
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| 231 | radeon_ring_write(rdev, 0); |
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| 232 | radeon_ring_unlock_commit(rdev); |
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| 1119 | serge | 233 | |
| 234 | dbgprintf("done %s\n\r",__FUNCTION__); |
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| 235 | |||
| 1117 | serge | 236 | } |
| 237 | |||
| 238 | void rv515_errata(struct radeon_device *rdev) |
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| 239 | { |
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| 240 | rdev->pll_errata = 0; |
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| 241 | } |
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| 242 | |||
| 243 | int rv515_mc_wait_for_idle(struct radeon_device *rdev) |
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| 244 | { |
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| 245 | unsigned i; |
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| 246 | uint32_t tmp; |
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| 247 | |||
| 248 | for (i = 0; i < rdev->usec_timeout; i++) { |
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| 249 | /* read MC_STATUS */ |
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| 250 | tmp = RREG32_MC(RV515_MC_STATUS); |
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| 251 | if (tmp & RV515_MC_STATUS_IDLE) { |
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| 252 | return 0; |
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| 253 | } |
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| 254 | DRM_UDELAY(1); |
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| 255 | } |
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| 256 | return -1; |
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| 257 | } |
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| 258 | |||
| 1119 | serge | 259 | #if 0 |
| 1117 | serge | 260 | void rv515_gpu_init(struct radeon_device *rdev) |
| 261 | { |
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| 262 | unsigned pipe_select_current, gb_pipe_select, tmp; |
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| 263 | |||
| 264 | r100_hdp_reset(rdev); |
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| 265 | r100_rb2d_reset(rdev); |
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| 266 | |||
| 267 | if (r100_gui_wait_for_idle(rdev)) { |
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| 268 | printk(KERN_WARNING "Failed to wait GUI idle while " |
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| 269 | "reseting GPU. Bad things might happen.\n"); |
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| 270 | } |
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| 271 | |||
| 272 | rs600_disable_vga(rdev); |
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| 273 | |||
| 274 | r420_pipes_init(rdev); |
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| 275 | gb_pipe_select = RREG32(0x402C); |
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| 276 | tmp = RREG32(0x170C); |
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| 277 | pipe_select_current = (tmp >> 2) & 3; |
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| 278 | tmp = (1 << pipe_select_current) | |
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| 279 | (((gb_pipe_select >> 8) & 0xF) << 4); |
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| 280 | WREG32_PLL(0x000D, tmp); |
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| 281 | if (r100_gui_wait_for_idle(rdev)) { |
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| 282 | printk(KERN_WARNING "Failed to wait GUI idle while " |
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| 283 | "reseting GPU. Bad things might happen.\n"); |
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| 284 | } |
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| 285 | if (rv515_mc_wait_for_idle(rdev)) { |
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| 286 | printk(KERN_WARNING "Failed to wait MC idle while " |
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| 287 | "programming pipes. Bad things might happen.\n"); |
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| 288 | } |
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| 289 | } |
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| 290 | |||
| 291 | #endif |
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| 292 | |||
| 293 | int rv515_ga_reset(struct radeon_device *rdev) |
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| 294 | { |
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| 295 | uint32_t tmp; |
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| 296 | bool reinit_cp; |
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| 297 | int i; |
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| 298 | |||
| 299 | dbgprintf("%s\n\r",__FUNCTION__); |
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| 300 | |||
| 301 | reinit_cp = rdev->cp.ready; |
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| 302 | rdev->cp.ready = false; |
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| 303 | for (i = 0; i < rdev->usec_timeout; i++) { |
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| 304 | WREG32(RADEON_CP_CSQ_MODE, 0); |
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| 305 | WREG32(RADEON_CP_CSQ_CNTL, 0); |
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| 306 | WREG32(RADEON_RBBM_SOFT_RESET, 0x32005); |
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| 307 | (void)RREG32(RADEON_RBBM_SOFT_RESET); |
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| 308 | udelay(200); |
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| 309 | WREG32(RADEON_RBBM_SOFT_RESET, 0); |
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| 310 | /* Wait to prevent race in RBBM_STATUS */ |
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| 311 | mdelay(1); |
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| 312 | tmp = RREG32(RADEON_RBBM_STATUS); |
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| 313 | if (tmp & ((1 << 20) | (1 << 26))) { |
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| 314 | DRM_ERROR("VAP & CP still busy (RBBM_STATUS=0x%08X)\n", tmp); |
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| 315 | /* GA still busy soft reset it */ |
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| 316 | WREG32(0x429C, 0x200); |
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| 317 | WREG32(R300_VAP_PVS_STATE_FLUSH_REG, 0); |
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| 318 | WREG32(0x43E0, 0); |
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| 319 | WREG32(0x43E4, 0); |
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| 320 | WREG32(0x24AC, 0); |
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| 321 | } |
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| 322 | /* Wait to prevent race in RBBM_STATUS */ |
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| 323 | mdelay(1); |
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| 324 | tmp = RREG32(RADEON_RBBM_STATUS); |
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| 325 | if (!(tmp & ((1 << 20) | (1 << 26)))) { |
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| 326 | break; |
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| 327 | } |
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| 328 | } |
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| 329 | for (i = 0; i < rdev->usec_timeout; i++) { |
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| 330 | tmp = RREG32(RADEON_RBBM_STATUS); |
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| 331 | if (!(tmp & ((1 << 20) | (1 << 26)))) { |
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| 332 | DRM_INFO("GA reset succeed (RBBM_STATUS=0x%08X)\n", |
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| 333 | tmp); |
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| 334 | DRM_INFO("GA_IDLE=0x%08X\n", RREG32(0x425C)); |
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| 335 | DRM_INFO("RB3D_RESET_STATUS=0x%08X\n", RREG32(0x46f0)); |
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| 336 | DRM_INFO("ISYNC_CNTL=0x%08X\n", RREG32(0x1724)); |
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| 337 | if (reinit_cp) { |
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| 338 | return r100_cp_init(rdev, rdev->cp.ring_size); |
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| 339 | } |
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| 340 | return 0; |
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| 341 | } |
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| 342 | DRM_UDELAY(1); |
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| 343 | } |
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| 344 | tmp = RREG32(RADEON_RBBM_STATUS); |
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| 345 | DRM_ERROR("Failed to reset GA ! (RBBM_STATUS=0x%08X)\n", tmp); |
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| 346 | return -1; |
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| 347 | } |
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| 348 | |||
| 349 | int rv515_gpu_reset(struct radeon_device *rdev) |
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| 350 | { |
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| 351 | uint32_t status; |
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| 352 | |||
| 353 | dbgprintf("%s\n\r",__FUNCTION__); |
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| 354 | |||
| 355 | /* reset order likely matter */ |
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| 356 | status = RREG32(RADEON_RBBM_STATUS); |
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| 357 | /* reset HDP */ |
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| 358 | r100_hdp_reset(rdev); |
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| 359 | /* reset rb2d */ |
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| 360 | if (status & ((1 << 17) | (1 << 18) | (1 << 27))) { |
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| 361 | r100_rb2d_reset(rdev); |
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| 362 | } |
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| 363 | /* reset GA */ |
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| 364 | if (status & ((1 << 20) | (1 << 26))) { |
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| 365 | rv515_ga_reset(rdev); |
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| 366 | } |
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| 367 | /* reset CP */ |
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| 368 | status = RREG32(RADEON_RBBM_STATUS); |
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| 369 | if (status & (1 << 16)) { |
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| 370 | r100_cp_reset(rdev); |
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| 371 | } |
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| 372 | /* Check if GPU is idle */ |
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| 373 | status = RREG32(RADEON_RBBM_STATUS); |
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| 374 | if (status & (1 << 31)) { |
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| 375 | DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status); |
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| 376 | return -1; |
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| 377 | } |
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| 378 | DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status); |
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| 379 | return 0; |
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| 380 | } |
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| 381 | |||
| 382 | |||
| 383 | /* |
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| 384 | * VRAM info |
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| 385 | */ |
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| 386 | static void rv515_vram_get_type(struct radeon_device *rdev) |
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| 387 | { |
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| 388 | uint32_t tmp; |
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| 389 | |||
| 390 | rdev->mc.vram_width = 128; |
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| 391 | rdev->mc.vram_is_ddr = true; |
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| 392 | tmp = RREG32_MC(RV515_MC_CNTL); |
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| 393 | tmp &= RV515_MEM_NUM_CHANNELS_MASK; |
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| 394 | switch (tmp) { |
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| 395 | case 0: |
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| 396 | rdev->mc.vram_width = 64; |
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| 397 | break; |
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| 398 | case 1: |
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| 399 | rdev->mc.vram_width = 128; |
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| 400 | break; |
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| 401 | default: |
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| 402 | rdev->mc.vram_width = 128; |
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| 403 | break; |
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| 404 | } |
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| 405 | } |
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| 406 | |||
| 407 | void rv515_vram_info(struct radeon_device *rdev) |
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| 408 | { |
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| 409 | rv515_vram_get_type(rdev); |
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| 410 | rdev->mc.vram_size = RREG32(RADEON_CONFIG_MEMSIZE); |
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| 411 | |||
| 412 | rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); |
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| 413 | rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); |
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| 414 | } |
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| 415 | |||
| 416 | |||
| 417 | /* |
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| 418 | * Indirect registers accessor |
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| 419 | */ |
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| 420 | uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg) |
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| 421 | { |
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| 422 | uint32_t r; |
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| 423 | |||
| 424 | WREG32(R520_MC_IND_INDEX, 0x7f0000 | (reg & 0xffff)); |
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| 425 | r = RREG32(R520_MC_IND_DATA); |
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| 426 | WREG32(R520_MC_IND_INDEX, 0); |
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| 427 | return r; |
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| 428 | } |
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| 429 | |||
| 430 | void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
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| 431 | { |
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| 432 | WREG32(R520_MC_IND_INDEX, 0xff0000 | ((reg) & 0xffff)); |
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| 433 | WREG32(R520_MC_IND_DATA, (v)); |
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| 434 | WREG32(R520_MC_IND_INDEX, 0); |
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| 435 | } |
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| 436 | |||
| 437 | uint32_t rv515_pcie_rreg(struct radeon_device *rdev, uint32_t reg) |
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| 438 | { |
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| 439 | uint32_t r; |
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| 440 | |||
| 441 | WREG32(RADEON_PCIE_INDEX, ((reg) & 0x7ff)); |
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| 442 | (void)RREG32(RADEON_PCIE_INDEX); |
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| 443 | r = RREG32(RADEON_PCIE_DATA); |
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| 444 | return r; |
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| 445 | } |
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| 446 | |||
| 447 | void rv515_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
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| 448 | { |
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| 449 | WREG32(RADEON_PCIE_INDEX, ((reg) & 0x7ff)); |
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| 450 | (void)RREG32(RADEON_PCIE_INDEX); |
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| 451 | WREG32(RADEON_PCIE_DATA, (v)); |
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| 452 | (void)RREG32(RADEON_PCIE_DATA); |
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| 453 | } |
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| 454 | |||
| 455 | #if 0 |
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| 456 | /* |
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| 457 | * Debugfs info |
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| 458 | */ |
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| 459 | #if defined(CONFIG_DEBUG_FS) |
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| 460 | static int rv515_debugfs_pipes_info(struct seq_file *m, void *data) |
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| 461 | { |
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| 462 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
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| 463 | struct drm_device *dev = node->minor->dev; |
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| 464 | struct radeon_device *rdev = dev->dev_private; |
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| 465 | uint32_t tmp; |
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| 466 | |||
| 467 | tmp = RREG32(R400_GB_PIPE_SELECT); |
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| 468 | seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp); |
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| 469 | tmp = RREG32(R500_SU_REG_DEST); |
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| 470 | seq_printf(m, "SU_REG_DEST 0x%08x\n", tmp); |
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| 471 | tmp = RREG32(R300_GB_TILE_CONFIG); |
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| 472 | seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp); |
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| 473 | tmp = RREG32(R300_DST_PIPE_CONFIG); |
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| 474 | seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp); |
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| 475 | return 0; |
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| 476 | } |
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| 477 | |||
| 478 | static int rv515_debugfs_ga_info(struct seq_file *m, void *data) |
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| 479 | { |
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| 480 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
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| 481 | struct drm_device *dev = node->minor->dev; |
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| 482 | struct radeon_device *rdev = dev->dev_private; |
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| 483 | uint32_t tmp; |
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| 484 | |||
| 485 | tmp = RREG32(0x2140); |
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| 486 | seq_printf(m, "VAP_CNTL_STATUS 0x%08x\n", tmp); |
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| 487 | radeon_gpu_reset(rdev); |
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| 488 | tmp = RREG32(0x425C); |
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| 489 | seq_printf(m, "GA_IDLE 0x%08x\n", tmp); |
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| 490 | return 0; |
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| 491 | } |
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| 492 | |||
| 493 | static struct drm_info_list rv515_pipes_info_list[] = { |
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| 494 | {"rv515_pipes_info", rv515_debugfs_pipes_info, 0, NULL}, |
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| 495 | }; |
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| 496 | |||
| 497 | static struct drm_info_list rv515_ga_info_list[] = { |
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| 498 | {"rv515_ga_info", rv515_debugfs_ga_info, 0, NULL}, |
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| 499 | }; |
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| 500 | #endif |
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| 501 | |||
| 502 | int rv515_debugfs_pipes_info_init(struct radeon_device *rdev) |
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| 503 | { |
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| 504 | #if defined(CONFIG_DEBUG_FS) |
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| 505 | return radeon_debugfs_add_files(rdev, rv515_pipes_info_list, 1); |
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| 506 | #else |
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| 507 | return 0; |
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| 508 | #endif |
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| 509 | } |
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| 510 | |||
| 511 | int rv515_debugfs_ga_info_init(struct radeon_device *rdev) |
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| 512 | { |
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| 513 | #if defined(CONFIG_DEBUG_FS) |
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| 514 | return radeon_debugfs_add_files(rdev, rv515_ga_info_list, 1); |
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| 515 | #else |
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| 516 | return 0; |
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| 517 | #endif |
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| 518 | } |
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| 519 | |||
| 520 | #endif |
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| 521 | |||
| 522 | /* |
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| 523 | * Asic initialization |
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| 524 | */ |
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| 525 | static const unsigned r500_reg_safe_bm[159] = { |
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| 526 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
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| 527 | 0xFFFFFFBF, 0xFFFFFFFF, 0xFFFFFFBF, 0xFFFFFFFF, |
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| 528 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
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| 529 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
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| 530 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
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| 531 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
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| 532 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
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| 533 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
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| 534 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
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| 535 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
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| 536 | 0x17FF1FFF, 0xFFFFFFFC, 0xFFFFFFFF, 0xFF30FFBF, |
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| 537 | 0xFFFFFFF8, 0xC3E6FFFF, 0xFFFFF6DF, 0xFFFFFFFF, |
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| 538 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
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| 539 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
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| 540 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFF03F, |
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| 541 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
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| 542 | 0xFFFFFFFF, 0xFFFFEFCE, 0xF00EBFFF, 0x007C0000, |
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| 543 | 0xF0000038, 0xFF000009, 0xFFFFFFFF, 0xFFFFFFFF, |
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| 544 | 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0xFFFFFFFF, |
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| 545 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
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| 546 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
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| 547 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
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| 548 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
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| 549 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
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| 550 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
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| 551 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
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| 552 | 0xFFFFF7FF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
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| 553 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
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| 554 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
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| 555 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
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| 556 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
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| 557 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
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| 558 | 0x1FFFFC78, 0xFFFFE000, 0xFFFFFFFE, 0xFFFFFFFF, |
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| 559 | 0x38CF8F50, 0xFFF88082, 0xFF0000FC, 0xFAE009FF, |
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| 560 | 0x0000FFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, |
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| 561 | 0xFFFF8CFC, 0xFFFFC1FF, 0xFFFFFFFF, 0xFFFFFFFF, |
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| 562 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
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| 563 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFF80FFFF, |
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| 564 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
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| 565 | 0x0003FC01, 0x3FFFFCF8, 0xFE800B19, |
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| 566 | }; |
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| 567 | |||
| 568 | |||
| 569 | |||
| 570 | int rv515_init(struct radeon_device *rdev) |
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| 571 | { |
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| 572 | dbgprintf("%s\n\r",__FUNCTION__); |
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| 573 | |||
| 574 | rdev->config.r300.reg_safe_bm = r500_reg_safe_bm; |
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| 575 | rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r500_reg_safe_bm); |
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| 576 | return 0; |
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| 577 | } |