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5078 | serge | 1 | /* |
2 | * Copyright 2011 Advanced Micro Devices, Inc. |
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3 | * |
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4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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5 | * copy of this software and associated documentation files (the "Software"), |
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6 | * to deal in the Software without restriction, including without limitation |
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7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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8 | * and/or sell copies of the Software, and to permit persons to whom the |
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9 | * Software is furnished to do so, subject to the following conditions: |
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10 | * |
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11 | * The above copyright notice and this permission notice shall be included in |
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12 | * all copies or substantial portions of the Software. |
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13 | * |
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14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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20 | * OTHER DEALINGS IN THE SOFTWARE. |
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21 | * |
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22 | */ |
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23 | #ifndef __RS780_DPM_H__ |
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24 | #define __RS780_DPM_H__ |
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25 | |||
26 | enum rs780_vddc_level { |
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27 | RS780_VDDC_LEVEL_UNKNOWN = 0, |
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28 | RS780_VDDC_LEVEL_LOW = 1, |
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29 | RS780_VDDC_LEVEL_HIGH = 2, |
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30 | }; |
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31 | |||
32 | struct igp_power_info { |
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33 | /* flags */ |
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34 | bool invert_pwm_required; |
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35 | bool pwm_voltage_control; |
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36 | bool voltage_control; |
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37 | bool gfx_clock_gating; |
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38 | /* stored values */ |
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39 | u32 system_config; |
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40 | u32 bootup_uma_clk; |
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41 | u16 max_voltage; |
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42 | u16 min_voltage; |
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43 | u16 boot_voltage; |
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44 | u16 inter_voltage_low; |
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45 | u16 inter_voltage_high; |
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46 | u16 num_of_cycles_in_period; |
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47 | /* variable */ |
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48 | int crtc_id; |
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49 | int refresh_rate; |
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50 | }; |
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51 | |||
52 | struct igp_ps { |
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53 | enum rs780_vddc_level min_voltage; |
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54 | enum rs780_vddc_level max_voltage; |
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55 | u32 sclk_low; |
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56 | u32 sclk_high; |
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57 | u32 flags; |
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58 | }; |
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59 | |||
60 | #define RS780_CGFTV_DFLT 0x0303000f |
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61 | #define RS780_FBDIVTIMERVAL_DFLT 0x2710 |
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62 | |||
63 | #define RS780_FVTHROTUTC0_DFLT 0x04010040 |
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64 | #define RS780_FVTHROTUTC1_DFLT 0x04010040 |
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65 | #define RS780_FVTHROTUTC2_DFLT 0x04010040 |
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66 | #define RS780_FVTHROTUTC3_DFLT 0x04010040 |
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67 | #define RS780_FVTHROTUTC4_DFLT 0x04010040 |
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68 | |||
69 | #define RS780_FVTHROTDTC0_DFLT 0x04010040 |
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70 | #define RS780_FVTHROTDTC1_DFLT 0x04010040 |
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71 | #define RS780_FVTHROTDTC2_DFLT 0x04010040 |
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72 | #define RS780_FVTHROTDTC3_DFLT 0x04010040 |
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73 | #define RS780_FVTHROTDTC4_DFLT 0x04010040 |
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74 | |||
75 | #define RS780_FVTHROTFBUSREG0_DFLT 0x00001001 |
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76 | #define RS780_FVTHROTFBUSREG1_DFLT 0x00002002 |
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77 | #define RS780_FVTHROTFBDSREG0_DFLT 0x00004001 |
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78 | #define RS780_FVTHROTFBDSREG1_DFLT 0x00020010 |
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79 | |||
80 | #define RS780_FVTHROTPWMUSREG0_DFLT 0x00002001 |
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81 | #define RS780_FVTHROTPWMUSREG1_DFLT 0x00004003 |
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82 | #define RS780_FVTHROTPWMDSREG0_DFLT 0x00002001 |
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83 | #define RS780_FVTHROTPWMDSREG1_DFLT 0x00004003 |
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84 | |||
85 | #define RS780_FVTHROTPWMFBDIVRANGEREG0_DFLT 0x37 |
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86 | #define RS780_FVTHROTPWMFBDIVRANGEREG1_DFLT 0x4b |
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87 | #define RS780_FVTHROTPWMFBDIVRANGEREG2_DFLT 0x8b |
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88 | |||
89 | #define RS780D_FVTHROTPWMFBDIVRANGEREG0_DFLT 0x8b |
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90 | #define RS780D_FVTHROTPWMFBDIVRANGEREG1_DFLT 0x8c |
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91 | #define RS780D_FVTHROTPWMFBDIVRANGEREG2_DFLT 0xb5 |
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92 | |||
93 | #define RS880D_FVTHROTPWMFBDIVRANGEREG0_DFLT 0x8d |
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94 | #define RS880D_FVTHROTPWMFBDIVRANGEREG1_DFLT 0x8e |
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95 | #define RS880D_FVTHROTPWMFBDIVRANGEREG2_DFLT 0xBa |
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96 | |||
97 | #define RS780_FVTHROTPWMRANGE0_GPIO_DFLT 0x1a |
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98 | #define RS780_FVTHROTPWMRANGE1_GPIO_DFLT 0x1a |
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99 | #define RS780_FVTHROTPWMRANGE2_GPIO_DFLT 0x0 |
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100 | #define RS780_FVTHROTPWMRANGE3_GPIO_DFLT 0x0 |
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101 | |||
102 | #define RS780_SLOWCLKFEEDBACKDIV_DFLT 110 |
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103 | |||
104 | #define RS780_CGCLKGATING_DFLT 0x0000E204 |
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105 | |||
106 | #define RS780_DEFAULT_VCLK_FREQ 53300 /* 10 khz */ |
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107 | #define RS780_DEFAULT_DCLK_FREQ 40000 /* 10 khz */ |
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108 | |||
109 | #endif |