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1179 | serge | 1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
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3 | * Copyright 2008 Red Hat Inc. |
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4 | * Copyright 2009 Jerome Glisse. |
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5 | * |
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6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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7 | * copy of this software and associated documentation files (the "Software"), |
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8 | * to deal in the Software without restriction, including without limitation |
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9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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10 | * and/or sell copies of the Software, and to permit persons to whom the |
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11 | * Software is furnished to do so, subject to the following conditions: |
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12 | * |
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13 | * The above copyright notice and this permission notice shall be included in |
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14 | * all copies or substantial portions of the Software. |
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15 | * |
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16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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22 | * OTHER DEALINGS IN THE SOFTWARE. |
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23 | * |
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24 | * Authors: Dave Airlie |
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25 | * Alex Deucher |
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26 | * Jerome Glisse |
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27 | */ |
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28 | #ifndef RS690R_H |
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29 | #define RS690R_H |
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30 | |||
31 | /* RS690/RS740 registers */ |
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32 | #define MC_INDEX 0x0078 |
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33 | # define MC_INDEX_MASK 0x1FF |
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34 | # define MC_INDEX_WR_EN (1 << 9) |
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35 | # define MC_INDEX_WR_ACK 0x7F |
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36 | #define MC_DATA 0x007C |
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37 | #define HDP_FB_LOCATION 0x0134 |
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38 | #define DC_LB_MEMORY_SPLIT 0x6520 |
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39 | #define DC_LB_MEMORY_SPLIT_MASK 0x00000003 |
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40 | #define DC_LB_MEMORY_SPLIT_SHIFT 0 |
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41 | #define DC_LB_MEMORY_SPLIT_D1HALF_D2HALF 0 |
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42 | #define DC_LB_MEMORY_SPLIT_D1_3Q_D2_1Q 1 |
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43 | #define DC_LB_MEMORY_SPLIT_D1_ONLY 2 |
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44 | #define DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q 3 |
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45 | #define DC_LB_MEMORY_SPLIT_SHIFT_MODE (1 << 2) |
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46 | #define DC_LB_DISP1_END_ADR_SHIFT 4 |
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47 | #define DC_LB_DISP1_END_ADR_MASK 0x00007FF0 |
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48 | #define D1MODE_PRIORITY_A_CNT 0x6548 |
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49 | #define MODE_PRIORITY_MARK_MASK 0x00007FFF |
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50 | #define MODE_PRIORITY_OFF (1 << 16) |
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51 | #define MODE_PRIORITY_ALWAYS_ON (1 << 20) |
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52 | #define MODE_PRIORITY_FORCE_MASK (1 << 24) |
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53 | #define D1MODE_PRIORITY_B_CNT 0x654C |
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54 | #define LB_MAX_REQ_OUTSTANDING 0x6D58 |
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55 | #define LB_D1_MAX_REQ_OUTSTANDING_MASK 0x0000000F |
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56 | #define LB_D1_MAX_REQ_OUTSTANDING_SHIFT 0 |
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57 | #define LB_D2_MAX_REQ_OUTSTANDING_MASK 0x000F0000 |
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58 | #define LB_D2_MAX_REQ_OUTSTANDING_SHIFT 16 |
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59 | #define DCP_CONTROL 0x6C9C |
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60 | #define D2MODE_PRIORITY_A_CNT 0x6D48 |
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61 | #define D2MODE_PRIORITY_B_CNT 0x6D4C |
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62 | |||
63 | /* MC indirect registers */ |
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64 | #define MC_STATUS_IDLE (1 << 0) |
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65 | #define MC_MISC_CNTL 0x18 |
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66 | #define DISABLE_GTW (1 << 1) |
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67 | #define GART_INDEX_REG_EN (1 << 12) |
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68 | #define BLOCK_GFX_D3_EN (1 << 14) |
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69 | #define GART_FEATURE_ID 0x2B |
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70 | #define HANG_EN (1 << 11) |
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71 | #define TLB_ENABLE (1 << 18) |
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72 | #define P2P_ENABLE (1 << 19) |
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73 | #define GTW_LAC_EN (1 << 25) |
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74 | #define LEVEL2_GART (0 << 30) |
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75 | #define LEVEL1_GART (1 << 30) |
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76 | #define PDC_EN (1 << 31) |
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77 | #define GART_BASE 0x2C |
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78 | #define GART_CACHE_CNTRL 0x2E |
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79 | # define GART_CACHE_INVALIDATE (1 << 0) |
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80 | #define MC_STATUS 0x90 |
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81 | #define MCCFG_FB_LOCATION 0x100 |
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82 | #define MC_FB_START_MASK 0x0000FFFF |
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83 | #define MC_FB_START_SHIFT 0 |
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84 | #define MC_FB_TOP_MASK 0xFFFF0000 |
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85 | #define MC_FB_TOP_SHIFT 16 |
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86 | #define MCCFG_AGP_LOCATION 0x101 |
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87 | #define MC_AGP_START_MASK 0x0000FFFF |
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88 | #define MC_AGP_START_SHIFT 0 |
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89 | #define MC_AGP_TOP_MASK 0xFFFF0000 |
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90 | #define MC_AGP_TOP_SHIFT 16 |
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91 | #define MCCFG_AGP_BASE 0x102 |
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92 | #define MCCFG_AGP_BASE_2 0x103 |
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93 | #define MC_INIT_MISC_LAT_TIMER 0x104 |
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94 | #define MC_DISP0R_INIT_LAT_SHIFT 8 |
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95 | #define MC_DISP0R_INIT_LAT_MASK 0x00000F00 |
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96 | #define MC_DISP1R_INIT_LAT_SHIFT 12 |
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97 | #define MC_DISP1R_INIT_LAT_MASK 0x0000F000 |
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98 | |||
99 | #endif><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><> |