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1128 | serge | 1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
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3 | * Copyright 2008 Red Hat Inc. |
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4 | * Copyright 2009 Jerome Glisse. |
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5 | * |
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6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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7 | * copy of this software and associated documentation files (the "Software"), |
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8 | * to deal in the Software without restriction, including without limitation |
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9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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10 | * and/or sell copies of the Software, and to permit persons to whom the |
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11 | * Software is furnished to do so, subject to the following conditions: |
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12 | * |
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13 | * The above copyright notice and this permission notice shall be included in |
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14 | * all copies or substantial portions of the Software. |
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15 | * |
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16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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22 | * OTHER DEALINGS IN THE SOFTWARE. |
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23 | * |
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24 | * Authors: Dave Airlie |
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25 | * Alex Deucher |
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26 | * Jerome Glisse |
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27 | */ |
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28 | #include "drmP.h" |
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29 | #include "radeon_reg.h" |
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30 | #include "radeon.h" |
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1179 | serge | 31 | #include "rs690r.h" |
32 | #include "atom.h" |
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33 | #include "atom-bits.h" |
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1128 | serge | 34 | |
35 | /* rs690,rs740 depends on : */ |
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36 | void r100_hdp_reset(struct radeon_device *rdev); |
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37 | int r300_mc_wait_for_idle(struct radeon_device *rdev); |
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38 | void r420_pipes_init(struct radeon_device *rdev); |
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39 | void rs400_gart_disable(struct radeon_device *rdev); |
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40 | int rs400_gart_enable(struct radeon_device *rdev); |
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41 | void rs400_gart_adjust_size(struct radeon_device *rdev); |
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42 | void rs600_mc_disable_clients(struct radeon_device *rdev); |
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43 | void rs600_disable_vga(struct radeon_device *rdev); |
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44 | |||
45 | /* This files gather functions specifics to : |
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46 | * rs690,rs740 |
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47 | * |
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48 | * Some of these functions might be used by newer ASICs. |
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49 | */ |
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50 | void rs690_gpu_init(struct radeon_device *rdev); |
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51 | int rs690_mc_wait_for_idle(struct radeon_device *rdev); |
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52 | |||
53 | |||
54 | /* |
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55 | * MC functions. |
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56 | */ |
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57 | int rs690_mc_init(struct radeon_device *rdev) |
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58 | { |
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59 | uint32_t tmp; |
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60 | int r; |
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61 | |||
1129 | serge | 62 | if (r100_debugfs_rbbm_init(rdev)) { |
63 | DRM_ERROR("Failed to register debugfs file for RBBM !\n"); |
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64 | } |
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1128 | serge | 65 | |
66 | rs690_gpu_init(rdev); |
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67 | rs400_gart_disable(rdev); |
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68 | |||
69 | /* Setup GPU memory space */ |
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1179 | serge | 70 | rdev->mc.gtt_location = rdev->mc.mc_vram_size; |
1128 | serge | 71 | rdev->mc.gtt_location += (rdev->mc.gtt_size - 1); |
72 | rdev->mc.gtt_location &= ~(rdev->mc.gtt_size - 1); |
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73 | rdev->mc.vram_location = 0xFFFFFFFFUL; |
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74 | r = radeon_mc_setup(rdev); |
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75 | if (r) { |
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76 | return r; |
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77 | } |
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78 | |||
79 | /* Program GPU memory space */ |
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80 | rs600_mc_disable_clients(rdev); |
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81 | if (rs690_mc_wait_for_idle(rdev)) { |
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82 | printk(KERN_WARNING "Failed to wait MC idle while " |
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83 | "programming pipes. Bad things might happen.\n"); |
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84 | } |
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1179 | serge | 85 | tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1; |
1128 | serge | 86 | tmp = REG_SET(RS690_MC_FB_TOP, tmp >> 16); |
87 | tmp |= REG_SET(RS690_MC_FB_START, rdev->mc.vram_location >> 16); |
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88 | WREG32_MC(RS690_MCCFG_FB_LOCATION, tmp); |
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89 | /* FIXME: Does this reg exist on RS480,RS740 ? */ |
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90 | WREG32(0x310, rdev->mc.vram_location); |
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91 | WREG32(RS690_HDP_FB_LOCATION, rdev->mc.vram_location >> 16); |
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92 | return 0; |
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93 | } |
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94 | |||
95 | void rs690_mc_fini(struct radeon_device *rdev) |
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96 | { |
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97 | } |
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98 | |||
99 | |||
100 | /* |
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101 | * Global GPU functions |
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102 | */ |
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103 | int rs690_mc_wait_for_idle(struct radeon_device *rdev) |
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104 | { |
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105 | unsigned i; |
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106 | uint32_t tmp; |
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107 | |||
108 | for (i = 0; i < rdev->usec_timeout; i++) { |
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109 | /* read MC_STATUS */ |
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110 | tmp = RREG32_MC(RS690_MC_STATUS); |
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111 | if (tmp & RS690_MC_STATUS_IDLE) { |
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112 | return 0; |
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113 | } |
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114 | DRM_UDELAY(1); |
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115 | } |
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116 | return -1; |
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117 | } |
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118 | |||
119 | void rs690_errata(struct radeon_device *rdev) |
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120 | { |
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121 | rdev->pll_errata = 0; |
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122 | } |
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123 | |||
124 | void rs690_gpu_init(struct radeon_device *rdev) |
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125 | { |
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126 | /* FIXME: HDP same place on rs690 ? */ |
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127 | r100_hdp_reset(rdev); |
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128 | rs600_disable_vga(rdev); |
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129 | /* FIXME: is this correct ? */ |
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130 | r420_pipes_init(rdev); |
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131 | if (rs690_mc_wait_for_idle(rdev)) { |
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132 | printk(KERN_WARNING "Failed to wait MC idle while " |
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133 | "programming pipes. Bad things might happen.\n"); |
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134 | } |
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135 | } |
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136 | |||
137 | |||
138 | /* |
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139 | * VRAM info. |
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140 | */ |
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1179 | serge | 141 | void rs690_pm_info(struct radeon_device *rdev) |
142 | { |
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143 | int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo); |
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144 | struct _ATOM_INTEGRATED_SYSTEM_INFO *info; |
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145 | struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 *info_v2; |
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146 | void *ptr; |
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147 | uint16_t data_offset; |
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148 | uint8_t frev, crev; |
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149 | fixed20_12 tmp; |
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150 | |||
151 | atom_parse_data_header(rdev->mode_info.atom_context, index, NULL, |
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152 | &frev, &crev, &data_offset); |
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153 | ptr = rdev->mode_info.atom_context->bios + data_offset; |
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154 | info = (struct _ATOM_INTEGRATED_SYSTEM_INFO *)ptr; |
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155 | info_v2 = (struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 *)ptr; |
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156 | /* Get various system informations from bios */ |
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157 | switch (crev) { |
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158 | case 1: |
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159 | tmp.full = rfixed_const(100); |
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160 | rdev->pm.igp_sideport_mclk.full = rfixed_const(info->ulBootUpMemoryClock); |
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161 | rdev->pm.igp_sideport_mclk.full = rfixed_div(rdev->pm.igp_sideport_mclk, tmp); |
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162 | rdev->pm.igp_system_mclk.full = rfixed_const(le16_to_cpu(info->usK8MemoryClock)); |
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163 | rdev->pm.igp_ht_link_clk.full = rfixed_const(le16_to_cpu(info->usFSBClock)); |
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164 | rdev->pm.igp_ht_link_width.full = rfixed_const(info->ucHTLinkWidth); |
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165 | break; |
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166 | case 2: |
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167 | tmp.full = rfixed_const(100); |
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168 | rdev->pm.igp_sideport_mclk.full = rfixed_const(info_v2->ulBootUpSidePortClock); |
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169 | rdev->pm.igp_sideport_mclk.full = rfixed_div(rdev->pm.igp_sideport_mclk, tmp); |
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170 | rdev->pm.igp_system_mclk.full = rfixed_const(info_v2->ulBootUpUMAClock); |
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171 | rdev->pm.igp_system_mclk.full = rfixed_div(rdev->pm.igp_system_mclk, tmp); |
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172 | rdev->pm.igp_ht_link_clk.full = rfixed_const(info_v2->ulHTLinkFreq); |
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173 | rdev->pm.igp_ht_link_clk.full = rfixed_div(rdev->pm.igp_ht_link_clk, tmp); |
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174 | rdev->pm.igp_ht_link_width.full = rfixed_const(le16_to_cpu(info_v2->usMinHTLinkWidth)); |
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175 | break; |
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176 | default: |
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177 | tmp.full = rfixed_const(100); |
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178 | /* We assume the slower possible clock ie worst case */ |
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179 | /* DDR 333Mhz */ |
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180 | rdev->pm.igp_sideport_mclk.full = rfixed_const(333); |
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181 | /* FIXME: system clock ? */ |
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182 | rdev->pm.igp_system_mclk.full = rfixed_const(100); |
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183 | rdev->pm.igp_system_mclk.full = rfixed_div(rdev->pm.igp_system_mclk, tmp); |
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184 | rdev->pm.igp_ht_link_clk.full = rfixed_const(200); |
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185 | rdev->pm.igp_ht_link_width.full = rfixed_const(8); |
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186 | DRM_ERROR("No integrated system info for your GPU, using safe default\n"); |
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187 | break; |
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188 | } |
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189 | /* Compute various bandwidth */ |
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190 | /* k8_bandwidth = (memory_clk / 2) * 2 * 8 * 0.5 = memory_clk * 4 */ |
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191 | tmp.full = rfixed_const(4); |
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192 | rdev->pm.k8_bandwidth.full = rfixed_mul(rdev->pm.igp_system_mclk, tmp); |
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193 | /* ht_bandwidth = ht_clk * 2 * ht_width / 8 * 0.8 |
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194 | * = ht_clk * ht_width / 5 |
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195 | */ |
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196 | tmp.full = rfixed_const(5); |
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197 | rdev->pm.ht_bandwidth.full = rfixed_mul(rdev->pm.igp_ht_link_clk, |
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198 | rdev->pm.igp_ht_link_width); |
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199 | rdev->pm.ht_bandwidth.full = rfixed_div(rdev->pm.ht_bandwidth, tmp); |
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200 | if (tmp.full < rdev->pm.max_bandwidth.full) { |
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201 | /* HT link is a limiting factor */ |
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202 | rdev->pm.max_bandwidth.full = tmp.full; |
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203 | } |
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204 | /* sideport_bandwidth = (sideport_clk / 2) * 2 * 2 * 0.7 |
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205 | * = (sideport_clk * 14) / 10 |
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206 | */ |
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207 | tmp.full = rfixed_const(14); |
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208 | rdev->pm.sideport_bandwidth.full = rfixed_mul(rdev->pm.igp_sideport_mclk, tmp); |
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209 | tmp.full = rfixed_const(10); |
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210 | rdev->pm.sideport_bandwidth.full = rfixed_div(rdev->pm.sideport_bandwidth, tmp); |
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211 | } |
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212 | |||
1128 | serge | 213 | void rs690_vram_info(struct radeon_device *rdev) |
214 | { |
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215 | uint32_t tmp; |
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1179 | serge | 216 | fixed20_12 a; |
1128 | serge | 217 | |
218 | rs400_gart_adjust_size(rdev); |
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219 | /* DDR for all card after R300 & IGP */ |
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220 | rdev->mc.vram_is_ddr = true; |
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221 | /* FIXME: is this correct for RS690/RS740 ? */ |
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222 | tmp = RREG32(RADEON_MEM_CNTL); |
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223 | if (tmp & R300_MEM_NUM_CHANNELS_MASK) { |
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224 | rdev->mc.vram_width = 128; |
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225 | } else { |
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226 | rdev->mc.vram_width = 64; |
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227 | } |
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1179 | serge | 228 | rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); |
229 | rdev->mc.mc_vram_size = rdev->mc.real_vram_size; |
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1128 | serge | 230 | |
231 | rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); |
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232 | rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); |
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1179 | serge | 233 | rs690_pm_info(rdev); |
234 | /* FIXME: we should enforce default clock in case GPU is not in |
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235 | * default setup |
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236 | */ |
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237 | a.full = rfixed_const(100); |
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238 | rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk); |
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239 | rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a); |
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240 | a.full = rfixed_const(16); |
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241 | /* core_bandwidth = sclk(Mhz) * 16 */ |
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242 | rdev->pm.core_bandwidth.full = rfixed_div(rdev->pm.sclk, a); |
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1128 | serge | 243 | } |
244 | |||
1179 | serge | 245 | void rs690_line_buffer_adjust(struct radeon_device *rdev, |
246 | struct drm_display_mode *mode1, |
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247 | struct drm_display_mode *mode2) |
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248 | { |
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249 | u32 tmp; |
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1128 | serge | 250 | |
1179 | serge | 251 | /* |
252 | * Line Buffer Setup |
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253 | * There is a single line buffer shared by both display controllers. |
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254 | * DC_LB_MEMORY_SPLIT controls how that line buffer is shared between |
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255 | * the display controllers. The paritioning can either be done |
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256 | * manually or via one of four preset allocations specified in bits 1:0: |
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257 | * 0 - line buffer is divided in half and shared between crtc |
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258 | * 1 - D1 gets 3/4 of the line buffer, D2 gets 1/4 |
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259 | * 2 - D1 gets the whole buffer |
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260 | * 3 - D1 gets 1/4 of the line buffer, D2 gets 3/4 |
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261 | * Setting bit 2 of DC_LB_MEMORY_SPLIT controls switches to manual |
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262 | * allocation mode. In manual allocation mode, D1 always starts at 0, |
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263 | * D1 end/2 is specified in bits 14:4; D2 allocation follows D1. |
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264 | */ |
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265 | tmp = RREG32(DC_LB_MEMORY_SPLIT) & ~DC_LB_MEMORY_SPLIT_MASK; |
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266 | tmp &= ~DC_LB_MEMORY_SPLIT_SHIFT_MODE; |
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267 | /* auto */ |
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268 | if (mode1 && mode2) { |
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269 | if (mode1->hdisplay > mode2->hdisplay) { |
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270 | if (mode1->hdisplay > 2560) |
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271 | tmp |= DC_LB_MEMORY_SPLIT_D1_3Q_D2_1Q; |
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272 | else |
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273 | tmp |= DC_LB_MEMORY_SPLIT_D1HALF_D2HALF; |
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274 | } else if (mode2->hdisplay > mode1->hdisplay) { |
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275 | if (mode2->hdisplay > 2560) |
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276 | tmp |= DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q; |
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277 | else |
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278 | tmp |= DC_LB_MEMORY_SPLIT_D1HALF_D2HALF; |
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279 | } else |
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280 | tmp |= AVIVO_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF; |
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281 | } else if (mode1) { |
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282 | tmp |= DC_LB_MEMORY_SPLIT_D1_ONLY; |
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283 | } else if (mode2) { |
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284 | tmp |= DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q; |
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285 | } |
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286 | WREG32(DC_LB_MEMORY_SPLIT, tmp); |
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287 | } |
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288 | |||
289 | struct rs690_watermark { |
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290 | u32 lb_request_fifo_depth; |
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291 | fixed20_12 num_line_pair; |
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292 | fixed20_12 estimated_width; |
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293 | fixed20_12 worst_case_latency; |
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294 | fixed20_12 consumption_rate; |
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295 | fixed20_12 active_time; |
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296 | fixed20_12 dbpp; |
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297 | fixed20_12 priority_mark_max; |
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298 | fixed20_12 priority_mark; |
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299 | fixed20_12 sclk; |
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300 | }; |
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301 | |||
302 | void rs690_crtc_bandwidth_compute(struct radeon_device *rdev, |
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303 | struct radeon_crtc *crtc, |
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304 | struct rs690_watermark *wm) |
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305 | { |
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306 | struct drm_display_mode *mode = &crtc->base.mode; |
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307 | fixed20_12 a, b, c; |
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308 | fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width; |
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309 | fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency; |
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310 | /* FIXME: detect IGP with sideport memory, i don't think there is any |
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311 | * such product available |
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312 | */ |
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313 | bool sideport = false; |
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314 | |||
315 | if (!crtc->base.enabled) { |
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316 | /* FIXME: wouldn't it better to set priority mark to maximum */ |
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317 | wm->lb_request_fifo_depth = 4; |
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318 | return; |
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319 | } |
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320 | |||
321 | if (crtc->vsc.full > rfixed_const(2)) |
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322 | wm->num_line_pair.full = rfixed_const(2); |
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323 | else |
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324 | wm->num_line_pair.full = rfixed_const(1); |
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325 | |||
326 | b.full = rfixed_const(mode->crtc_hdisplay); |
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327 | c.full = rfixed_const(256); |
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328 | a.full = rfixed_mul(wm->num_line_pair, b); |
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329 | request_fifo_depth.full = rfixed_div(a, c); |
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330 | if (a.full < rfixed_const(4)) { |
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331 | wm->lb_request_fifo_depth = 4; |
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332 | } else { |
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333 | wm->lb_request_fifo_depth = rfixed_trunc(request_fifo_depth); |
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334 | } |
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335 | |||
336 | /* Determine consumption rate |
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337 | * pclk = pixel clock period(ns) = 1000 / (mode.clock / 1000) |
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338 | * vtaps = number of vertical taps, |
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339 | * vsc = vertical scaling ratio, defined as source/destination |
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340 | * hsc = horizontal scaling ration, defined as source/destination |
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341 | */ |
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342 | a.full = rfixed_const(mode->clock); |
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343 | b.full = rfixed_const(1000); |
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344 | a.full = rfixed_div(a, b); |
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345 | pclk.full = rfixed_div(b, a); |
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346 | if (crtc->rmx_type != RMX_OFF) { |
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347 | b.full = rfixed_const(2); |
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348 | if (crtc->vsc.full > b.full) |
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349 | b.full = crtc->vsc.full; |
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350 | b.full = rfixed_mul(b, crtc->hsc); |
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351 | c.full = rfixed_const(2); |
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352 | b.full = rfixed_div(b, c); |
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353 | consumption_time.full = rfixed_div(pclk, b); |
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354 | } else { |
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355 | consumption_time.full = pclk.full; |
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356 | } |
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357 | a.full = rfixed_const(1); |
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358 | wm->consumption_rate.full = rfixed_div(a, consumption_time); |
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359 | |||
360 | |||
361 | /* Determine line time |
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362 | * LineTime = total time for one line of displayhtotal |
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363 | * LineTime = total number of horizontal pixels |
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364 | * pclk = pixel clock period(ns) |
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365 | */ |
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366 | a.full = rfixed_const(crtc->base.mode.crtc_htotal); |
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367 | line_time.full = rfixed_mul(a, pclk); |
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368 | |||
369 | /* Determine active time |
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370 | * ActiveTime = time of active region of display within one line, |
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371 | * hactive = total number of horizontal active pixels |
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372 | * htotal = total number of horizontal pixels |
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373 | */ |
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374 | a.full = rfixed_const(crtc->base.mode.crtc_htotal); |
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375 | b.full = rfixed_const(crtc->base.mode.crtc_hdisplay); |
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376 | wm->active_time.full = rfixed_mul(line_time, b); |
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377 | wm->active_time.full = rfixed_div(wm->active_time, a); |
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378 | |||
379 | /* Maximun bandwidth is the minimun bandwidth of all component */ |
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380 | rdev->pm.max_bandwidth = rdev->pm.core_bandwidth; |
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381 | if (sideport) { |
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382 | if (rdev->pm.max_bandwidth.full > rdev->pm.sideport_bandwidth.full && |
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383 | rdev->pm.sideport_bandwidth.full) |
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384 | rdev->pm.max_bandwidth = rdev->pm.sideport_bandwidth; |
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385 | read_delay_latency.full = rfixed_const(370 * 800 * 1000); |
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386 | read_delay_latency.full = rfixed_div(read_delay_latency, |
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387 | rdev->pm.igp_sideport_mclk); |
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388 | } else { |
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389 | if (rdev->pm.max_bandwidth.full > rdev->pm.k8_bandwidth.full && |
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390 | rdev->pm.k8_bandwidth.full) |
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391 | rdev->pm.max_bandwidth = rdev->pm.k8_bandwidth; |
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392 | if (rdev->pm.max_bandwidth.full > rdev->pm.ht_bandwidth.full && |
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393 | rdev->pm.ht_bandwidth.full) |
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394 | rdev->pm.max_bandwidth = rdev->pm.ht_bandwidth; |
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395 | read_delay_latency.full = rfixed_const(5000); |
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396 | } |
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397 | |||
398 | /* sclk = system clocks(ns) = 1000 / max_bandwidth / 16 */ |
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399 | a.full = rfixed_const(16); |
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400 | rdev->pm.sclk.full = rfixed_mul(rdev->pm.max_bandwidth, a); |
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401 | a.full = rfixed_const(1000); |
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402 | rdev->pm.sclk.full = rfixed_div(a, rdev->pm.sclk); |
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403 | /* Determine chunk time |
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404 | * ChunkTime = the time it takes the DCP to send one chunk of data |
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405 | * to the LB which consists of pipeline delay and inter chunk gap |
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406 | * sclk = system clock(ns) |
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407 | */ |
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408 | a.full = rfixed_const(256 * 13); |
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409 | chunk_time.full = rfixed_mul(rdev->pm.sclk, a); |
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410 | a.full = rfixed_const(10); |
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411 | chunk_time.full = rfixed_div(chunk_time, a); |
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412 | |||
413 | /* Determine the worst case latency |
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414 | * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines) |
||
415 | * WorstCaseLatency = worst case time from urgent to when the MC starts |
||
416 | * to return data |
||
417 | * READ_DELAY_IDLE_MAX = constant of 1us |
||
418 | * ChunkTime = time it takes the DCP to send one chunk of data to the LB |
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419 | * which consists of pipeline delay and inter chunk gap |
||
420 | */ |
||
421 | if (rfixed_trunc(wm->num_line_pair) > 1) { |
||
422 | a.full = rfixed_const(3); |
||
423 | wm->worst_case_latency.full = rfixed_mul(a, chunk_time); |
||
424 | wm->worst_case_latency.full += read_delay_latency.full; |
||
425 | } else { |
||
426 | a.full = rfixed_const(2); |
||
427 | wm->worst_case_latency.full = rfixed_mul(a, chunk_time); |
||
428 | wm->worst_case_latency.full += read_delay_latency.full; |
||
429 | } |
||
430 | |||
431 | /* Determine the tolerable latency |
||
432 | * TolerableLatency = Any given request has only 1 line time |
||
433 | * for the data to be returned |
||
434 | * LBRequestFifoDepth = Number of chunk requests the LB can |
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435 | * put into the request FIFO for a display |
||
436 | * LineTime = total time for one line of display |
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437 | * ChunkTime = the time it takes the DCP to send one chunk |
||
438 | * of data to the LB which consists of |
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439 | * pipeline delay and inter chunk gap |
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440 | */ |
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441 | if ((2+wm->lb_request_fifo_depth) >= rfixed_trunc(request_fifo_depth)) { |
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442 | tolerable_latency.full = line_time.full; |
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443 | } else { |
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444 | tolerable_latency.full = rfixed_const(wm->lb_request_fifo_depth - 2); |
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445 | tolerable_latency.full = request_fifo_depth.full - tolerable_latency.full; |
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446 | tolerable_latency.full = rfixed_mul(tolerable_latency, chunk_time); |
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447 | tolerable_latency.full = line_time.full - tolerable_latency.full; |
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448 | } |
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449 | /* We assume worst case 32bits (4 bytes) */ |
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450 | wm->dbpp.full = rfixed_const(4 * 8); |
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451 | |||
452 | /* Determine the maximum priority mark |
||
453 | * width = viewport width in pixels |
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454 | */ |
||
455 | a.full = rfixed_const(16); |
||
456 | wm->priority_mark_max.full = rfixed_const(crtc->base.mode.crtc_hdisplay); |
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457 | wm->priority_mark_max.full = rfixed_div(wm->priority_mark_max, a); |
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458 | |||
459 | /* Determine estimated width */ |
||
460 | estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full; |
||
461 | estimated_width.full = rfixed_div(estimated_width, consumption_time); |
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462 | if (rfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) { |
||
463 | wm->priority_mark.full = rfixed_const(10); |
||
464 | } else { |
||
465 | a.full = rfixed_const(16); |
||
466 | wm->priority_mark.full = rfixed_div(estimated_width, a); |
||
467 | wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full; |
||
468 | } |
||
469 | } |
||
470 | |||
471 | void rs690_bandwidth_update(struct radeon_device *rdev) |
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472 | { |
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473 | struct drm_display_mode *mode0 = NULL; |
||
474 | struct drm_display_mode *mode1 = NULL; |
||
475 | struct rs690_watermark wm0; |
||
476 | struct rs690_watermark wm1; |
||
477 | u32 tmp; |
||
478 | fixed20_12 priority_mark02, priority_mark12, fill_rate; |
||
479 | fixed20_12 a, b; |
||
480 | |||
481 | if (rdev->mode_info.crtcs[0]->base.enabled) |
||
482 | mode0 = &rdev->mode_info.crtcs[0]->base.mode; |
||
483 | if (rdev->mode_info.crtcs[1]->base.enabled) |
||
484 | mode1 = &rdev->mode_info.crtcs[1]->base.mode; |
||
485 | /* |
||
486 | * Set display0/1 priority up in the memory controller for |
||
487 | * modes if the user specifies HIGH for displaypriority |
||
488 | * option. |
||
489 | */ |
||
490 | if (rdev->disp_priority == 2) { |
||
491 | tmp = RREG32_MC(MC_INIT_MISC_LAT_TIMER); |
||
492 | tmp &= ~MC_DISP1R_INIT_LAT_MASK; |
||
493 | tmp &= ~MC_DISP0R_INIT_LAT_MASK; |
||
494 | if (mode1) |
||
495 | tmp |= (1 << MC_DISP1R_INIT_LAT_SHIFT); |
||
496 | if (mode0) |
||
497 | tmp |= (1 << MC_DISP0R_INIT_LAT_SHIFT); |
||
498 | WREG32_MC(MC_INIT_MISC_LAT_TIMER, tmp); |
||
499 | } |
||
500 | rs690_line_buffer_adjust(rdev, mode0, mode1); |
||
501 | |||
502 | if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) |
||
503 | WREG32(DCP_CONTROL, 0); |
||
504 | if ((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880)) |
||
505 | WREG32(DCP_CONTROL, 2); |
||
506 | |||
507 | rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0); |
||
508 | rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1); |
||
509 | |||
510 | tmp = (wm0.lb_request_fifo_depth - 1); |
||
511 | tmp |= (wm1.lb_request_fifo_depth - 1) << 16; |
||
512 | WREG32(LB_MAX_REQ_OUTSTANDING, tmp); |
||
513 | |||
514 | if (mode0 && mode1) { |
||
515 | if (rfixed_trunc(wm0.dbpp) > 64) |
||
516 | a.full = rfixed_mul(wm0.dbpp, wm0.num_line_pair); |
||
517 | else |
||
518 | a.full = wm0.num_line_pair.full; |
||
519 | if (rfixed_trunc(wm1.dbpp) > 64) |
||
520 | b.full = rfixed_mul(wm1.dbpp, wm1.num_line_pair); |
||
521 | else |
||
522 | b.full = wm1.num_line_pair.full; |
||
523 | a.full += b.full; |
||
524 | fill_rate.full = rfixed_div(wm0.sclk, a); |
||
525 | if (wm0.consumption_rate.full > fill_rate.full) { |
||
526 | b.full = wm0.consumption_rate.full - fill_rate.full; |
||
527 | b.full = rfixed_mul(b, wm0.active_time); |
||
528 | a.full = rfixed_mul(wm0.worst_case_latency, |
||
529 | wm0.consumption_rate); |
||
530 | a.full = a.full + b.full; |
||
531 | b.full = rfixed_const(16 * 1000); |
||
532 | priority_mark02.full = rfixed_div(a, b); |
||
533 | } else { |
||
534 | a.full = rfixed_mul(wm0.worst_case_latency, |
||
535 | wm0.consumption_rate); |
||
536 | b.full = rfixed_const(16 * 1000); |
||
537 | priority_mark02.full = rfixed_div(a, b); |
||
538 | } |
||
539 | if (wm1.consumption_rate.full > fill_rate.full) { |
||
540 | b.full = wm1.consumption_rate.full - fill_rate.full; |
||
541 | b.full = rfixed_mul(b, wm1.active_time); |
||
542 | a.full = rfixed_mul(wm1.worst_case_latency, |
||
543 | wm1.consumption_rate); |
||
544 | a.full = a.full + b.full; |
||
545 | b.full = rfixed_const(16 * 1000); |
||
546 | priority_mark12.full = rfixed_div(a, b); |
||
547 | } else { |
||
548 | a.full = rfixed_mul(wm1.worst_case_latency, |
||
549 | wm1.consumption_rate); |
||
550 | b.full = rfixed_const(16 * 1000); |
||
551 | priority_mark12.full = rfixed_div(a, b); |
||
552 | } |
||
553 | if (wm0.priority_mark.full > priority_mark02.full) |
||
554 | priority_mark02.full = wm0.priority_mark.full; |
||
555 | if (rfixed_trunc(priority_mark02) < 0) |
||
556 | priority_mark02.full = 0; |
||
557 | if (wm0.priority_mark_max.full > priority_mark02.full) |
||
558 | priority_mark02.full = wm0.priority_mark_max.full; |
||
559 | if (wm1.priority_mark.full > priority_mark12.full) |
||
560 | priority_mark12.full = wm1.priority_mark.full; |
||
561 | if (rfixed_trunc(priority_mark12) < 0) |
||
562 | priority_mark12.full = 0; |
||
563 | if (wm1.priority_mark_max.full > priority_mark12.full) |
||
564 | priority_mark12.full = wm1.priority_mark_max.full; |
||
565 | WREG32(D1MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark02)); |
||
566 | WREG32(D1MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark02)); |
||
567 | WREG32(D2MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark12)); |
||
568 | WREG32(D2MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark12)); |
||
569 | } else if (mode0) { |
||
570 | if (rfixed_trunc(wm0.dbpp) > 64) |
||
571 | a.full = rfixed_mul(wm0.dbpp, wm0.num_line_pair); |
||
572 | else |
||
573 | a.full = wm0.num_line_pair.full; |
||
574 | fill_rate.full = rfixed_div(wm0.sclk, a); |
||
575 | if (wm0.consumption_rate.full > fill_rate.full) { |
||
576 | b.full = wm0.consumption_rate.full - fill_rate.full; |
||
577 | b.full = rfixed_mul(b, wm0.active_time); |
||
578 | a.full = rfixed_mul(wm0.worst_case_latency, |
||
579 | wm0.consumption_rate); |
||
580 | a.full = a.full + b.full; |
||
581 | b.full = rfixed_const(16 * 1000); |
||
582 | priority_mark02.full = rfixed_div(a, b); |
||
583 | } else { |
||
584 | a.full = rfixed_mul(wm0.worst_case_latency, |
||
585 | wm0.consumption_rate); |
||
586 | b.full = rfixed_const(16 * 1000); |
||
587 | priority_mark02.full = rfixed_div(a, b); |
||
588 | } |
||
589 | if (wm0.priority_mark.full > priority_mark02.full) |
||
590 | priority_mark02.full = wm0.priority_mark.full; |
||
591 | if (rfixed_trunc(priority_mark02) < 0) |
||
592 | priority_mark02.full = 0; |
||
593 | if (wm0.priority_mark_max.full > priority_mark02.full) |
||
594 | priority_mark02.full = wm0.priority_mark_max.full; |
||
595 | WREG32(D1MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark02)); |
||
596 | WREG32(D1MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark02)); |
||
597 | WREG32(D2MODE_PRIORITY_A_CNT, MODE_PRIORITY_OFF); |
||
598 | WREG32(D2MODE_PRIORITY_B_CNT, MODE_PRIORITY_OFF); |
||
599 | } else { |
||
600 | if (rfixed_trunc(wm1.dbpp) > 64) |
||
601 | a.full = rfixed_mul(wm1.dbpp, wm1.num_line_pair); |
||
602 | else |
||
603 | a.full = wm1.num_line_pair.full; |
||
604 | fill_rate.full = rfixed_div(wm1.sclk, a); |
||
605 | if (wm1.consumption_rate.full > fill_rate.full) { |
||
606 | b.full = wm1.consumption_rate.full - fill_rate.full; |
||
607 | b.full = rfixed_mul(b, wm1.active_time); |
||
608 | a.full = rfixed_mul(wm1.worst_case_latency, |
||
609 | wm1.consumption_rate); |
||
610 | a.full = a.full + b.full; |
||
611 | b.full = rfixed_const(16 * 1000); |
||
612 | priority_mark12.full = rfixed_div(a, b); |
||
613 | } else { |
||
614 | a.full = rfixed_mul(wm1.worst_case_latency, |
||
615 | wm1.consumption_rate); |
||
616 | b.full = rfixed_const(16 * 1000); |
||
617 | priority_mark12.full = rfixed_div(a, b); |
||
618 | } |
||
619 | if (wm1.priority_mark.full > priority_mark12.full) |
||
620 | priority_mark12.full = wm1.priority_mark.full; |
||
621 | if (rfixed_trunc(priority_mark12) < 0) |
||
622 | priority_mark12.full = 0; |
||
623 | if (wm1.priority_mark_max.full > priority_mark12.full) |
||
624 | priority_mark12.full = wm1.priority_mark_max.full; |
||
625 | WREG32(D1MODE_PRIORITY_A_CNT, MODE_PRIORITY_OFF); |
||
626 | WREG32(D1MODE_PRIORITY_B_CNT, MODE_PRIORITY_OFF); |
||
627 | WREG32(D2MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark12)); |
||
628 | WREG32(D2MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark12)); |
||
629 | } |
||
630 | } |
||
631 | |||
1128 | serge | 632 | /* |
633 | * Indirect registers accessor |
||
634 | */ |
||
635 | uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg) |
||
636 | { |
||
637 | uint32_t r; |
||
638 | |||
639 | WREG32(RS690_MC_INDEX, (reg & RS690_MC_INDEX_MASK)); |
||
640 | r = RREG32(RS690_MC_DATA); |
||
641 | WREG32(RS690_MC_INDEX, RS690_MC_INDEX_MASK); |
||
642 | return r; |
||
643 | } |
||
644 | |||
645 | void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
||
646 | { |
||
647 | WREG32(RS690_MC_INDEX, |
||
648 | RS690_MC_INDEX_WR_EN | ((reg) & RS690_MC_INDEX_MASK)); |
||
649 | WREG32(RS690_MC_DATA, v); |
||
650 | WREG32(RS690_MC_INDEX, RS690_MC_INDEX_WR_ACK); |
||
651 | }>>>>><>><>><>>>> |