WebSVN – Kolibri OS – Blame – /drivers/video/drm/radeon/rs600.c

Rev	Author	Line No.	Line
1128	serge	1	/*
		2	* Copyright 2008 Advanced Micro Devices, Inc.
		3	* Copyright 2008 Red Hat Inc.
		4	* Copyright 2009 Jerome Glisse.
		5	*
		6	* Permission is hereby granted, free of charge, to any person obtaining a
		7	* copy of this software and associated documentation files (the "Software"),
		8	* to deal in the Software without restriction, including without limitation
		9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		10	* and/or sell copies of the Software, and to permit persons to whom the
		11	* Software is furnished to do so, subject to the following conditions:
		12	*
		13	* The above copyright notice and this permission notice shall be included in
		14	* all copies or substantial portions of the Software.
		15	*
		16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
		20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
		21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
		22	* OTHER DEALINGS IN THE SOFTWARE.
		23	*
		24	* Authors: Dave Airlie
		25	* Alex Deucher
		26	* Jerome Glisse
		27	*/
1221	serge	28	/* RS600 / Radeon X1250/X1270 integrated GPU
		29	*
		30	* This file gather function specific to RS600 which is the IGP of
		31	* the X1250/X1270 family supporting intel CPU (while RS690/RS740
		32	* is the X1250/X1270 supporting AMD CPU). The display engine are
		33	* the avivo one, bios is an atombios, 3D block are the one of the
		34	* R4XX family. The GART is different from the RS400 one and is very
		35	* close to the one of the R600 family (R600 likely being an evolution
		36	* of the RS600 GART block).
		37	*/
2997	Serge	38	#include
1128	serge	39	#include "radeon.h"
1963	serge	40	#include "radeon_asic.h"
6104	serge	41	#include "radeon_audio.h"
1221	serge	42	#include "atom.h"
		43	#include "rs600d.h"
1128	serge	44
1179	serge	45	#include "rs600_reg_safe.h"
		46
2997	Serge	47	static void rs600_gpu_init(struct radeon_device *rdev);
1128	serge	48	int rs600_mc_wait_for_idle(struct radeon_device *rdev);
		49
2997	Serge	50	static const u32 crtc_offsets[2] =
		51	{
		52	0,
		53	AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL
		54	};
		55
3764	Serge	56	static bool avivo_is_in_vblank(struct radeon_device *rdev, int crtc)
		57	{
		58	if (RREG32(AVIVO_D1CRTC_STATUS + crtc_offsets[crtc]) & AVIVO_D1CRTC_V_BLANK)
		59	return true;
		60	else
		61	return false;
		62	}
		63
		64	static bool avivo_is_counter_moving(struct radeon_device *rdev, int crtc)
		65	{
		66	u32 pos1, pos2;
		67
		68	pos1 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]);
		69	pos2 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]);
		70
		71	if (pos1 != pos2)
		72	return true;
		73	else
		74	return false;
		75	}
		76
		77	/**
		78	* avivo_wait_for_vblank - vblank wait asic callback.
		79	*
		80	* @rdev: radeon_device pointer
		81	* @crtc: crtc to wait for vblank on
		82	*
		83	* Wait for vblank on the requested crtc (r5xx-r7xx).
		84	*/
2997	Serge	85	void avivo_wait_for_vblank(struct radeon_device *rdev, int crtc)
		86	{
3764	Serge	87	unsigned i = 0;
2997	Serge	88
		89	if (crtc >= rdev->num_crtc)
		90	return;
		91
3764	Serge	92	if (!(RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[crtc]) & AVIVO_CRTC_EN))
		93	return;
		94
		95	/* depending on when we hit vblank, we may be close to active; if so,
		96	* wait for another frame.
		97	*/
		98	while (avivo_is_in_vblank(rdev, crtc)) {
		99	if (i++ % 100 == 0) {
		100	if (!avivo_is_counter_moving(rdev, crtc))
2997	Serge	101	break;
		102	}
3764	Serge	103	}
		104
		105	while (!avivo_is_in_vblank(rdev, crtc)) {
		106	if (i++ % 100 == 0) {
		107	if (!avivo_is_counter_moving(rdev, crtc))
		108	break;
		109	}
5078	serge	110	}
		111	}
		112	void avivo_program_fmt(struct drm_encoder *encoder)
		113	{
		114	struct drm_device *dev = encoder->dev;
		115	struct radeon_device *rdev = dev->dev_private;
		116	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		117	struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
		118	int bpc = 0;
		119	u32 tmp = 0;
		120	enum radeon_connector_dither dither = RADEON_FMT_DITHER_DISABLE;
		121
		122	if (connector) {
		123	struct radeon_connector *radeon_connector = to_radeon_connector(connector);
		124	bpc = radeon_get_monitor_bpc(connector);
		125	dither = radeon_connector->dither;
		126	}
		127
		128	/* LVDS FMT is set up by atom */
		129	if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
		130	return;
		131
		132	if (bpc == 0)
		133	return;
		134
		135	switch (bpc) {
		136	case 6:
		137	if (dither == RADEON_FMT_DITHER_ENABLE)
		138	/* XXX sort out optimal dither settings */
		139	tmp \|= AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
		140	else
		141	tmp \|= AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_EN;
		142	break;
		143	case 8:
		144	if (dither == RADEON_FMT_DITHER_ENABLE)
		145	/* XXX sort out optimal dither settings */
		146	tmp \|= (AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN \|
		147	AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH);
		148	else
		149	tmp \|= (AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_EN \|
		150	AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH);
		151	break;
		152	case 10:
		153	default:
		154	/* not needed */
		155	break;
		156	}
		157
		158	switch (radeon_encoder->encoder_id) {
		159	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
		160	WREG32(AVIVO_TMDSA_BIT_DEPTH_CONTROL, tmp);
		161	break;
		162	case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
		163	WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, tmp);
		164	break;
		165	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
		166	WREG32(AVIVO_DVOA_BIT_DEPTH_CONTROL, tmp);
		167	break;
		168	case ENCODER_OBJECT_ID_INTERNAL_DDI:
		169	WREG32(AVIVO_DDIA_BIT_DEPTH_CONTROL, tmp);
		170	break;
		171	default:
		172	break;
		173	}
		174	}
		175
		176	void rs600_pm_misc(struct radeon_device *rdev)
		177	{
		178	int requested_index = rdev->pm.requested_power_state_index;
		179	struct radeon_power_state *ps = &rdev->pm.power_state[requested_index];
		180	struct radeon_voltage *voltage = &ps->clock_info[0].voltage;
		181	u32 tmp, dyn_pwrmgt_sclk_length, dyn_sclk_vol_cntl;
		182	u32 hdp_dyn_cntl, /mc_host_dyn_cntl,/ dyn_backbias_cntl;
		183
		184	if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) {
		185	if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
		186	tmp = RREG32(voltage->gpio.reg);
		187	if (voltage->active_high)
		188	tmp \|= voltage->gpio.mask;
		189	else
		190	tmp &= ~(voltage->gpio.mask);
		191	WREG32(voltage->gpio.reg, tmp);
		192	if (voltage->delay)
		193	udelay(voltage->delay);
		194	} else {
		195	tmp = RREG32(voltage->gpio.reg);
		196	if (voltage->active_high)
		197	tmp &= ~voltage->gpio.mask;
		198	else
		199	tmp \|= voltage->gpio.mask;
		200	WREG32(voltage->gpio.reg, tmp);
		201	if (voltage->delay)
		202	udelay(voltage->delay);
2997	Serge	203	}
5078	serge	204	} else if (voltage->type == VOLTAGE_VDDC)
		205	radeon_atom_set_voltage(rdev, voltage->vddc_id, SET_VOLTAGE_TYPE_ASIC_VDDC);
		206
		207	dyn_pwrmgt_sclk_length = RREG32_PLL(DYN_PWRMGT_SCLK_LENGTH);
		208	dyn_pwrmgt_sclk_length &= ~REDUCED_POWER_SCLK_HILEN(0xf);
		209	dyn_pwrmgt_sclk_length &= ~REDUCED_POWER_SCLK_LOLEN(0xf);
		210	if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) {
		211	if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2) {
		212	dyn_pwrmgt_sclk_length \|= REDUCED_POWER_SCLK_HILEN(2);
		213	dyn_pwrmgt_sclk_length \|= REDUCED_POWER_SCLK_LOLEN(2);
		214	} else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4) {
		215	dyn_pwrmgt_sclk_length \|= REDUCED_POWER_SCLK_HILEN(4);
		216	dyn_pwrmgt_sclk_length \|= REDUCED_POWER_SCLK_LOLEN(4);
		217	}
		218	} else {
		219	dyn_pwrmgt_sclk_length \|= REDUCED_POWER_SCLK_HILEN(1);
		220	dyn_pwrmgt_sclk_length \|= REDUCED_POWER_SCLK_LOLEN(1);
2997	Serge	221	}
5078	serge	222	WREG32_PLL(DYN_PWRMGT_SCLK_LENGTH, dyn_pwrmgt_sclk_length);
		223
		224	dyn_sclk_vol_cntl = RREG32_PLL(DYN_SCLK_VOL_CNTL);
		225	if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) {
		226	dyn_sclk_vol_cntl \|= IO_CG_VOLTAGE_DROP;
		227	if (voltage->delay) {
		228	dyn_sclk_vol_cntl \|= VOLTAGE_DROP_SYNC;
		229	dyn_sclk_vol_cntl \|= VOLTAGE_DELAY_SEL(voltage->delay);
		230	} else
		231	dyn_sclk_vol_cntl &= ~VOLTAGE_DROP_SYNC;
		232	} else
		233	dyn_sclk_vol_cntl &= ~IO_CG_VOLTAGE_DROP;
		234	WREG32_PLL(DYN_SCLK_VOL_CNTL, dyn_sclk_vol_cntl);
		235
		236	hdp_dyn_cntl = RREG32_PLL(HDP_DYN_CNTL);
		237	if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN)
		238	hdp_dyn_cntl &= ~HDP_FORCEON;
		239	else
		240	hdp_dyn_cntl \|= HDP_FORCEON;
		241	WREG32_PLL(HDP_DYN_CNTL, hdp_dyn_cntl);
		242	#if 0
		243	/* mc_host_dyn seems to cause hangs from time to time */
		244	mc_host_dyn_cntl = RREG32_PLL(MC_HOST_DYN_CNTL);
		245	if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_MC_HOST_BLOCK_EN)
		246	mc_host_dyn_cntl &= ~MC_HOST_FORCEON;
		247	else
		248	mc_host_dyn_cntl \|= MC_HOST_FORCEON;
		249	WREG32_PLL(MC_HOST_DYN_CNTL, mc_host_dyn_cntl);
		250	#endif
		251	dyn_backbias_cntl = RREG32_PLL(DYN_BACKBIAS_CNTL);
		252	if (ps->misc & ATOM_PM_MISCINFO2_DYNAMIC_BACK_BIAS_EN)
		253	dyn_backbias_cntl \|= IO_CG_BACKBIAS_EN;
		254	else
		255	dyn_backbias_cntl &= ~IO_CG_BACKBIAS_EN;
		256	WREG32_PLL(DYN_BACKBIAS_CNTL, dyn_backbias_cntl);
		257
		258	/* set pcie lanes */
		259	if ((rdev->flags & RADEON_IS_PCIE) &&
		260	!(rdev->flags & RADEON_IS_IGP) &&
		261	rdev->asic->pm.set_pcie_lanes &&
		262	(ps->pcie_lanes !=
		263	rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) {
		264	radeon_set_pcie_lanes(rdev,
		265	ps->pcie_lanes);
		266	DRM_DEBUG("Setting: p: %d\n", ps->pcie_lanes);
		267	}
2997	Serge	268	}
5078	serge	269
		270	void rs600_pm_prepare(struct radeon_device *rdev)
		271	{
		272	struct drm_device *ddev = rdev->ddev;
		273	struct drm_crtc *crtc;
		274	struct radeon_crtc *radeon_crtc;
		275	u32 tmp;
		276
		277	/* disable any active CRTCs */
		278	list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
		279	radeon_crtc = to_radeon_crtc(crtc);
		280	if (radeon_crtc->enabled) {
		281	tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset);
		282	tmp \|= AVIVO_CRTC_DISP_READ_REQUEST_DISABLE;
		283	WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
		284	}
		285	}
		286	}
		287
		288	void rs600_pm_finish(struct radeon_device *rdev)
		289	{
		290	struct drm_device *ddev = rdev->ddev;
		291	struct drm_crtc *crtc;
		292	struct radeon_crtc *radeon_crtc;
		293	u32 tmp;
		294
		295	/* enable any active CRTCs */
		296	list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
		297	radeon_crtc = to_radeon_crtc(crtc);
		298	if (radeon_crtc->enabled) {
		299	tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset);
		300	tmp &= ~AVIVO_CRTC_DISP_READ_REQUEST_DISABLE;
		301	WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
		302	}
		303	}
		304	}
		305
1321	serge	306	/* hpd for digital panel detect/disconnect */
		307	bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
		308	{
		309	u32 tmp;
		310	bool connected = false;
		311
		312	switch (hpd) {
		313	case RADEON_HPD_1:
		314	tmp = RREG32(R_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS);
		315	if (G_007D04_DC_HOT_PLUG_DETECT1_SENSE(tmp))
		316	connected = true;
		317	break;
		318	case RADEON_HPD_2:
		319	tmp = RREG32(R_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS);
		320	if (G_007D14_DC_HOT_PLUG_DETECT2_SENSE(tmp))
		321	connected = true;
		322	break;
		323	default:
		324	break;
		325	}
		326	return connected;
		327	}
		328
		329	void rs600_hpd_set_polarity(struct radeon_device *rdev,
		330	enum radeon_hpd_id hpd)
		331	{
		332	u32 tmp;
		333	bool connected = rs600_hpd_sense(rdev, hpd);
		334
		335	switch (hpd) {
		336	case RADEON_HPD_1:
		337	tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL);
		338	if (connected)
		339	tmp &= ~S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1);
		340	else
		341	tmp \|= S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1);
		342	WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
		343	break;
		344	case RADEON_HPD_2:
		345	tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL);
		346	if (connected)
		347	tmp &= ~S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1);
		348	else
		349	tmp \|= S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1);
		350	WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
		351	break;
		352	default:
		353	break;
		354	}
		355	}
		356
		357	void rs600_hpd_init(struct radeon_device *rdev)
		358	{
		359	struct drm_device *dev = rdev->ddev;
		360	struct drm_connector *connector;
2997	Serge	361	unsigned enable = 0;
1321	serge	362
		363	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
		364	struct radeon_connector *radeon_connector = to_radeon_connector(connector);
		365	switch (radeon_connector->hpd.hpd) {
		366	case RADEON_HPD_1:
		367	WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL,
		368	S_007D00_DC_HOT_PLUG_DETECT1_EN(1));
		369	break;
		370	case RADEON_HPD_2:
		371	WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL,
		372	S_007D10_DC_HOT_PLUG_DETECT2_EN(1));
		373	break;
		374	default:
		375	break;
		376	}
2997	Serge	377	enable \|= 1 << radeon_connector->hpd.hpd;
		378	radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
1321	serge	379	}
2997	Serge	380	// radeon_irq_kms_enable_hpd(rdev, enable);
1321	serge	381	}
		382
		383	void rs600_hpd_fini(struct radeon_device *rdev)
		384	{
		385	struct drm_device *dev = rdev->ddev;
		386	struct drm_connector *connector;
2997	Serge	387	unsigned disable = 0;
1321	serge	388
		389	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
		390	struct radeon_connector *radeon_connector = to_radeon_connector(connector);
		391	switch (radeon_connector->hpd.hpd) {
		392	case RADEON_HPD_1:
		393	WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL,
		394	S_007D00_DC_HOT_PLUG_DETECT1_EN(0));
		395	break;
		396	case RADEON_HPD_2:
		397	WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL,
		398	S_007D10_DC_HOT_PLUG_DETECT2_EN(0));
		399	break;
		400	default:
		401	break;
		402	}
2997	Serge	403	disable \|= 1 << radeon_connector->hpd.hpd;
1321	serge	404	}
2997	Serge	405	// radeon_irq_kms_disable_hpd(rdev, disable);
1321	serge	406	}
		407
1963	serge	408	int rs600_asic_reset(struct radeon_device *rdev)
		409	{
		410	struct rv515_mc_save save;
		411	u32 status, tmp;
		412	int ret = 0;
		413
		414	status = RREG32(R_000E40_RBBM_STATUS);
		415	if (!G_000E40_GUI_ACTIVE(status)) {
		416	return 0;
		417	}
		418	/* Stops all mc clients */
		419	rv515_mc_stop(rdev, &save);
		420	status = RREG32(R_000E40_RBBM_STATUS);
		421	dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
		422	/* stop CP */
		423	WREG32(RADEON_CP_CSQ_CNTL, 0);
		424	tmp = RREG32(RADEON_CP_RB_CNTL);
		425	WREG32(RADEON_CP_RB_CNTL, tmp \| RADEON_RB_RPTR_WR_ENA);
		426	WREG32(RADEON_CP_RB_RPTR_WR, 0);
		427	WREG32(RADEON_CP_RB_WPTR, 0);
		428	WREG32(RADEON_CP_RB_CNTL, tmp);
		429	// pci_save_state(rdev->pdev);
		430	/* disable bus mastering */
2997	Serge	431	// pci_clear_master(rdev->pdev);
		432	mdelay(1);
1963	serge	433	/* reset GA+VAP */
		434	WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_VAP(1) \|
		435	S_0000F0_SOFT_RESET_GA(1));
		436	RREG32(R_0000F0_RBBM_SOFT_RESET);
		437	mdelay(500);
		438	WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
		439	mdelay(1);
		440	status = RREG32(R_000E40_RBBM_STATUS);
		441	dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
		442	/* reset CP */
		443	WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
		444	RREG32(R_0000F0_RBBM_SOFT_RESET);
		445	mdelay(500);
		446	WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
		447	mdelay(1);
		448	status = RREG32(R_000E40_RBBM_STATUS);
		449	dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
		450	/* reset MC */
		451	WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_MC(1));
		452	RREG32(R_0000F0_RBBM_SOFT_RESET);
		453	mdelay(500);
		454	WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
		455	mdelay(1);
		456	status = RREG32(R_000E40_RBBM_STATUS);
		457	dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
		458	/* restore PCI & busmastering */
		459	// pci_restore_state(rdev->pdev);
		460	/* Check if GPU is idle */
		461	if (G_000E40_GA_BUSY(status) \|\| G_000E40_VAP_BUSY(status)) {
		462	dev_err(rdev->dev, "failed to reset GPU\n");
		463	ret = -1;
		464	} else
		465	dev_info(rdev->dev, "GPU reset succeed\n");
		466	rv515_mc_resume(rdev, &save);
		467	return ret;
		468	}
		469
1128	serge	470	/*
		471	* GART.
		472	*/
		473	void rs600_gart_tlb_flush(struct radeon_device *rdev)
		474	{
		475	uint32_t tmp;
		476
1221	serge	477	tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
		478	tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE;
		479	WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
1128	serge	480
1221	serge	481	tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
1963	serge	482	tmp \|= S_000100_INVALIDATE_ALL_L1_TLBS(1) \| S_000100_INVALIDATE_L2_CACHE(1);
1221	serge	483	WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
1128	serge	484
1221	serge	485	tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
		486	tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE;
		487	WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
		488	tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
1128	serge	489	}
		490
2997	Serge	491	static int rs600_gart_init(struct radeon_device *rdev)
1128	serge	492	{
		493	int r;
		494
2997	Serge	495	if (rdev->gart.robj) {
1963	serge	496	WARN(1, "RS600 GART already initialized\n");
1221	serge	497	return 0;
		498	}
1128	serge	499	/* Initialize common gart structure */
		500	r = radeon_gart_init(rdev);
		501	if (r) {
		502	return r;
		503	}
		504	rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
1221	serge	505	return radeon_gart_table_vram_alloc(rdev);
		506	}
		507
2005	serge	508	static int rs600_gart_enable(struct radeon_device *rdev)
1221	serge	509	{
		510	u32 tmp;
		511	int r, i;
		512
2997	Serge	513	if (rdev->gart.robj == NULL) {
1221	serge	514	dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
		515	return -EINVAL;
		516	}
		517	r = radeon_gart_table_vram_pin(rdev);
		518	if (r)
1128	serge	519	return r;
1221	serge	520	/* Enable bus master */
2005	serge	521	tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
		522	WREG32(RADEON_BUS_CNTL, tmp);
1128	serge	523	/* FIXME: setup default page */
1221	serge	524	WREG32_MC(R_000100_MC_PT0_CNTL,
6104	serge	525	(S_000100_EFFECTIVE_L2_CACHE_SIZE(6) \|
		526	S_000100_EFFECTIVE_L2_QUEUE_SIZE(6)));
1321	serge	527
1128	serge	528	for (i = 0; i < 19; i++) {
1221	serge	529	WREG32_MC(R_00016C_MC_PT0_CLIENT0_CNTL + i,
6104	serge	530	S_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(1) \|
		531	S_00016C_SYSTEM_ACCESS_MODE_MASK(
1321	serge	532	V_00016C_SYSTEM_ACCESS_MODE_NOT_IN_SYS) \|
6104	serge	533	S_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS(
1321	serge	534	V_00016C_SYSTEM_APERTURE_UNMAPPED_PASSTHROUGH) \|
		535	S_00016C_EFFECTIVE_L1_CACHE_SIZE(3) \|
6104	serge	536	S_00016C_ENABLE_FRAGMENT_PROCESSING(1) \|
1321	serge	537	S_00016C_EFFECTIVE_L1_QUEUE_SIZE(3));
1128	serge	538	}
		539	/* enable first context */
1221	serge	540	WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL,
6104	serge	541	S_000102_ENABLE_PAGE_TABLE(1) \|
		542	S_000102_PAGE_TABLE_DEPTH(V_000102_PAGE_TABLE_FLAT));
1321	serge	543
1128	serge	544	/* disable all other contexts */
1321	serge	545	for (i = 1; i < 8; i++)
1221	serge	546	WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL + i, 0);
1128	serge	547
		548	/* setup the page table */
1221	serge	549	WREG32_MC(R_00012C_MC_PT0_CONTEXT0_FLAT_BASE_ADDR,
6104	serge	550	rdev->gart.table_addr);
1321	serge	551	WREG32_MC(R_00013C_MC_PT0_CONTEXT0_FLAT_START_ADDR, rdev->mc.gtt_start);
		552	WREG32_MC(R_00014C_MC_PT0_CONTEXT0_FLAT_END_ADDR, rdev->mc.gtt_end);
1221	serge	553	WREG32_MC(R_00011C_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0);
1128	serge	554
1321	serge	555	/* System context maps to VRAM space */
		556	WREG32_MC(R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start);
		557	WREG32_MC(R_000114_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end);
		558
1128	serge	559	/* enable page tables */
1221	serge	560	tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
		561	WREG32_MC(R_000100_MC_PT0_CNTL, (tmp \| S_000100_ENABLE_PT(1)));
		562	tmp = RREG32_MC(R_000009_MC_CNTL1);
		563	WREG32_MC(R_000009_MC_CNTL1, (tmp \| S_000009_ENABLE_PAGE_TABLES(1)));
1128	serge	564	rs600_gart_tlb_flush(rdev);
2997	Serge	565	DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
		566	(unsigned)(rdev->mc.gtt_size >> 20),
		567	(unsigned long long)rdev->gart.table_addr);
1128	serge	568	rdev->gart.ready = true;
		569	return 0;
		570	}
		571
2997	Serge	572	static void rs600_gart_disable(struct radeon_device *rdev)
1128	serge	573	{
1321	serge	574	u32 tmp;
1128	serge	575
		576	/* FIXME: disable out of gart access */
1221	serge	577	WREG32_MC(R_000100_MC_PT0_CNTL, 0);
		578	tmp = RREG32_MC(R_000009_MC_CNTL1);
		579	WREG32_MC(R_000009_MC_CNTL1, tmp & C_000009_ENABLE_PAGE_TABLES);
2997	Serge	580	radeon_gart_table_vram_unpin(rdev);
1128	serge	581	}
		582
2997	Serge	583	static void rs600_gart_fini(struct radeon_device *rdev)
1221	serge	584	{
1963	serge	585	radeon_gart_fini(rdev);
1221	serge	586	rs600_gart_disable(rdev);
		587	radeon_gart_table_vram_free(rdev);
		588	}
		589
6104	serge	590	uint64_t rs600_gart_get_page_entry(uint64_t addr, uint32_t flags)
1128	serge	591	{
		592	addr = addr & 0xFFFFFFFFFFFFF000ULL;
5078	serge	593	addr \|= R600_PTE_SYSTEM;
		594	if (flags & RADEON_GART_PAGE_VALID)
		595	addr \|= R600_PTE_VALID;
		596	if (flags & RADEON_GART_PAGE_READ)
		597	addr \|= R600_PTE_READABLE;
		598	if (flags & RADEON_GART_PAGE_WRITE)
		599	addr \|= R600_PTE_WRITEABLE;
		600	if (flags & RADEON_GART_PAGE_SNOOP)
		601	addr \|= R600_PTE_SNOOPED;
6104	serge	602	return addr;
1128	serge	603	}
		604
6104	serge	605	void rs600_gart_set_page(struct radeon_device *rdev, unsigned i,
		606	uint64_t entry)
		607	{
		608	void __iomem ptr = (void )rdev->gart.ptr;
		609	writeq(entry, ptr + (i * 8));
		610	}
		611
1321	serge	612	int rs600_irq_set(struct radeon_device *rdev)
		613	{
		614	uint32_t tmp = 0;
		615	uint32_t mode_int = 0;
		616	u32 hpd1 = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL) &
		617	~S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1);
		618	u32 hpd2 = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL) &
		619	~S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1);
2997	Serge	620	u32 hdmi0;
		621	if (ASIC_IS_DCE2(rdev))
		622	hdmi0 = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL) &
		623	~S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1);
		624	else
		625	hdmi0 = 0;
1128	serge	626
6104	serge	627	if (!rdev->irq.installed) {
1963	serge	628	WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
1403	serge	629	WREG32(R_000040_GEN_INT_CNTL, 0);
		630	return -EINVAL;
		631	}
2997	Serge	632	if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
1321	serge	633	tmp \|= S_000040_SW_INT_EN(1);
		634	}
1963	serge	635	if (rdev->irq.crtc_vblank_int[0] \|\|
2997	Serge	636	atomic_read(&rdev->irq.pflip[0])) {
1321	serge	637	mode_int \|= S_006540_D1MODE_VBLANK_INT_MASK(1);
		638	}
1963	serge	639	if (rdev->irq.crtc_vblank_int[1] \|\|
2997	Serge	640	atomic_read(&rdev->irq.pflip[1])) {
1321	serge	641	mode_int \|= S_006540_D2MODE_VBLANK_INT_MASK(1);
		642	}
		643	if (rdev->irq.hpd[0]) {
		644	hpd1 \|= S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1);
		645	}
		646	if (rdev->irq.hpd[1]) {
		647	hpd2 \|= S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1);
		648	}
2997	Serge	649	if (rdev->irq.afmt[0]) {
		650	hdmi0 \|= S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1);
		651	}
1321	serge	652	WREG32(R_000040_GEN_INT_CNTL, tmp);
		653	WREG32(R_006540_DxMODE_INT_MASK, mode_int);
		654	WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
		655	WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
2997	Serge	656	if (ASIC_IS_DCE2(rdev))
		657	WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, hdmi0);
6104	serge	658
		659	/* posting read */
		660	RREG32(R_000040_GEN_INT_CNTL);
		661
1321	serge	662	return 0;
		663	}
1128	serge	664
1963	serge	665	static inline u32 rs600_irq_ack(struct radeon_device *rdev)
1128	serge	666	{
1221	serge	667	uint32_t irqs = RREG32(R_000044_GEN_INT_STATUS);
1963	serge	668	uint32_t irq_mask = S_000044_SW_INT(1);
1321	serge	669	u32 tmp;
1128	serge	670
1221	serge	671	if (G_000044_DISPLAY_INT_STAT(irqs)) {
1963	serge	672	rdev->irq.stat_regs.r500.disp_int = RREG32(R_007EDC_DISP_INTERRUPT_STATUS);
		673	if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
1221	serge	674	WREG32(R_006534_D1MODE_VBLANK_STATUS,
		675	S_006534_D1MODE_VBLANK_ACK(1));
		676	}
1963	serge	677	if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
1221	serge	678	WREG32(R_006D34_D2MODE_VBLANK_STATUS,
		679	S_006D34_D2MODE_VBLANK_ACK(1));
		680	}
1963	serge	681	if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
1321	serge	682	tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL);
		683	tmp \|= S_007D08_DC_HOT_PLUG_DETECT1_INT_ACK(1);
		684	WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
		685	}
1963	serge	686	if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
1321	serge	687	tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL);
		688	tmp \|= S_007D18_DC_HOT_PLUG_DETECT2_INT_ACK(1);
		689	WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
		690	}
1221	serge	691	} else {
1963	serge	692	rdev->irq.stat_regs.r500.disp_int = 0;
1129	serge	693	}
1128	serge	694
2997	Serge	695	if (ASIC_IS_DCE2(rdev)) {
		696	rdev->irq.stat_regs.r500.hdmi0_status = RREG32(R_007404_HDMI0_STATUS) &
		697	S_007404_HDMI0_AZ_FORMAT_WTRIG(1);
		698	if (G_007404_HDMI0_AZ_FORMAT_WTRIG(rdev->irq.stat_regs.r500.hdmi0_status)) {
		699	tmp = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL);
		700	tmp \|= S_007408_HDMI0_AZ_FORMAT_WTRIG_ACK(1);
		701	WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, tmp);
		702	}
		703	} else
		704	rdev->irq.stat_regs.r500.hdmi0_status = 0;
		705
1221	serge	706	if (irqs) {
		707	WREG32(R_000044_GEN_INT_STATUS, irqs);
1128	serge	708	}
1221	serge	709	return irqs & irq_mask;
1128	serge	710	}
		711
1221	serge	712	void rs600_irq_disable(struct radeon_device *rdev)
1128	serge	713	{
2997	Serge	714	u32 hdmi0 = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL) &
		715	~S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1);
		716	WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, hdmi0);
1221	serge	717	WREG32(R_000040_GEN_INT_CNTL, 0);
		718	WREG32(R_006540_DxMODE_INT_MASK, 0);
		719	/* Wait and acknowledge irq */
		720	mdelay(1);
1963	serge	721	rs600_irq_ack(rdev);
1128	serge	722	}
		723
2005	serge	724	int rs600_irq_process(struct radeon_device *rdev)
		725	{
		726	u32 status, msi_rearm;
		727	bool queue_hotplug = false;
2997	Serge	728	bool queue_hdmi = false;
1128	serge	729
2005	serge	730	status = rs600_irq_ack(rdev);
2997	Serge	731	if (!status &&
		732	!rdev->irq.stat_regs.r500.disp_int &&
		733	!rdev->irq.stat_regs.r500.hdmi0_status) {
2005	serge	734	return IRQ_NONE;
		735	}
2997	Serge	736	while (status \|\|
		737	rdev->irq.stat_regs.r500.disp_int \|\|
		738	rdev->irq.stat_regs.r500.hdmi0_status) {
2005	serge	739	/* SW interrupt */
		740	if (G_000044_SW_INT(status)) {
2997	Serge	741	radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
2005	serge	742	}
		743	/* Vertical blank interrupts */
		744	if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
		745	if (rdev->irq.crtc_vblank_int[0]) {
6104	serge	746	drm_handle_vblank(rdev->ddev, 0);
2005	serge	747	rdev->pm.vblank_sync = true;
6104	serge	748	wake_up(&rdev->irq.vblank_queue);
2005	serge	749	}
6104	serge	750	if (atomic_read(&rdev->irq.pflip[0]))
		751	radeon_crtc_handle_vblank(rdev, 0);
2005	serge	752	}
		753	if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
		754	if (rdev->irq.crtc_vblank_int[1]) {
6104	serge	755	drm_handle_vblank(rdev->ddev, 1);
2005	serge	756	rdev->pm.vblank_sync = true;
6104	serge	757	wake_up(&rdev->irq.vblank_queue);
2005	serge	758	}
6104	serge	759	if (atomic_read(&rdev->irq.pflip[1]))
		760	radeon_crtc_handle_vblank(rdev, 1);
2005	serge	761	}
		762	if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
		763	queue_hotplug = true;
		764	DRM_DEBUG("HPD1\n");
		765	}
		766	if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
		767	queue_hotplug = true;
		768	DRM_DEBUG("HPD2\n");
		769	}
2997	Serge	770	if (G_007404_HDMI0_AZ_FORMAT_WTRIG(rdev->irq.stat_regs.r500.hdmi0_status)) {
		771	queue_hdmi = true;
		772	DRM_DEBUG("HDMI0\n");
		773	}
2005	serge	774	status = rs600_irq_ack(rdev);
		775	}
		776	// if (queue_hotplug)
		777	// schedule_work(&rdev->hotplug_work);
2997	Serge	778	// if (queue_hdmi)
		779	// schedule_work(&rdev->audio_work);
2005	serge	780	if (rdev->msi_enabled) {
		781	switch (rdev->family) {
		782	case CHIP_RS600:
		783	case CHIP_RS690:
		784	case CHIP_RS740:
		785	msi_rearm = RREG32(RADEON_BUS_CNTL) & ~RS600_MSI_REARM;
		786	WREG32(RADEON_BUS_CNTL, msi_rearm);
		787	WREG32(RADEON_BUS_CNTL, msi_rearm \| RS600_MSI_REARM);
		788	break;
		789	default:
2997	Serge	790	WREG32(RADEON_MSI_REARM_EN, RV370_MSI_REARM_EN);
2005	serge	791	break;
		792	}
		793	}
		794	return IRQ_HANDLED;
		795	}
		796
1221	serge	797	u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc)
1128	serge	798	{
1221	serge	799	if (crtc == 0)
		800	return RREG32(R_0060A4_D1CRTC_STATUS_FRAME_COUNT);
		801	else
		802	return RREG32(R_0068A4_D2CRTC_STATUS_FRAME_COUNT);
1128	serge	803	}
		804
		805	int rs600_mc_wait_for_idle(struct radeon_device *rdev)
		806	{
		807	unsigned i;
		808
		809	for (i = 0; i < rdev->usec_timeout; i++) {
1221	serge	810	if (G_000000_MC_IDLE(RREG32_MC(R_000000_MC_STATUS)))
1128	serge	811	return 0;
1221	serge	812	udelay(1);
1128	serge	813	}
		814	return -1;
		815	}
		816
2997	Serge	817	static void rs600_gpu_init(struct radeon_device *rdev)
1128	serge	818	{
		819	r420_pipes_init(rdev);
1221	serge	820	/* Wait for mc idle */
		821	if (rs600_mc_wait_for_idle(rdev))
		822	dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
1128	serge	823	}
		824
2997	Serge	825	static void rs600_mc_init(struct radeon_device *rdev)
1128	serge	826	{
1430	serge	827	u64 base;
		828
1963	serge	829	rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
		830	rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
1128	serge	831	rdev->mc.vram_is_ddr = true;
		832	rdev->mc.vram_width = 128;
1321	serge	833	rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
		834	rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
1430	serge	835	rdev->mc.visible_vram_size = rdev->mc.aper_size;
		836	rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
		837	base = RREG32_MC(R_000004_MC_FB_LOCATION);
		838	base = G_000004_MC_FB_START(base) << 16;
		839	radeon_vram_location(rdev, &rdev->mc, base);
1963	serge	840	rdev->mc.gtt_base_align = 0;
1430	serge	841	radeon_gtt_location(rdev, &rdev->mc);
1963	serge	842	radeon_update_bandwidth_info(rdev);
1128	serge	843	}
		844
1179	serge	845	void rs600_bandwidth_update(struct radeon_device *rdev)
		846	{
1963	serge	847	struct drm_display_mode *mode0 = NULL;
		848	struct drm_display_mode *mode1 = NULL;
		849	u32 d1mode_priority_a_cnt, d2mode_priority_a_cnt;
		850	/* FIXME: implement full support */
		851
5271	serge	852	if (!rdev->mode_info.mode_config_initialized)
		853	return;
		854
1963	serge	855	radeon_update_display_priority(rdev);
		856
		857	if (rdev->mode_info.crtcs[0]->base.enabled)
		858	mode0 = &rdev->mode_info.crtcs[0]->base.mode;
		859	if (rdev->mode_info.crtcs[1]->base.enabled)
		860	mode1 = &rdev->mode_info.crtcs[1]->base.mode;
		861
		862	rs690_line_buffer_adjust(rdev, mode0, mode1);
		863
		864	if (rdev->disp_priority == 2) {
		865	d1mode_priority_a_cnt = RREG32(R_006548_D1MODE_PRIORITY_A_CNT);
		866	d2mode_priority_a_cnt = RREG32(R_006D48_D2MODE_PRIORITY_A_CNT);
		867	d1mode_priority_a_cnt \|= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1);
		868	d2mode_priority_a_cnt \|= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1);
		869	WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);
		870	WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt);
		871	WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);
		872	WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt);
		873	}
1179	serge	874	}
1128	serge	875
		876	uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg)
		877	{
5078	serge	878	unsigned long flags;
		879	u32 r;
		880
		881	spin_lock_irqsave(&rdev->mc_idx_lock, flags);
1221	serge	882	WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) \|
		883	S_000070_MC_IND_CITF_ARB0(1));
5078	serge	884	r = RREG32(R_000074_MC_IND_DATA);
		885	spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
		886	return r;
1221	serge	887	}
1128	serge	888
1221	serge	889	void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
		890	{
5078	serge	891	unsigned long flags;
		892
		893	spin_lock_irqsave(&rdev->mc_idx_lock, flags);
1221	serge	894	WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) \|
		895	S_000070_MC_IND_CITF_ARB0(1) \| S_000070_MC_IND_WR_EN(1));
		896	WREG32(R_000074_MC_IND_DATA, v);
5078	serge	897	spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
1221	serge	898	}
		899
2997	Serge	900	static void rs600_debugfs(struct radeon_device *rdev)
1221	serge	901	{
		902	if (r100_debugfs_rbbm_init(rdev))
		903	DRM_ERROR("Failed to register debugfs file for RBBM !\n");
		904	}
		905
		906	void rs600_set_safe_registers(struct radeon_device *rdev)
		907	{
		908	rdev->config.r300.reg_safe_bm = rs600_reg_safe_bm;
		909	rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rs600_reg_safe_bm);
		910	}
		911
		912	static void rs600_mc_program(struct radeon_device *rdev)
		913	{
		914	struct rv515_mc_save save;
		915
		916	/* Stops all mc clients */
		917	rv515_mc_stop(rdev, &save);
		918
		919	/* Wait for mc idle */
		920	if (rs600_mc_wait_for_idle(rdev))
		921	dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
		922
		923	/* FIXME: What does AGP means for such chipset ? */
		924	WREG32_MC(R_000005_MC_AGP_LOCATION, 0x0FFFFFFF);
		925	WREG32_MC(R_000006_AGP_BASE, 0);
		926	WREG32_MC(R_000007_AGP_BASE_2, 0);
		927	/* Program MC */
		928	WREG32_MC(R_000004_MC_FB_LOCATION,
		929	S_000004_MC_FB_START(rdev->mc.vram_start >> 16) \|
		930	S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16));
		931	WREG32(R_000134_HDP_FB_LOCATION,
		932	S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
		933
		934	rv515_mc_resume(rdev, &save);
		935	}
		936
		937	static int rs600_startup(struct radeon_device *rdev)
		938	{
		939	int r;
		940
		941	rs600_mc_program(rdev);
		942	/* Resume clock */
		943	rv515_clock_startup(rdev);
		944	/* Initialize GPU configuration (# pipes, ...) */
		945	rs600_gpu_init(rdev);
		946	/* Initialize GART (initialize after TTM so we can allocate
		947	* memory through TTM but finalize after TTM) */
		948	r = rs600_gart_enable(rdev);
		949	if (r)
6104	serge	950	return r;
2005	serge	951
		952	/* allocate wb buffer */
		953	r = radeon_wb_init(rdev);
		954	if (r)
		955	return r;
		956
3192	Serge	957	r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
		958	if (r) {
		959	dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
		960	return r;
		961	}
		962
1221	serge	963	/* Enable IRQ */
3764	Serge	964	if (!rdev->irq.installed) {
		965	r = radeon_irq_kms_init(rdev);
		966	if (r)
		967	return r;
		968	}
		969
2005	serge	970	rs600_irq_set(rdev);
1403	serge	971	rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
1221	serge	972	/* 1M ring buffer */
1413	serge	973	r = r100_cp_init(rdev, 1024 * 1024);
		974	if (r) {
1963	serge	975	dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
1413	serge	976	return r;
		977	}
2997	Serge	978
		979	r = radeon_ib_pool_init(rdev);
2005	serge	980	if (r) {
2997	Serge	981	dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
2005	serge	982	return r;
		983	}
2997	Serge	984
6104	serge	985	r = radeon_audio_init(rdev);
5078	serge	986	if (r) {
		987	dev_err(rdev->dev, "failed initializing audio\n");
		988	return r;
		989	}
2997	Serge	990
1221	serge	991	return 0;
1128	serge	992	}
		993
1221	serge	994
6104	serge	995	void rs600_fini(struct radeon_device *rdev)
		996	{
		997	radeon_pm_fini(rdev);
		998	radeon_audio_fini(rdev);
		999	r100_cp_fini(rdev);
		1000	radeon_wb_fini(rdev);
		1001	radeon_ib_pool_fini(rdev);
		1002	radeon_gem_fini(rdev);
		1003	rs600_gart_fini(rdev);
		1004	radeon_irq_kms_fini(rdev);
		1005	radeon_fence_driver_fini(rdev);
		1006	radeon_bo_fini(rdev);
		1007	radeon_atombios_fini(rdev);
		1008	kfree(rdev->bios);
		1009	rdev->bios = NULL;
		1010	}
1221	serge	1011
		1012	int rs600_init(struct radeon_device *rdev)
1128	serge	1013	{
1221	serge	1014	int r;
		1015
		1016	/* Disable VGA */
		1017	rv515_vga_render_disable(rdev);
		1018	/* Initialize scratch registers */
		1019	radeon_scratch_init(rdev);
		1020	/* Initialize surface registers */
		1021	radeon_surface_init(rdev);
1963	serge	1022	/* restore some register to sane defaults */
		1023	r100_restore_sanity(rdev);
1221	serge	1024	/* BIOS */
		1025	if (!radeon_get_bios(rdev)) {
		1026	if (ASIC_IS_AVIVO(rdev))
		1027	return -EINVAL;
		1028	}
		1029	if (rdev->is_atom_bios) {
		1030	r = radeon_atombios_init(rdev);
		1031	if (r)
		1032	return r;
		1033	} else {
		1034	dev_err(rdev->dev, "Expecting atombios for RS600 GPU\n");
		1035	return -EINVAL;
		1036	}
		1037	/* Reset gpu before posting otherwise ATOM will enter infinite loop */
1963	serge	1038	if (radeon_asic_reset(rdev)) {
1221	serge	1039	dev_warn(rdev->dev,
		1040	"GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
		1041	RREG32(R_000E40_RBBM_STATUS),
		1042	RREG32(R_0007C0_CP_STAT));
		1043	}
		1044	/* check if cards are posted or not */
1321	serge	1045	if (radeon_boot_test_post_card(rdev) == false)
		1046	return -EINVAL;
		1047
1221	serge	1048	/* Initialize clocks */
		1049	radeon_get_clock_info(rdev->ddev);
1430	serge	1050	/* initialize memory controller */
		1051	rs600_mc_init(rdev);
1221	serge	1052	rs600_debugfs(rdev);
		1053	/* Fence driver */
2005	serge	1054	r = radeon_fence_driver_init(rdev);
		1055	if (r)
		1056	return r;
1221	serge	1057	/* Memory manager */
1321	serge	1058	r = radeon_bo_init(rdev);
1221	serge	1059	if (r)
		1060	return r;
		1061	r = rs600_gart_init(rdev);
		1062	if (r)
		1063	return r;
		1064	rs600_set_safe_registers(rdev);
2997	Serge	1065
5078	serge	1066	/* Initialize power management */
		1067	radeon_pm_init(rdev);
		1068
1221	serge	1069	rdev->accel_working = true;
		1070	r = rs600_startup(rdev);
		1071	if (r) {
		1072	/* Somethings want wront with the accel init stop accel */
		1073	dev_err(rdev->dev, "Disabling GPU acceleration\n");
6104	serge	1074	r100_cp_fini(rdev);
		1075	radeon_wb_fini(rdev);
		1076	radeon_ib_pool_fini(rdev);
1221	serge	1077	rs600_gart_fini(rdev);
6104	serge	1078	radeon_irq_kms_fini(rdev);
1221	serge	1079	rdev->accel_working = false;
		1080	}
		1081	return 0;
1128	serge	1082	}

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(root)/drivers/video/drm/radeon/rs600.c – Rev 6104