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1128 | serge | 1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
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3 | * Copyright 2008 Red Hat Inc. |
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4 | * Copyright 2009 Jerome Glisse. |
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5 | * |
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6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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7 | * copy of this software and associated documentation files (the "Software"), |
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8 | * to deal in the Software without restriction, including without limitation |
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9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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10 | * and/or sell copies of the Software, and to permit persons to whom the |
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11 | * Software is furnished to do so, subject to the following conditions: |
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12 | * |
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13 | * The above copyright notice and this permission notice shall be included in |
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14 | * all copies or substantial portions of the Software. |
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15 | * |
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16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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22 | * OTHER DEALINGS IN THE SOFTWARE. |
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23 | * |
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24 | * Authors: Dave Airlie |
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25 | * Alex Deucher |
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26 | * Jerome Glisse |
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27 | */ |
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1221 | serge | 28 | /* RS600 / Radeon X1250/X1270 integrated GPU |
29 | * |
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30 | * This file gather function specific to RS600 which is the IGP of |
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31 | * the X1250/X1270 family supporting intel CPU (while RS690/RS740 |
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32 | * is the X1250/X1270 supporting AMD CPU). The display engine are |
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33 | * the avivo one, bios is an atombios, 3D block are the one of the |
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34 | * R4XX family. The GART is different from the RS400 one and is very |
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35 | * close to the one of the R600 family (R600 likely being an evolution |
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36 | * of the RS600 GART block). |
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37 | */ |
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2997 | Serge | 38 | #include |
1128 | serge | 39 | #include "radeon.h" |
1963 | serge | 40 | #include "radeon_asic.h" |
1221 | serge | 41 | #include "atom.h" |
42 | #include "rs600d.h" |
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1128 | serge | 43 | |
1179 | serge | 44 | #include "rs600_reg_safe.h" |
45 | |||
2997 | Serge | 46 | static void rs600_gpu_init(struct radeon_device *rdev); |
1128 | serge | 47 | int rs600_mc_wait_for_idle(struct radeon_device *rdev); |
48 | |||
2997 | Serge | 49 | static const u32 crtc_offsets[2] = |
50 | { |
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51 | 0, |
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52 | AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL |
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53 | }; |
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54 | |||
3764 | Serge | 55 | static bool avivo_is_in_vblank(struct radeon_device *rdev, int crtc) |
56 | { |
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57 | if (RREG32(AVIVO_D1CRTC_STATUS + crtc_offsets[crtc]) & AVIVO_D1CRTC_V_BLANK) |
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58 | return true; |
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59 | else |
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60 | return false; |
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61 | } |
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62 | |||
63 | static bool avivo_is_counter_moving(struct radeon_device *rdev, int crtc) |
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64 | { |
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65 | u32 pos1, pos2; |
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66 | |||
67 | pos1 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]); |
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68 | pos2 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]); |
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69 | |||
70 | if (pos1 != pos2) |
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71 | return true; |
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72 | else |
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73 | return false; |
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74 | } |
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75 | |||
76 | /** |
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77 | * avivo_wait_for_vblank - vblank wait asic callback. |
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78 | * |
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79 | * @rdev: radeon_device pointer |
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80 | * @crtc: crtc to wait for vblank on |
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81 | * |
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82 | * Wait for vblank on the requested crtc (r5xx-r7xx). |
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83 | */ |
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2997 | Serge | 84 | void avivo_wait_for_vblank(struct radeon_device *rdev, int crtc) |
85 | { |
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3764 | Serge | 86 | unsigned i = 0; |
2997 | Serge | 87 | |
88 | if (crtc >= rdev->num_crtc) |
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89 | return; |
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90 | |||
3764 | Serge | 91 | if (!(RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[crtc]) & AVIVO_CRTC_EN)) |
92 | return; |
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93 | |||
94 | /* depending on when we hit vblank, we may be close to active; if so, |
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95 | * wait for another frame. |
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96 | */ |
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97 | while (avivo_is_in_vblank(rdev, crtc)) { |
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98 | if (i++ % 100 == 0) { |
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99 | if (!avivo_is_counter_moving(rdev, crtc)) |
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2997 | Serge | 100 | break; |
101 | } |
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3764 | Serge | 102 | } |
103 | |||
104 | while (!avivo_is_in_vblank(rdev, crtc)) { |
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105 | if (i++ % 100 == 0) { |
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106 | if (!avivo_is_counter_moving(rdev, crtc)) |
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107 | break; |
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108 | } |
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2997 | Serge | 109 | for (i = 0; i < rdev->usec_timeout; i++) { |
110 | if (RREG32(AVIVO_D1CRTC_STATUS + crtc_offsets[crtc]) & AVIVO_D1CRTC_V_BLANK) |
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111 | break; |
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112 | udelay(1); |
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113 | } |
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114 | } |
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115 | } |
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1321 | serge | 116 | /* hpd for digital panel detect/disconnect */ |
117 | bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) |
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118 | { |
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119 | u32 tmp; |
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120 | bool connected = false; |
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121 | |||
122 | switch (hpd) { |
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123 | case RADEON_HPD_1: |
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124 | tmp = RREG32(R_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS); |
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125 | if (G_007D04_DC_HOT_PLUG_DETECT1_SENSE(tmp)) |
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126 | connected = true; |
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127 | break; |
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128 | case RADEON_HPD_2: |
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129 | tmp = RREG32(R_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS); |
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130 | if (G_007D14_DC_HOT_PLUG_DETECT2_SENSE(tmp)) |
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131 | connected = true; |
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132 | break; |
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133 | default: |
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134 | break; |
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135 | } |
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136 | return connected; |
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137 | } |
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138 | |||
139 | void rs600_hpd_set_polarity(struct radeon_device *rdev, |
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140 | enum radeon_hpd_id hpd) |
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141 | { |
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142 | u32 tmp; |
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143 | bool connected = rs600_hpd_sense(rdev, hpd); |
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144 | |||
145 | switch (hpd) { |
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146 | case RADEON_HPD_1: |
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147 | tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL); |
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148 | if (connected) |
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149 | tmp &= ~S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1); |
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150 | else |
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151 | tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1); |
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152 | WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); |
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153 | break; |
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154 | case RADEON_HPD_2: |
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155 | tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL); |
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156 | if (connected) |
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157 | tmp &= ~S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1); |
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158 | else |
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159 | tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1); |
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160 | WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); |
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161 | break; |
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162 | default: |
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163 | break; |
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164 | } |
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165 | } |
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166 | |||
167 | void rs600_hpd_init(struct radeon_device *rdev) |
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168 | { |
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169 | struct drm_device *dev = rdev->ddev; |
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170 | struct drm_connector *connector; |
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2997 | Serge | 171 | unsigned enable = 0; |
1321 | serge | 172 | |
173 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
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174 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
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175 | switch (radeon_connector->hpd.hpd) { |
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176 | case RADEON_HPD_1: |
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177 | WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL, |
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178 | S_007D00_DC_HOT_PLUG_DETECT1_EN(1)); |
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179 | break; |
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180 | case RADEON_HPD_2: |
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181 | WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL, |
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182 | S_007D10_DC_HOT_PLUG_DETECT2_EN(1)); |
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183 | break; |
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184 | default: |
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185 | break; |
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186 | } |
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2997 | Serge | 187 | enable |= 1 << radeon_connector->hpd.hpd; |
188 | radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd); |
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1321 | serge | 189 | } |
2997 | Serge | 190 | // radeon_irq_kms_enable_hpd(rdev, enable); |
1321 | serge | 191 | } |
192 | |||
193 | void rs600_hpd_fini(struct radeon_device *rdev) |
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194 | { |
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195 | struct drm_device *dev = rdev->ddev; |
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196 | struct drm_connector *connector; |
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2997 | Serge | 197 | unsigned disable = 0; |
1321 | serge | 198 | |
199 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
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200 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
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201 | switch (radeon_connector->hpd.hpd) { |
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202 | case RADEON_HPD_1: |
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203 | WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL, |
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204 | S_007D00_DC_HOT_PLUG_DETECT1_EN(0)); |
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205 | break; |
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206 | case RADEON_HPD_2: |
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207 | WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL, |
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208 | S_007D10_DC_HOT_PLUG_DETECT2_EN(0)); |
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209 | break; |
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210 | default: |
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211 | break; |
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212 | } |
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2997 | Serge | 213 | disable |= 1 << radeon_connector->hpd.hpd; |
1321 | serge | 214 | } |
2997 | Serge | 215 | // radeon_irq_kms_disable_hpd(rdev, disable); |
1321 | serge | 216 | } |
217 | |||
1963 | serge | 218 | int rs600_asic_reset(struct radeon_device *rdev) |
219 | { |
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220 | struct rv515_mc_save save; |
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221 | u32 status, tmp; |
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222 | int ret = 0; |
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223 | |||
224 | status = RREG32(R_000E40_RBBM_STATUS); |
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225 | if (!G_000E40_GUI_ACTIVE(status)) { |
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226 | return 0; |
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227 | } |
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228 | /* Stops all mc clients */ |
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229 | rv515_mc_stop(rdev, &save); |
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230 | status = RREG32(R_000E40_RBBM_STATUS); |
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231 | dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); |
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232 | /* stop CP */ |
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233 | WREG32(RADEON_CP_CSQ_CNTL, 0); |
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234 | tmp = RREG32(RADEON_CP_RB_CNTL); |
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235 | WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA); |
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236 | WREG32(RADEON_CP_RB_RPTR_WR, 0); |
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237 | WREG32(RADEON_CP_RB_WPTR, 0); |
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238 | WREG32(RADEON_CP_RB_CNTL, tmp); |
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239 | // pci_save_state(rdev->pdev); |
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240 | /* disable bus mastering */ |
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2997 | Serge | 241 | // pci_clear_master(rdev->pdev); |
242 | mdelay(1); |
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1963 | serge | 243 | /* reset GA+VAP */ |
244 | WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_VAP(1) | |
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245 | S_0000F0_SOFT_RESET_GA(1)); |
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246 | RREG32(R_0000F0_RBBM_SOFT_RESET); |
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247 | mdelay(500); |
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248 | WREG32(R_0000F0_RBBM_SOFT_RESET, 0); |
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249 | mdelay(1); |
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250 | status = RREG32(R_000E40_RBBM_STATUS); |
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251 | dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); |
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252 | /* reset CP */ |
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253 | WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1)); |
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254 | RREG32(R_0000F0_RBBM_SOFT_RESET); |
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255 | mdelay(500); |
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256 | WREG32(R_0000F0_RBBM_SOFT_RESET, 0); |
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257 | mdelay(1); |
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258 | status = RREG32(R_000E40_RBBM_STATUS); |
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259 | dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); |
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260 | /* reset MC */ |
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261 | WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_MC(1)); |
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262 | RREG32(R_0000F0_RBBM_SOFT_RESET); |
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263 | mdelay(500); |
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264 | WREG32(R_0000F0_RBBM_SOFT_RESET, 0); |
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265 | mdelay(1); |
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266 | status = RREG32(R_000E40_RBBM_STATUS); |
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267 | dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); |
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268 | /* restore PCI & busmastering */ |
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269 | // pci_restore_state(rdev->pdev); |
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270 | /* Check if GPU is idle */ |
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271 | if (G_000E40_GA_BUSY(status) || G_000E40_VAP_BUSY(status)) { |
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272 | dev_err(rdev->dev, "failed to reset GPU\n"); |
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273 | ret = -1; |
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274 | } else |
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275 | dev_info(rdev->dev, "GPU reset succeed\n"); |
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276 | rv515_mc_resume(rdev, &save); |
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277 | return ret; |
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278 | } |
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279 | |||
1128 | serge | 280 | /* |
281 | * GART. |
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282 | */ |
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283 | void rs600_gart_tlb_flush(struct radeon_device *rdev) |
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284 | { |
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285 | uint32_t tmp; |
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286 | |||
1221 | serge | 287 | tmp = RREG32_MC(R_000100_MC_PT0_CNTL); |
288 | tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE; |
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289 | WREG32_MC(R_000100_MC_PT0_CNTL, tmp); |
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1128 | serge | 290 | |
1221 | serge | 291 | tmp = RREG32_MC(R_000100_MC_PT0_CNTL); |
1963 | serge | 292 | tmp |= S_000100_INVALIDATE_ALL_L1_TLBS(1) | S_000100_INVALIDATE_L2_CACHE(1); |
1221 | serge | 293 | WREG32_MC(R_000100_MC_PT0_CNTL, tmp); |
1128 | serge | 294 | |
1221 | serge | 295 | tmp = RREG32_MC(R_000100_MC_PT0_CNTL); |
296 | tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE; |
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297 | WREG32_MC(R_000100_MC_PT0_CNTL, tmp); |
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298 | tmp = RREG32_MC(R_000100_MC_PT0_CNTL); |
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1128 | serge | 299 | } |
300 | |||
2997 | Serge | 301 | static int rs600_gart_init(struct radeon_device *rdev) |
1128 | serge | 302 | { |
303 | int r; |
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304 | |||
2997 | Serge | 305 | if (rdev->gart.robj) { |
1963 | serge | 306 | WARN(1, "RS600 GART already initialized\n"); |
1221 | serge | 307 | return 0; |
308 | } |
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1128 | serge | 309 | /* Initialize common gart structure */ |
310 | r = radeon_gart_init(rdev); |
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311 | if (r) { |
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312 | return r; |
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313 | } |
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314 | rdev->gart.table_size = rdev->gart.num_gpu_pages * 8; |
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1221 | serge | 315 | return radeon_gart_table_vram_alloc(rdev); |
316 | } |
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317 | |||
2005 | serge | 318 | static int rs600_gart_enable(struct radeon_device *rdev) |
1221 | serge | 319 | { |
320 | u32 tmp; |
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321 | int r, i; |
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322 | |||
2997 | Serge | 323 | if (rdev->gart.robj == NULL) { |
1221 | serge | 324 | dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); |
325 | return -EINVAL; |
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326 | } |
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327 | r = radeon_gart_table_vram_pin(rdev); |
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328 | if (r) |
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1128 | serge | 329 | return r; |
1430 | serge | 330 | radeon_gart_restore(rdev); |
1221 | serge | 331 | /* Enable bus master */ |
2005 | serge | 332 | tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS; |
333 | WREG32(RADEON_BUS_CNTL, tmp); |
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1128 | serge | 334 | /* FIXME: setup default page */ |
1221 | serge | 335 | WREG32_MC(R_000100_MC_PT0_CNTL, |
336 | (S_000100_EFFECTIVE_L2_CACHE_SIZE(6) | |
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337 | S_000100_EFFECTIVE_L2_QUEUE_SIZE(6))); |
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1321 | serge | 338 | |
1128 | serge | 339 | for (i = 0; i < 19; i++) { |
1221 | serge | 340 | WREG32_MC(R_00016C_MC_PT0_CLIENT0_CNTL + i, |
341 | S_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(1) | |
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342 | S_00016C_SYSTEM_ACCESS_MODE_MASK( |
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1321 | serge | 343 | V_00016C_SYSTEM_ACCESS_MODE_NOT_IN_SYS) | |
1221 | serge | 344 | S_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS( |
1321 | serge | 345 | V_00016C_SYSTEM_APERTURE_UNMAPPED_PASSTHROUGH) | |
346 | S_00016C_EFFECTIVE_L1_CACHE_SIZE(3) | |
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1221 | serge | 347 | S_00016C_ENABLE_FRAGMENT_PROCESSING(1) | |
1321 | serge | 348 | S_00016C_EFFECTIVE_L1_QUEUE_SIZE(3)); |
1128 | serge | 349 | } |
350 | /* enable first context */ |
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1221 | serge | 351 | WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL, |
352 | S_000102_ENABLE_PAGE_TABLE(1) | |
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353 | S_000102_PAGE_TABLE_DEPTH(V_000102_PAGE_TABLE_FLAT)); |
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1321 | serge | 354 | |
1128 | serge | 355 | /* disable all other contexts */ |
1321 | serge | 356 | for (i = 1; i < 8; i++) |
1221 | serge | 357 | WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL + i, 0); |
1128 | serge | 358 | |
359 | /* setup the page table */ |
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1221 | serge | 360 | WREG32_MC(R_00012C_MC_PT0_CONTEXT0_FLAT_BASE_ADDR, |
1128 | serge | 361 | rdev->gart.table_addr); |
1321 | serge | 362 | WREG32_MC(R_00013C_MC_PT0_CONTEXT0_FLAT_START_ADDR, rdev->mc.gtt_start); |
363 | WREG32_MC(R_00014C_MC_PT0_CONTEXT0_FLAT_END_ADDR, rdev->mc.gtt_end); |
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1221 | serge | 364 | WREG32_MC(R_00011C_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0); |
1128 | serge | 365 | |
1321 | serge | 366 | /* System context maps to VRAM space */ |
367 | WREG32_MC(R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start); |
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368 | WREG32_MC(R_000114_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end); |
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369 | |||
1128 | serge | 370 | /* enable page tables */ |
1221 | serge | 371 | tmp = RREG32_MC(R_000100_MC_PT0_CNTL); |
372 | WREG32_MC(R_000100_MC_PT0_CNTL, (tmp | S_000100_ENABLE_PT(1))); |
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373 | tmp = RREG32_MC(R_000009_MC_CNTL1); |
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374 | WREG32_MC(R_000009_MC_CNTL1, (tmp | S_000009_ENABLE_PAGE_TABLES(1))); |
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1128 | serge | 375 | rs600_gart_tlb_flush(rdev); |
2997 | Serge | 376 | DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", |
377 | (unsigned)(rdev->mc.gtt_size >> 20), |
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378 | (unsigned long long)rdev->gart.table_addr); |
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1128 | serge | 379 | rdev->gart.ready = true; |
380 | return 0; |
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381 | } |
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382 | |||
2997 | Serge | 383 | static void rs600_gart_disable(struct radeon_device *rdev) |
1128 | serge | 384 | { |
1321 | serge | 385 | u32 tmp; |
1128 | serge | 386 | |
387 | /* FIXME: disable out of gart access */ |
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1221 | serge | 388 | WREG32_MC(R_000100_MC_PT0_CNTL, 0); |
389 | tmp = RREG32_MC(R_000009_MC_CNTL1); |
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390 | WREG32_MC(R_000009_MC_CNTL1, tmp & C_000009_ENABLE_PAGE_TABLES); |
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2997 | Serge | 391 | radeon_gart_table_vram_unpin(rdev); |
1128 | serge | 392 | } |
393 | |||
2997 | Serge | 394 | static void rs600_gart_fini(struct radeon_device *rdev) |
1221 | serge | 395 | { |
1963 | serge | 396 | radeon_gart_fini(rdev); |
1221 | serge | 397 | rs600_gart_disable(rdev); |
398 | radeon_gart_table_vram_free(rdev); |
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399 | } |
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400 | |||
1128 | serge | 401 | #define R600_PTE_VALID (1 << 0) |
402 | #define R600_PTE_SYSTEM (1 << 1) |
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403 | #define R600_PTE_SNOOPED (1 << 2) |
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404 | #define R600_PTE_READABLE (1 << 5) |
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405 | #define R600_PTE_WRITEABLE (1 << 6) |
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406 | |||
407 | int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr) |
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408 | { |
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2997 | Serge | 409 | void __iomem *ptr = (void *)rdev->gart.ptr; |
1128 | serge | 410 | |
411 | if (i < 0 || i > rdev->gart.num_gpu_pages) { |
||
412 | return -EINVAL; |
||
413 | } |
||
414 | addr = addr & 0xFFFFFFFFFFFFF000ULL; |
||
415 | addr |= R600_PTE_VALID | R600_PTE_SYSTEM | R600_PTE_SNOOPED; |
||
416 | addr |= R600_PTE_READABLE | R600_PTE_WRITEABLE; |
||
2160 | serge | 417 | writeq(addr, ptr + (i * 8)); |
1128 | serge | 418 | return 0; |
419 | } |
||
420 | |||
1321 | serge | 421 | int rs600_irq_set(struct radeon_device *rdev) |
422 | { |
||
423 | uint32_t tmp = 0; |
||
424 | uint32_t mode_int = 0; |
||
425 | u32 hpd1 = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL) & |
||
426 | ~S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1); |
||
427 | u32 hpd2 = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL) & |
||
428 | ~S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1); |
||
2997 | Serge | 429 | u32 hdmi0; |
430 | if (ASIC_IS_DCE2(rdev)) |
||
431 | hdmi0 = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL) & |
||
432 | ~S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1); |
||
433 | else |
||
434 | hdmi0 = 0; |
||
1128 | serge | 435 | |
1403 | serge | 436 | if (!rdev->irq.installed) { |
1963 | serge | 437 | WARN(1, "Can't enable IRQ/MSI because no handler is installed\n"); |
1403 | serge | 438 | WREG32(R_000040_GEN_INT_CNTL, 0); |
439 | return -EINVAL; |
||
440 | } |
||
2997 | Serge | 441 | if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) { |
1321 | serge | 442 | tmp |= S_000040_SW_INT_EN(1); |
443 | } |
||
1963 | serge | 444 | if (rdev->irq.crtc_vblank_int[0] || |
2997 | Serge | 445 | atomic_read(&rdev->irq.pflip[0])) { |
1321 | serge | 446 | mode_int |= S_006540_D1MODE_VBLANK_INT_MASK(1); |
447 | } |
||
1963 | serge | 448 | if (rdev->irq.crtc_vblank_int[1] || |
2997 | Serge | 449 | atomic_read(&rdev->irq.pflip[1])) { |
1321 | serge | 450 | mode_int |= S_006540_D2MODE_VBLANK_INT_MASK(1); |
451 | } |
||
452 | if (rdev->irq.hpd[0]) { |
||
453 | hpd1 |= S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1); |
||
454 | } |
||
455 | if (rdev->irq.hpd[1]) { |
||
456 | hpd2 |= S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1); |
||
457 | } |
||
2997 | Serge | 458 | if (rdev->irq.afmt[0]) { |
459 | hdmi0 |= S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1); |
||
460 | } |
||
1321 | serge | 461 | WREG32(R_000040_GEN_INT_CNTL, tmp); |
462 | WREG32(R_006540_DxMODE_INT_MASK, mode_int); |
||
463 | WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1); |
||
464 | WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2); |
||
2997 | Serge | 465 | if (ASIC_IS_DCE2(rdev)) |
466 | WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, hdmi0); |
||
1321 | serge | 467 | return 0; |
468 | } |
||
1128 | serge | 469 | |
1963 | serge | 470 | static inline u32 rs600_irq_ack(struct radeon_device *rdev) |
1128 | serge | 471 | { |
1221 | serge | 472 | uint32_t irqs = RREG32(R_000044_GEN_INT_STATUS); |
1963 | serge | 473 | uint32_t irq_mask = S_000044_SW_INT(1); |
1321 | serge | 474 | u32 tmp; |
1128 | serge | 475 | |
1221 | serge | 476 | if (G_000044_DISPLAY_INT_STAT(irqs)) { |
1963 | serge | 477 | rdev->irq.stat_regs.r500.disp_int = RREG32(R_007EDC_DISP_INTERRUPT_STATUS); |
478 | if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { |
||
1221 | serge | 479 | WREG32(R_006534_D1MODE_VBLANK_STATUS, |
480 | S_006534_D1MODE_VBLANK_ACK(1)); |
||
481 | } |
||
1963 | serge | 482 | if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { |
1221 | serge | 483 | WREG32(R_006D34_D2MODE_VBLANK_STATUS, |
484 | S_006D34_D2MODE_VBLANK_ACK(1)); |
||
485 | } |
||
1963 | serge | 486 | if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { |
1321 | serge | 487 | tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL); |
488 | tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_ACK(1); |
||
489 | WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); |
||
490 | } |
||
1963 | serge | 491 | if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { |
1321 | serge | 492 | tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL); |
493 | tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_ACK(1); |
||
494 | WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); |
||
495 | } |
||
1221 | serge | 496 | } else { |
1963 | serge | 497 | rdev->irq.stat_regs.r500.disp_int = 0; |
1129 | serge | 498 | } |
1128 | serge | 499 | |
2997 | Serge | 500 | if (ASIC_IS_DCE2(rdev)) { |
501 | rdev->irq.stat_regs.r500.hdmi0_status = RREG32(R_007404_HDMI0_STATUS) & |
||
502 | S_007404_HDMI0_AZ_FORMAT_WTRIG(1); |
||
503 | if (G_007404_HDMI0_AZ_FORMAT_WTRIG(rdev->irq.stat_regs.r500.hdmi0_status)) { |
||
504 | tmp = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL); |
||
505 | tmp |= S_007408_HDMI0_AZ_FORMAT_WTRIG_ACK(1); |
||
506 | WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, tmp); |
||
507 | } |
||
508 | } else |
||
509 | rdev->irq.stat_regs.r500.hdmi0_status = 0; |
||
510 | |||
1221 | serge | 511 | if (irqs) { |
512 | WREG32(R_000044_GEN_INT_STATUS, irqs); |
||
1128 | serge | 513 | } |
1221 | serge | 514 | return irqs & irq_mask; |
1128 | serge | 515 | } |
516 | |||
1221 | serge | 517 | void rs600_irq_disable(struct radeon_device *rdev) |
1128 | serge | 518 | { |
2997 | Serge | 519 | u32 hdmi0 = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL) & |
520 | ~S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1); |
||
521 | WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, hdmi0); |
||
1221 | serge | 522 | WREG32(R_000040_GEN_INT_CNTL, 0); |
523 | WREG32(R_006540_DxMODE_INT_MASK, 0); |
||
524 | /* Wait and acknowledge irq */ |
||
525 | mdelay(1); |
||
1963 | serge | 526 | rs600_irq_ack(rdev); |
1128 | serge | 527 | } |
528 | |||
2005 | serge | 529 | int rs600_irq_process(struct radeon_device *rdev) |
530 | { |
||
531 | u32 status, msi_rearm; |
||
532 | bool queue_hotplug = false; |
||
2997 | Serge | 533 | bool queue_hdmi = false; |
1128 | serge | 534 | |
2005 | serge | 535 | status = rs600_irq_ack(rdev); |
2997 | Serge | 536 | if (!status && |
537 | !rdev->irq.stat_regs.r500.disp_int && |
||
538 | !rdev->irq.stat_regs.r500.hdmi0_status) { |
||
2005 | serge | 539 | return IRQ_NONE; |
540 | } |
||
2997 | Serge | 541 | while (status || |
542 | rdev->irq.stat_regs.r500.disp_int || |
||
543 | rdev->irq.stat_regs.r500.hdmi0_status) { |
||
2005 | serge | 544 | /* SW interrupt */ |
545 | if (G_000044_SW_INT(status)) { |
||
2997 | Serge | 546 | radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); |
2005 | serge | 547 | } |
548 | /* Vertical blank interrupts */ |
||
549 | if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { |
||
550 | if (rdev->irq.crtc_vblank_int[0]) { |
||
551 | // drm_handle_vblank(rdev->ddev, 0); |
||
552 | rdev->pm.vblank_sync = true; |
||
553 | // wake_up(&rdev->irq.vblank_queue); |
||
554 | } |
||
555 | // if (rdev->irq.pflip[0]) |
||
556 | // radeon_crtc_handle_flip(rdev, 0); |
||
557 | } |
||
558 | if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { |
||
559 | if (rdev->irq.crtc_vblank_int[1]) { |
||
560 | // drm_handle_vblank(rdev->ddev, 1); |
||
561 | rdev->pm.vblank_sync = true; |
||
562 | // wake_up(&rdev->irq.vblank_queue); |
||
563 | } |
||
564 | // if (rdev->irq.pflip[1]) |
||
565 | // radeon_crtc_handle_flip(rdev, 1); |
||
566 | } |
||
567 | if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { |
||
568 | queue_hotplug = true; |
||
569 | DRM_DEBUG("HPD1\n"); |
||
570 | } |
||
571 | if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { |
||
572 | queue_hotplug = true; |
||
573 | DRM_DEBUG("HPD2\n"); |
||
574 | } |
||
2997 | Serge | 575 | if (G_007404_HDMI0_AZ_FORMAT_WTRIG(rdev->irq.stat_regs.r500.hdmi0_status)) { |
576 | queue_hdmi = true; |
||
577 | DRM_DEBUG("HDMI0\n"); |
||
578 | } |
||
2005 | serge | 579 | status = rs600_irq_ack(rdev); |
580 | } |
||
581 | // if (queue_hotplug) |
||
582 | // schedule_work(&rdev->hotplug_work); |
||
2997 | Serge | 583 | // if (queue_hdmi) |
584 | // schedule_work(&rdev->audio_work); |
||
2005 | serge | 585 | if (rdev->msi_enabled) { |
586 | switch (rdev->family) { |
||
587 | case CHIP_RS600: |
||
588 | case CHIP_RS690: |
||
589 | case CHIP_RS740: |
||
590 | msi_rearm = RREG32(RADEON_BUS_CNTL) & ~RS600_MSI_REARM; |
||
591 | WREG32(RADEON_BUS_CNTL, msi_rearm); |
||
592 | WREG32(RADEON_BUS_CNTL, msi_rearm | RS600_MSI_REARM); |
||
593 | break; |
||
594 | default: |
||
2997 | Serge | 595 | WREG32(RADEON_MSI_REARM_EN, RV370_MSI_REARM_EN); |
2005 | serge | 596 | break; |
597 | } |
||
598 | } |
||
599 | return IRQ_HANDLED; |
||
600 | } |
||
601 | |||
1221 | serge | 602 | u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc) |
1128 | serge | 603 | { |
1221 | serge | 604 | if (crtc == 0) |
605 | return RREG32(R_0060A4_D1CRTC_STATUS_FRAME_COUNT); |
||
606 | else |
||
607 | return RREG32(R_0068A4_D2CRTC_STATUS_FRAME_COUNT); |
||
1128 | serge | 608 | } |
609 | |||
610 | int rs600_mc_wait_for_idle(struct radeon_device *rdev) |
||
611 | { |
||
612 | unsigned i; |
||
613 | |||
614 | for (i = 0; i < rdev->usec_timeout; i++) { |
||
1221 | serge | 615 | if (G_000000_MC_IDLE(RREG32_MC(R_000000_MC_STATUS))) |
1128 | serge | 616 | return 0; |
1221 | serge | 617 | udelay(1); |
1128 | serge | 618 | } |
619 | return -1; |
||
620 | } |
||
621 | |||
2997 | Serge | 622 | static void rs600_gpu_init(struct radeon_device *rdev) |
1128 | serge | 623 | { |
624 | r420_pipes_init(rdev); |
||
1221 | serge | 625 | /* Wait for mc idle */ |
626 | if (rs600_mc_wait_for_idle(rdev)) |
||
627 | dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); |
||
1128 | serge | 628 | } |
629 | |||
2997 | Serge | 630 | static void rs600_mc_init(struct radeon_device *rdev) |
1128 | serge | 631 | { |
1430 | serge | 632 | u64 base; |
633 | |||
1963 | serge | 634 | rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); |
635 | rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); |
||
1128 | serge | 636 | rdev->mc.vram_is_ddr = true; |
637 | rdev->mc.vram_width = 128; |
||
1321 | serge | 638 | rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); |
639 | rdev->mc.mc_vram_size = rdev->mc.real_vram_size; |
||
1430 | serge | 640 | rdev->mc.visible_vram_size = rdev->mc.aper_size; |
641 | rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); |
||
642 | base = RREG32_MC(R_000004_MC_FB_LOCATION); |
||
643 | base = G_000004_MC_FB_START(base) << 16; |
||
644 | radeon_vram_location(rdev, &rdev->mc, base); |
||
1963 | serge | 645 | rdev->mc.gtt_base_align = 0; |
1430 | serge | 646 | radeon_gtt_location(rdev, &rdev->mc); |
1963 | serge | 647 | radeon_update_bandwidth_info(rdev); |
1128 | serge | 648 | } |
649 | |||
1179 | serge | 650 | void rs600_bandwidth_update(struct radeon_device *rdev) |
651 | { |
||
1963 | serge | 652 | struct drm_display_mode *mode0 = NULL; |
653 | struct drm_display_mode *mode1 = NULL; |
||
654 | u32 d1mode_priority_a_cnt, d2mode_priority_a_cnt; |
||
655 | /* FIXME: implement full support */ |
||
656 | |||
657 | radeon_update_display_priority(rdev); |
||
658 | |||
659 | if (rdev->mode_info.crtcs[0]->base.enabled) |
||
660 | mode0 = &rdev->mode_info.crtcs[0]->base.mode; |
||
661 | if (rdev->mode_info.crtcs[1]->base.enabled) |
||
662 | mode1 = &rdev->mode_info.crtcs[1]->base.mode; |
||
663 | |||
664 | rs690_line_buffer_adjust(rdev, mode0, mode1); |
||
665 | |||
666 | if (rdev->disp_priority == 2) { |
||
667 | d1mode_priority_a_cnt = RREG32(R_006548_D1MODE_PRIORITY_A_CNT); |
||
668 | d2mode_priority_a_cnt = RREG32(R_006D48_D2MODE_PRIORITY_A_CNT); |
||
669 | d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1); |
||
670 | d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1); |
||
671 | WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt); |
||
672 | WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt); |
||
673 | WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt); |
||
674 | WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt); |
||
675 | } |
||
1179 | serge | 676 | } |
1128 | serge | 677 | |
678 | uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg) |
||
679 | { |
||
1221 | serge | 680 | WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) | |
681 | S_000070_MC_IND_CITF_ARB0(1)); |
||
682 | return RREG32(R_000074_MC_IND_DATA); |
||
683 | } |
||
1128 | serge | 684 | |
1221 | serge | 685 | void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
686 | { |
||
687 | WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) | |
||
688 | S_000070_MC_IND_CITF_ARB0(1) | S_000070_MC_IND_WR_EN(1)); |
||
689 | WREG32(R_000074_MC_IND_DATA, v); |
||
690 | } |
||
691 | |||
2997 | Serge | 692 | static void rs600_debugfs(struct radeon_device *rdev) |
1221 | serge | 693 | { |
694 | if (r100_debugfs_rbbm_init(rdev)) |
||
695 | DRM_ERROR("Failed to register debugfs file for RBBM !\n"); |
||
696 | } |
||
697 | |||
698 | void rs600_set_safe_registers(struct radeon_device *rdev) |
||
699 | { |
||
700 | rdev->config.r300.reg_safe_bm = rs600_reg_safe_bm; |
||
701 | rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rs600_reg_safe_bm); |
||
702 | } |
||
703 | |||
704 | static void rs600_mc_program(struct radeon_device *rdev) |
||
705 | { |
||
706 | struct rv515_mc_save save; |
||
707 | |||
708 | /* Stops all mc clients */ |
||
709 | rv515_mc_stop(rdev, &save); |
||
710 | |||
711 | /* Wait for mc idle */ |
||
712 | if (rs600_mc_wait_for_idle(rdev)) |
||
713 | dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); |
||
714 | |||
715 | /* FIXME: What does AGP means for such chipset ? */ |
||
716 | WREG32_MC(R_000005_MC_AGP_LOCATION, 0x0FFFFFFF); |
||
717 | WREG32_MC(R_000006_AGP_BASE, 0); |
||
718 | WREG32_MC(R_000007_AGP_BASE_2, 0); |
||
719 | /* Program MC */ |
||
720 | WREG32_MC(R_000004_MC_FB_LOCATION, |
||
721 | S_000004_MC_FB_START(rdev->mc.vram_start >> 16) | |
||
722 | S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16)); |
||
723 | WREG32(R_000134_HDP_FB_LOCATION, |
||
724 | S_000134_HDP_FB_START(rdev->mc.vram_start >> 16)); |
||
725 | |||
726 | rv515_mc_resume(rdev, &save); |
||
727 | } |
||
728 | |||
729 | static int rs600_startup(struct radeon_device *rdev) |
||
730 | { |
||
731 | int r; |
||
732 | |||
733 | rs600_mc_program(rdev); |
||
734 | /* Resume clock */ |
||
735 | rv515_clock_startup(rdev); |
||
736 | /* Initialize GPU configuration (# pipes, ...) */ |
||
737 | rs600_gpu_init(rdev); |
||
738 | /* Initialize GART (initialize after TTM so we can allocate |
||
739 | * memory through TTM but finalize after TTM) */ |
||
740 | r = rs600_gart_enable(rdev); |
||
741 | if (r) |
||
1128 | serge | 742 | return r; |
2005 | serge | 743 | |
744 | /* allocate wb buffer */ |
||
745 | r = radeon_wb_init(rdev); |
||
746 | if (r) |
||
747 | return r; |
||
748 | |||
3192 | Serge | 749 | r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); |
750 | if (r) { |
||
751 | dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); |
||
752 | return r; |
||
753 | } |
||
754 | |||
1221 | serge | 755 | /* Enable IRQ */ |
3764 | Serge | 756 | if (!rdev->irq.installed) { |
757 | r = radeon_irq_kms_init(rdev); |
||
758 | if (r) |
||
759 | return r; |
||
760 | } |
||
761 | |||
2005 | serge | 762 | rs600_irq_set(rdev); |
1403 | serge | 763 | rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); |
1221 | serge | 764 | /* 1M ring buffer */ |
1413 | serge | 765 | r = r100_cp_init(rdev, 1024 * 1024); |
766 | if (r) { |
||
1963 | serge | 767 | dev_err(rdev->dev, "failed initializing CP (%d).\n", r); |
1413 | serge | 768 | return r; |
769 | } |
||
2997 | Serge | 770 | |
771 | r = radeon_ib_pool_init(rdev); |
||
2005 | serge | 772 | if (r) { |
2997 | Serge | 773 | dev_err(rdev->dev, "IB initialization failed (%d).\n", r); |
2005 | serge | 774 | return r; |
775 | } |
||
2997 | Serge | 776 | |
777 | |||
1221 | serge | 778 | return 0; |
1128 | serge | 779 | } |
780 | |||
1221 | serge | 781 | |
782 | |||
783 | int rs600_init(struct radeon_device *rdev) |
||
1128 | serge | 784 | { |
1221 | serge | 785 | int r; |
786 | |||
787 | /* Disable VGA */ |
||
788 | rv515_vga_render_disable(rdev); |
||
789 | /* Initialize scratch registers */ |
||
790 | radeon_scratch_init(rdev); |
||
791 | /* Initialize surface registers */ |
||
792 | radeon_surface_init(rdev); |
||
1963 | serge | 793 | /* restore some register to sane defaults */ |
794 | r100_restore_sanity(rdev); |
||
1221 | serge | 795 | /* BIOS */ |
796 | if (!radeon_get_bios(rdev)) { |
||
797 | if (ASIC_IS_AVIVO(rdev)) |
||
798 | return -EINVAL; |
||
799 | } |
||
800 | if (rdev->is_atom_bios) { |
||
801 | r = radeon_atombios_init(rdev); |
||
802 | if (r) |
||
803 | return r; |
||
804 | } else { |
||
805 | dev_err(rdev->dev, "Expecting atombios for RS600 GPU\n"); |
||
806 | return -EINVAL; |
||
807 | } |
||
808 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ |
||
1963 | serge | 809 | if (radeon_asic_reset(rdev)) { |
1221 | serge | 810 | dev_warn(rdev->dev, |
811 | "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", |
||
812 | RREG32(R_000E40_RBBM_STATUS), |
||
813 | RREG32(R_0007C0_CP_STAT)); |
||
814 | } |
||
815 | /* check if cards are posted or not */ |
||
1321 | serge | 816 | if (radeon_boot_test_post_card(rdev) == false) |
817 | return -EINVAL; |
||
818 | |||
1221 | serge | 819 | /* Initialize clocks */ |
820 | radeon_get_clock_info(rdev->ddev); |
||
1430 | serge | 821 | /* initialize memory controller */ |
822 | rs600_mc_init(rdev); |
||
1221 | serge | 823 | rs600_debugfs(rdev); |
824 | /* Fence driver */ |
||
2005 | serge | 825 | r = radeon_fence_driver_init(rdev); |
826 | if (r) |
||
827 | return r; |
||
1221 | serge | 828 | /* Memory manager */ |
1321 | serge | 829 | r = radeon_bo_init(rdev); |
1221 | serge | 830 | if (r) |
831 | return r; |
||
832 | r = rs600_gart_init(rdev); |
||
833 | if (r) |
||
834 | return r; |
||
835 | rs600_set_safe_registers(rdev); |
||
2997 | Serge | 836 | |
1221 | serge | 837 | rdev->accel_working = true; |
838 | r = rs600_startup(rdev); |
||
839 | if (r) { |
||
840 | /* Somethings want wront with the accel init stop accel */ |
||
841 | dev_err(rdev->dev, "Disabling GPU acceleration\n"); |
||
842 | // r100_cp_fini(rdev); |
||
843 | // r100_wb_fini(rdev); |
||
844 | // r100_ib_fini(rdev); |
||
845 | rs600_gart_fini(rdev); |
||
846 | // radeon_irq_kms_fini(rdev); |
||
847 | rdev->accel_working = false; |
||
848 | } |
||
849 | return 0; |
||
1128 | serge | 850 | }><>>>><>><>><>><>><>>>><>><>> |