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1128 serge 1
/*
2
 * Copyright 2008 Advanced Micro Devices, Inc.
3
 * Copyright 2008 Red Hat Inc.
4
 * Copyright 2009 Jerome Glisse.
5
 *
6
 * Permission is hereby granted, free of charge, to any person obtaining a
7
 * copy of this software and associated documentation files (the "Software"),
8
 * to deal in the Software without restriction, including without limitation
9
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10
 * and/or sell copies of the Software, and to permit persons to whom the
11
 * Software is furnished to do so, subject to the following conditions:
12
 *
13
 * The above copyright notice and this permission notice shall be included in
14
 * all copies or substantial portions of the Software.
15
 *
16
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22
 * OTHER DEALINGS IN THE SOFTWARE.
23
 *
24
 * Authors: Dave Airlie
25
 *          Alex Deucher
26
 *          Jerome Glisse
27
 */
1179 serge 28
#include 
1986 serge 29
#include 
1179 serge 30
#include 
1128 serge 31
#include "radeon.h"
1963 serge 32
#include "radeon_asic.h"
1221 serge 33
#include "rs400d.h"
1128 serge 34
 
1221 serge 35
/* This files gather functions specifics to : rs400,rs480 */
36
static int rs400_debugfs_pcie_gart_info_init(struct radeon_device *rdev);
1128 serge 37
 
38
void rs400_gart_adjust_size(struct radeon_device *rdev)
39
{
40
	/* Check gart size */
41
	switch (rdev->mc.gtt_size/(1024*1024)) {
42
	case 32:
43
	case 64:
44
	case 128:
45
	case 256:
46
	case 512:
47
	case 1024:
48
	case 2048:
49
		break;
50
	default:
51
		DRM_ERROR("Unable to use IGP GART size %uM\n",
1179 serge 52
			  (unsigned)(rdev->mc.gtt_size >> 20));
1128 serge 53
		DRM_ERROR("Valid GART size for IGP are 32M,64M,128M,256M,512M,1G,2G\n");
54
		DRM_ERROR("Forcing to 32M GART size\n");
55
		rdev->mc.gtt_size = 32 * 1024 * 1024;
56
		return;
57
	}
58
}
59
 
60
void rs400_gart_tlb_flush(struct radeon_device *rdev)
61
{
62
	uint32_t tmp;
63
	unsigned int timeout = rdev->usec_timeout;
64
 
65
	WREG32_MC(RS480_GART_CACHE_CNTRL, RS480_GART_CACHE_INVALIDATE);
66
	do {
67
		tmp = RREG32_MC(RS480_GART_CACHE_CNTRL);
68
		if ((tmp & RS480_GART_CACHE_INVALIDATE) == 0)
69
			break;
70
		DRM_UDELAY(1);
71
		timeout--;
72
	} while (timeout > 0);
73
	WREG32_MC(RS480_GART_CACHE_CNTRL, 0);
74
}
75
 
1179 serge 76
int rs400_gart_init(struct radeon_device *rdev)
1128 serge 77
{
78
	int r;
79
 
2997 Serge 80
	if (rdev->gart.ptr) {
1963 serge 81
		WARN(1, "RS400 GART already initialized\n");
1179 serge 82
		return 0;
83
	}
84
	/* Check gart size */
85
	switch(rdev->mc.gtt_size / (1024 * 1024)) {
86
	case 32:
87
	case 64:
88
	case 128:
89
	case 256:
90
	case 512:
91
	case 1024:
92
	case 2048:
93
		break;
94
	default:
95
		return -EINVAL;
96
	}
1128 serge 97
	/* Initialize common gart structure */
98
	r = radeon_gart_init(rdev);
1179 serge 99
	if (r)
1128 serge 100
		return r;
1179 serge 101
	if (rs400_debugfs_pcie_gart_info_init(rdev))
1128 serge 102
		DRM_ERROR("Failed to register debugfs file for RS400 GART !\n");
1179 serge 103
	rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
104
	return radeon_gart_table_ram_alloc(rdev);
105
}
1128 serge 106
 
1179 serge 107
int rs400_gart_enable(struct radeon_device *rdev)
108
{
109
	uint32_t size_reg;
110
	uint32_t tmp;
111
 
1430 serge 112
	radeon_gart_restore(rdev);
1128 serge 113
	tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH);
114
	tmp |= RS690_DIS_OUT_OF_PCI_GART_ACCESS;
115
	WREG32_MC(RS690_AIC_CTRL_SCRATCH, tmp);
116
	/* Check gart size */
117
	switch(rdev->mc.gtt_size / (1024 * 1024)) {
118
	case 32:
119
		size_reg = RS480_VA_SIZE_32MB;
120
		break;
121
	case 64:
122
		size_reg = RS480_VA_SIZE_64MB;
123
		break;
124
	case 128:
125
		size_reg = RS480_VA_SIZE_128MB;
126
		break;
127
	case 256:
128
		size_reg = RS480_VA_SIZE_256MB;
129
		break;
130
	case 512:
131
		size_reg = RS480_VA_SIZE_512MB;
132
		break;
133
	case 1024:
134
		size_reg = RS480_VA_SIZE_1GB;
135
		break;
136
	case 2048:
137
		size_reg = RS480_VA_SIZE_2GB;
138
		break;
139
	default:
140
		return -EINVAL;
141
	}
142
	/* It should be fine to program it to max value */
143
	if (rdev->family == CHIP_RS690 || (rdev->family == CHIP_RS740)) {
144
		WREG32_MC(RS690_MCCFG_AGP_BASE, 0xFFFFFFFF);
145
		WREG32_MC(RS690_MCCFG_AGP_BASE_2, 0);
146
	} else {
147
		WREG32(RADEON_AGP_BASE, 0xFFFFFFFF);
148
		WREG32(RS480_AGP_BASE_2, 0);
149
	}
1430 serge 150
	tmp = REG_SET(RS690_MC_AGP_TOP, rdev->mc.gtt_end >> 16);
151
	tmp |= REG_SET(RS690_MC_AGP_START, rdev->mc.gtt_start >> 16);
1128 serge 152
	if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) {
153
		WREG32_MC(RS690_MCCFG_AGP_LOCATION, tmp);
154
		tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
155
		WREG32(RADEON_BUS_CNTL, tmp);
156
	} else {
157
		WREG32(RADEON_MC_AGP_LOCATION, tmp);
158
		tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
159
		WREG32(RADEON_BUS_CNTL, tmp);
160
	}
161
	/* Table should be in 32bits address space so ignore bits above. */
1179 serge 162
	tmp = (u32)rdev->gart.table_addr & 0xfffff000;
163
	tmp |= (upper_32_bits(rdev->gart.table_addr) & 0xff) << 4;
164
 
1128 serge 165
	WREG32_MC(RS480_GART_BASE, tmp);
166
	/* TODO: more tweaking here */
167
	WREG32_MC(RS480_GART_FEATURE_ID,
168
		  (RS480_TLB_ENABLE |
169
		   RS480_GTW_LAC_EN | RS480_1LEVEL_GART));
170
	/* Disable snooping */
171
	WREG32_MC(RS480_AGP_MODE_CNTL,
172
		  (1 << RS480_REQ_TYPE_SNOOP_SHIFT) | RS480_REQ_TYPE_SNOOP_DIS);
173
	/* Disable AGP mode */
174
	/* FIXME: according to doc we should set HIDE_MMCFG_BAR=0,
175
	 * AGPMODE30=0 & AGP30ENHANCED=0 in NB_CNTL */
176
	if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) {
177
		WREG32_MC(RS480_MC_MISC_CNTL,
178
			  (RS480_GART_INDEX_REG_EN | RS690_BLOCK_GFX_D3_EN));
179
	} else {
180
		WREG32_MC(RS480_MC_MISC_CNTL, RS480_GART_INDEX_REG_EN);
181
	}
182
	/* Enable gart */
183
	WREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN | size_reg));
184
	rs400_gart_tlb_flush(rdev);
2997 Serge 185
	DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
186
		 (unsigned)(rdev->mc.gtt_size >> 20),
187
		 (unsigned long long)rdev->gart.table_addr);
1128 serge 188
	rdev->gart.ready = true;
189
	return 0;
190
}
191
 
192
void rs400_gart_disable(struct radeon_device *rdev)
193
{
194
	uint32_t tmp;
195
 
196
	tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH);
197
	tmp |= RS690_DIS_OUT_OF_PCI_GART_ACCESS;
198
	WREG32_MC(RS690_AIC_CTRL_SCRATCH, tmp);
199
	WREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE, 0);
200
}
201
 
1179 serge 202
void rs400_gart_fini(struct radeon_device *rdev)
203
{
1963 serge 204
	radeon_gart_fini(rdev);
1179 serge 205
	rs400_gart_disable(rdev);
206
	radeon_gart_table_ram_free(rdev);
207
}
208
 
1963 serge 209
#define RS400_PTE_WRITEABLE (1 << 2)
210
#define RS400_PTE_READABLE  (1 << 3)
211
 
1128 serge 212
int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
213
{
1179 serge 214
	uint32_t entry;
2997 Serge 215
	u32 *gtt = rdev->gart.ptr;
1179 serge 216
 
1128 serge 217
	if (i < 0 || i > rdev->gart.num_gpu_pages) {
218
		return -EINVAL;
219
	}
1179 serge 220
 
221
	entry = (lower_32_bits(addr) & PAGE_MASK) |
222
		((upper_32_bits(addr) & 0xff) << 4) |
1963 serge 223
		RS400_PTE_WRITEABLE | RS400_PTE_READABLE;
1179 serge 224
	entry = cpu_to_le32(entry);
2997 Serge 225
	gtt[i] = entry;
1128 serge 226
	return 0;
227
}
228
 
1404 serge 229
int rs400_mc_wait_for_idle(struct radeon_device *rdev)
230
{
231
	unsigned i;
232
	uint32_t tmp;
233
 
234
	for (i = 0; i < rdev->usec_timeout; i++) {
235
		/* read MC_STATUS */
1963 serge 236
		tmp = RREG32(RADEON_MC_STATUS);
237
		if (tmp & RADEON_MC_IDLE) {
1404 serge 238
			return 0;
239
		}
240
		DRM_UDELAY(1);
241
	}
242
	return -1;
243
}
244
 
2997 Serge 245
static void rs400_gpu_init(struct radeon_device *rdev)
1128 serge 246
{
247
	/* FIXME: is this correct ? */
248
	r420_pipes_init(rdev);
1404 serge 249
	if (rs400_mc_wait_for_idle(rdev)) {
250
		printk(KERN_WARNING "rs400: Failed to wait MC idle while "
1963 serge 251
		       "programming pipes. Bad things might happen. %08x\n", RREG32(RADEON_MC_STATUS));
1128 serge 252
	}
253
}
254
 
2997 Serge 255
static void rs400_mc_init(struct radeon_device *rdev)
1128 serge 256
{
1430 serge 257
	u64 base;
258
 
1128 serge 259
	rs400_gart_adjust_size(rdev);
1430 serge 260
	rdev->mc.igp_sideport_enabled = radeon_combios_sideport_present(rdev);
1128 serge 261
	/* DDR for all card after R300 & IGP */
262
	rdev->mc.vram_is_ddr = true;
263
	rdev->mc.vram_width = 128;
1179 serge 264
	r100_vram_init_sizes(rdev);
1430 serge 265
	base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
266
	radeon_vram_location(rdev, &rdev->mc, base);
1963 serge 267
	rdev->mc.gtt_base_align = rdev->mc.gtt_size - 1;
1430 serge 268
	radeon_gtt_location(rdev, &rdev->mc);
1963 serge 269
	radeon_update_bandwidth_info(rdev);
1128 serge 270
}
271
 
272
uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg)
273
{
274
	uint32_t r;
275
 
276
	WREG32(RS480_NB_MC_INDEX, reg & 0xff);
277
	r = RREG32(RS480_NB_MC_DATA);
278
	WREG32(RS480_NB_MC_INDEX, 0xff);
279
	return r;
280
}
281
 
282
void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
283
{
284
	WREG32(RS480_NB_MC_INDEX, ((reg) & 0xff) | RS480_NB_MC_IND_WR_EN);
285
	WREG32(RS480_NB_MC_DATA, (v));
286
	WREG32(RS480_NB_MC_INDEX, 0xff);
287
}
288
 
289
#if defined(CONFIG_DEBUG_FS)
290
static int rs400_debugfs_gart_info(struct seq_file *m, void *data)
291
{
292
	struct drm_info_node *node = (struct drm_info_node *) m->private;
293
	struct drm_device *dev = node->minor->dev;
294
	struct radeon_device *rdev = dev->dev_private;
295
	uint32_t tmp;
296
 
297
	tmp = RREG32(RADEON_HOST_PATH_CNTL);
298
	seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
299
	tmp = RREG32(RADEON_BUS_CNTL);
300
	seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
301
	tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH);
302
	seq_printf(m, "AIC_CTRL_SCRATCH 0x%08x\n", tmp);
303
	if (rdev->family == CHIP_RS690 || (rdev->family == CHIP_RS740)) {
304
		tmp = RREG32_MC(RS690_MCCFG_AGP_BASE);
305
		seq_printf(m, "MCCFG_AGP_BASE 0x%08x\n", tmp);
306
		tmp = RREG32_MC(RS690_MCCFG_AGP_BASE_2);
307
		seq_printf(m, "MCCFG_AGP_BASE_2 0x%08x\n", tmp);
308
		tmp = RREG32_MC(RS690_MCCFG_AGP_LOCATION);
309
		seq_printf(m, "MCCFG_AGP_LOCATION 0x%08x\n", tmp);
1963 serge 310
		tmp = RREG32_MC(RS690_MCCFG_FB_LOCATION);
1128 serge 311
		seq_printf(m, "MCCFG_FB_LOCATION 0x%08x\n", tmp);
1963 serge 312
		tmp = RREG32(RS690_HDP_FB_LOCATION);
1128 serge 313
		seq_printf(m, "HDP_FB_LOCATION 0x%08x\n", tmp);
314
	} else {
315
		tmp = RREG32(RADEON_AGP_BASE);
316
		seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
317
		tmp = RREG32(RS480_AGP_BASE_2);
318
		seq_printf(m, "AGP_BASE_2 0x%08x\n", tmp);
319
		tmp = RREG32(RADEON_MC_AGP_LOCATION);
320
		seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
321
	}
322
	tmp = RREG32_MC(RS480_GART_BASE);
323
	seq_printf(m, "GART_BASE 0x%08x\n", tmp);
324
	tmp = RREG32_MC(RS480_GART_FEATURE_ID);
325
	seq_printf(m, "GART_FEATURE_ID 0x%08x\n", tmp);
326
	tmp = RREG32_MC(RS480_AGP_MODE_CNTL);
327
	seq_printf(m, "AGP_MODE_CONTROL 0x%08x\n", tmp);
328
	tmp = RREG32_MC(RS480_MC_MISC_CNTL);
329
	seq_printf(m, "MC_MISC_CNTL 0x%08x\n", tmp);
330
	tmp = RREG32_MC(0x5F);
331
	seq_printf(m, "MC_MISC_UMA_CNTL 0x%08x\n", tmp);
332
	tmp = RREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE);
333
	seq_printf(m, "AGP_ADDRESS_SPACE_SIZE 0x%08x\n", tmp);
334
	tmp = RREG32_MC(RS480_GART_CACHE_CNTRL);
335
	seq_printf(m, "GART_CACHE_CNTRL 0x%08x\n", tmp);
336
	tmp = RREG32_MC(0x3B);
337
	seq_printf(m, "MC_GART_ERROR_ADDRESS 0x%08x\n", tmp);
338
	tmp = RREG32_MC(0x3C);
339
	seq_printf(m, "MC_GART_ERROR_ADDRESS_HI 0x%08x\n", tmp);
340
	tmp = RREG32_MC(0x30);
341
	seq_printf(m, "GART_ERROR_0 0x%08x\n", tmp);
342
	tmp = RREG32_MC(0x31);
343
	seq_printf(m, "GART_ERROR_1 0x%08x\n", tmp);
344
	tmp = RREG32_MC(0x32);
345
	seq_printf(m, "GART_ERROR_2 0x%08x\n", tmp);
346
	tmp = RREG32_MC(0x33);
347
	seq_printf(m, "GART_ERROR_3 0x%08x\n", tmp);
348
	tmp = RREG32_MC(0x34);
349
	seq_printf(m, "GART_ERROR_4 0x%08x\n", tmp);
350
	tmp = RREG32_MC(0x35);
351
	seq_printf(m, "GART_ERROR_5 0x%08x\n", tmp);
352
	tmp = RREG32_MC(0x36);
353
	seq_printf(m, "GART_ERROR_6 0x%08x\n", tmp);
354
	tmp = RREG32_MC(0x37);
355
	seq_printf(m, "GART_ERROR_7 0x%08x\n", tmp);
356
	return 0;
357
}
358
 
359
static struct drm_info_list rs400_gart_info_list[] = {
360
	{"rs400_gart_info", rs400_debugfs_gart_info, 0, NULL},
361
};
362
#endif
363
 
1221 serge 364
static int rs400_debugfs_pcie_gart_info_init(struct radeon_device *rdev)
1128 serge 365
{
366
#if defined(CONFIG_DEBUG_FS)
367
	return radeon_debugfs_add_files(rdev, rs400_gart_info_list, 1);
368
#else
369
	return 0;
370
#endif
371
}
1221 serge 372
 
2997 Serge 373
static void rs400_mc_program(struct radeon_device *rdev)
1221 serge 374
{
375
	struct r100_mc_save save;
376
 
377
	/* Stops all mc clients */
378
	r100_mc_stop(rdev, &save);
379
 
380
	/* Wait for mc idle */
1404 serge 381
	if (rs400_mc_wait_for_idle(rdev))
382
		dev_warn(rdev->dev, "rs400: Wait MC idle timeout before updating MC.\n");
1221 serge 383
	WREG32(R_000148_MC_FB_LOCATION,
384
		S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
385
		S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
386
 
387
	r100_mc_resume(rdev, &save);
388
}
389
 
390
static int rs400_startup(struct radeon_device *rdev)
391
{
392
	int r;
393
 
1963 serge 394
	r100_set_common_regs(rdev);
395
 
1221 serge 396
	rs400_mc_program(rdev);
397
	/* Resume clock */
398
	r300_clock_startup(rdev);
399
	/* Initialize GPU configuration (# pipes, ...) */
400
	rs400_gpu_init(rdev);
1321 serge 401
	r100_enable_bm(rdev);
1221 serge 402
	/* Initialize GART (initialize after TTM so we can allocate
403
	 * memory through TTM but finalize after TTM) */
404
	r = rs400_gart_enable(rdev);
405
	if (r)
406
		return r;
2005 serge 407
 
408
	/* allocate wb buffer */
409
	r = radeon_wb_init(rdev);
410
	if (r)
411
		return r;
412
 
3120 serge 413
	r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
414
	if (r) {
415
		dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
416
		return r;
417
	}
418
 
1221 serge 419
	/* Enable IRQ */
2005 serge 420
	r100_irq_set(rdev);
1403 serge 421
	rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
1221 serge 422
	/* 1M ring buffer */
1413 serge 423
   r = r100_cp_init(rdev, 1024 * 1024);
424
   if (r) {
1963 serge 425
		dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
1413 serge 426
       return r;
427
   }
2997 Serge 428
 
429
	r = radeon_ib_pool_init(rdev);
2005 serge 430
	if (r) {
2997 Serge 431
		dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
2005 serge 432
		return r;
433
	}
2997 Serge 434
 
1221 serge 435
	return 0;
436
}
437
 
438
 
439
 
440
 
441
int rs400_init(struct radeon_device *rdev)
442
{
443
	int r;
444
 
445
	/* Disable VGA */
446
	r100_vga_render_disable(rdev);
447
	/* Initialize scratch registers */
448
	radeon_scratch_init(rdev);
449
	/* Initialize surface registers */
450
	radeon_surface_init(rdev);
451
	/* TODO: disable VGA need to use VGA request */
1963 serge 452
	/* restore some register to sane defaults */
453
	r100_restore_sanity(rdev);
1221 serge 454
	/* BIOS*/
455
	if (!radeon_get_bios(rdev)) {
456
		if (ASIC_IS_AVIVO(rdev))
457
			return -EINVAL;
458
	}
459
	if (rdev->is_atom_bios) {
460
		dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
461
		return -EINVAL;
462
	} else {
463
		r = radeon_combios_init(rdev);
464
		if (r)
465
			return r;
466
	}
467
	/* Reset gpu before posting otherwise ATOM will enter infinite loop */
1963 serge 468
	if (radeon_asic_reset(rdev)) {
1221 serge 469
		dev_warn(rdev->dev,
470
			"GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
471
			RREG32(R_000E40_RBBM_STATUS),
472
			RREG32(R_0007C0_CP_STAT));
473
	}
474
	/* check if cards are posted or not */
1321 serge 475
	if (radeon_boot_test_post_card(rdev) == false)
476
		return -EINVAL;
477
 
1221 serge 478
	/* Initialize clocks */
479
	radeon_get_clock_info(rdev->ddev);
1430 serge 480
	/* initialize memory controller */
481
	rs400_mc_init(rdev);
1221 serge 482
	/* Fence driver */
2005 serge 483
	r = radeon_fence_driver_init(rdev);
484
	if (r)
485
		return r;
486
	r = radeon_irq_kms_init(rdev);
487
	if (r)
488
		return r;
1221 serge 489
	/* Memory manager */
1321 serge 490
	r = radeon_bo_init(rdev);
1221 serge 491
	if (r)
492
		return r;
493
	r = rs400_gart_init(rdev);
494
	if (r)
495
		return r;
496
	r300_set_reg_safe(rdev);
2997 Serge 497
 
1221 serge 498
	rdev->accel_working = true;
499
	r = rs400_startup(rdev);
500
	if (r) {
501
		/* Somethings want wront with the accel init stop accel */
502
		dev_err(rdev->dev, "Disabling GPU acceleration\n");
503
//		r100_cp_fini(rdev);
504
//		r100_wb_fini(rdev);
505
//		r100_ib_fini(rdev);
506
		rs400_gart_fini(rdev);
507
//		radeon_irq_kms_fini(rdev);
508
		rdev->accel_working = false;
509
	}
510
	return 0;
511
}