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Rev | Author | Line No. | Line |
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1246 | serge | 1 | |
2 | #include |
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5078 | serge | 3 | #include "radeon.h" |
1246 | serge | 4 | #include "radeon_object.h" |
5 | #include "drm_fb_helper.h" |
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3120 | serge | 6 | #include "hmm.h" |
7 | #include "bitmap.h" |
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8 | #include |
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5354 | serge | 9 | |
1246 | serge | 10 | |
5078 | serge | 11 | extern struct drm_gem_object *main_fb_obj; |
12 | |||
1246 | serge | 13 | |
5078 | serge | 14 | |
1986 | serge | 15 | |
1246 | serge | 16 | static void __stdcall move_cursor_kms(cursor_t *cursor, int x, int y); |
17 | |||
18 | |||
19 | |||
20 | |||
1313 | serge | 21 | |
22 | |||
1246 | serge | 23 | { |
24 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
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25 | struct radeon_device *rdev = crtc->dev->dev_private; |
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26 | |||
27 | |||
2004 | serge | 28 | WREG32(RADEON_MM_INDEX, EVERGREEN_CUR_CONTROL + radeon_crtc->crtc_offset); |
29 | WREG32(RADEON_MM_DATA, EVERGREEN_CURSOR_EN | |
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30 | EVERGREEN_CURSOR_MODE(EVERGREEN_CURSOR_24_8_PRE_MULT)); |
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31 | } else if (ASIC_IS_AVIVO(rdev)) { |
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32 | WREG32(RADEON_MM_INDEX, AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset); |
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1246 | serge | 33 | WREG32(RADEON_MM_DATA, AVIVO_D1CURSOR_EN | |
34 | (AVIVO_D1CURSOR_MODE_24BPP << AVIVO_D1CURSOR_MODE_SHIFT)); |
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35 | } else { |
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36 | switch (radeon_crtc->crtc_id) { |
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37 | case 0: |
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38 | WREG32(RADEON_MM_INDEX, RADEON_CRTC_GEN_CNTL); |
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39 | break; |
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40 | case 1: |
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41 | WREG32(RADEON_MM_INDEX, RADEON_CRTC2_GEN_CNTL); |
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42 | break; |
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43 | default: |
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44 | return; |
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45 | } |
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46 | |||
47 | |||
48 | (RADEON_CRTC_CUR_MODE_24BPP << RADEON_CRTC_CUR_MODE_SHIFT)), |
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49 | ~(RADEON_CRTC_CUR_EN | RADEON_CRTC_CUR_MODE_MASK)); |
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50 | } |
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51 | } |
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52 | |||
53 | |||
54 | { |
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55 | struct radeon_device *rdev = crtc->dev->dev_private; |
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56 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
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57 | uint32_t cur_lock; |
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58 | |||
59 | |||
2004 | serge | 60 | cur_lock = RREG32(EVERGREEN_CUR_UPDATE + radeon_crtc->crtc_offset); |
61 | if (lock) |
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62 | cur_lock |= EVERGREEN_CURSOR_UPDATE_LOCK; |
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63 | else |
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64 | cur_lock &= ~EVERGREEN_CURSOR_UPDATE_LOCK; |
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65 | WREG32(EVERGREEN_CUR_UPDATE + radeon_crtc->crtc_offset, cur_lock); |
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66 | } else if (ASIC_IS_AVIVO(rdev)) { |
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67 | cur_lock = RREG32(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset); |
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1246 | serge | 68 | if (lock) |
69 | cur_lock |= AVIVO_D1CURSOR_UPDATE_LOCK; |
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70 | else |
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71 | cur_lock &= ~AVIVO_D1CURSOR_UPDATE_LOCK; |
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72 | WREG32(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset, cur_lock); |
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73 | } else { |
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74 | cur_lock = RREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset); |
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75 | if (lock) |
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76 | cur_lock |= RADEON_CUR_LOCK; |
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77 | else |
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78 | cur_lock &= ~RADEON_CUR_LOCK; |
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79 | WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, cur_lock); |
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80 | } |
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81 | } |
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82 | |||
83 | |||
84 | { |
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85 | struct radeon_device *rdev; |
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86 | struct radeon_crtc *radeon_crtc; |
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87 | cursor_t *old; |
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88 | uint32_t gpu_addr; |
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89 | |||
90 | |||
5078 | serge | 91 | radeon_crtc = to_radeon_crtc(os_display->crtc); |
92 | |||
1246 | serge | 93 | |
5078 | serge | 94 | |
1246 | serge | 95 | |
5078 | serge | 96 | gpu_addr = radeon_bo_gpu_offset(cursor->cobj); |
5354 | serge | 97 | |
1246 | serge | 98 | |
2004 | serge | 99 | WREG32(EVERGREEN_CUR_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, |
100 | 0); |
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101 | WREG32(EVERGREEN_CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset, |
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102 | gpu_addr); |
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103 | } else if (ASIC_IS_AVIVO(rdev)) { |
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104 | if (rdev->family >= CHIP_RV770) |
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105 | WREG32(R700_D1CUR_SURFACE_ADDRESS_HIGH, 0); |
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106 | WREG32(AVIVO_D1CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset, gpu_addr); |
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1246 | serge | 107 | } |
2004 | serge | 108 | else { |
1246 | serge | 109 | radeon_crtc->legacy_cursor_offset = gpu_addr - rdev->mc.vram_start; |
1430 | serge | 110 | /* offset is from DISP(2)_BASE_ADDRESS */ |
1246 | serge | 111 | WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, radeon_crtc->legacy_cursor_offset); |
112 | } |
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113 | |||
114 | |||
115 | }; |
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116 | |||
117 | |||
118 | { |
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119 | struct radeon_device *rdev; |
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120 | rdev = (struct radeon_device *)os_display->ddev->dev_private; |
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5078 | serge | 121 | struct drm_crtc *crtc = os_display->crtc; |
122 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
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1246 | serge | 123 | |
124 | |||
125 | int hot_y = cursor->hot_y; |
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126 | int w = 32; |
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2004 | serge | 127 | |
1246 | serge | 128 | |
129 | |||
130 | |||
2004 | serge | 131 | WREG32(EVERGREEN_CUR_POSITION + radeon_crtc->crtc_offset, |
132 | (x << 16) | y); |
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133 | WREG32(EVERGREEN_CUR_HOT_SPOT + radeon_crtc->crtc_offset, |
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134 | (hot_x << 16) | hot_y); |
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135 | WREG32(EVERGREEN_CUR_SIZE + radeon_crtc->crtc_offset, |
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136 | ((w - 1) << 16) | 31); |
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137 | } else if (ASIC_IS_AVIVO(rdev)) { |
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138 | WREG32(AVIVO_D1CUR_POSITION + radeon_crtc->crtc_offset, |
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1246 | serge | 139 | (x << 16) | y); |
140 | WREG32(AVIVO_D1CUR_HOT_SPOT + radeon_crtc->crtc_offset, |
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141 | (hot_x << 16) | hot_y); |
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142 | WREG32(AVIVO_D1CUR_SIZE + radeon_crtc->crtc_offset, |
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143 | ((w - 1) << 16) | 31); |
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144 | } else { |
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145 | if (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN) |
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146 | y *= 2; |
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147 | |||
148 | |||
1404 | serge | 149 | int xorg =0, yorg=0; |
150 | |||
151 | |||
152 | y = y - hot_y; |
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153 | |||
154 | |||
155 | { |
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156 | xorg = -x + 1; |
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157 | x = 0; |
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158 | } |
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159 | |||
160 | |||
161 | { |
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162 | yorg = -hot_y + 1; |
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163 | y = 0; |
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164 | }; |
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165 | |||
166 | |||
167 | (RADEON_CUR_LOCK | (xorg << 16) | yorg )); |
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168 | WREG32(RADEON_CUR_HORZ_VERT_POSN, |
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169 | (RADEON_CUR_LOCK | (x << 16) | y)); |
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1246 | serge | 170 | |
171 | |||
5354 | serge | 172 | |
1404 | serge | 173 | |
1246 | serge | 174 | WREG32(RADEON_CUR_OFFSET, |
1404 | serge | 175 | (gpu_addr - rdev->mc.vram_start + (yorg * 256))); |
1430 | serge | 176 | } |
1246 | serge | 177 | radeon_lock_cursor_kms(crtc, false); |
178 | } |
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179 | |||
180 | |||
181 | { |
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182 | static char name[4]; |
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183 | |||
184 | |||
185 | name[1] = ((x[0] & 0x03) << 3) + ((x[1] & 0xE0) >> 5) + '@'; |
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186 | name[2] = (x[1] & 0x1F) + '@'; |
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187 | name[3] = 0; |
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188 | |||
189 | |||
190 | } |
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191 | |||
192 | |||
5078 | serge | 193 | struct drm_crtc *crtc, videomode_t *reqmode, bool strict) |
194 | { |
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1246 | serge | 195 | struct drm_display_mode *mode = NULL, *tmpmode; |
196 | struct drm_framebuffer *fb = NULL; |
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5078 | serge | 197 | struct drm_mode_set set; |
198 | const char *con_name; |
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199 | unsigned hdisplay, vdisplay; |
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200 | int ret; |
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201 | |||
1246 | serge | 202 | |
5078 | serge | 203 | |
1986 | serge | 204 | |
1246 | serge | 205 | { |
206 | if( (tmpmode->hdisplay == reqmode->width) && |
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5078 | serge | 207 | (tmpmode->vdisplay == reqmode->height) && |
208 | (drm_mode_vrefresh(tmpmode) == reqmode->freq) ) |
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1246 | serge | 209 | { |
210 | mode = tmpmode; |
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211 | goto do_set; |
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212 | } |
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213 | }; |
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5078 | serge | 214 | |
1246 | serge | 215 | |
216 | { |
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217 | list_for_each_entry(tmpmode, &connector->modes, head) |
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218 | { |
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219 | if( (tmpmode->hdisplay == reqmode->width) && |
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5078 | serge | 220 | (tmpmode->vdisplay == reqmode->height) ) |
221 | { |
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1246 | serge | 222 | mode = tmpmode; |
223 | goto do_set; |
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224 | } |
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225 | }; |
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5078 | serge | 226 | }; |
1246 | serge | 227 | |
228 | |||
5078 | serge | 229 | |
230 | |||
231 | |||
232 | |||
1246 | serge | 233 | |
234 | |||
5078 | serge | 235 | |
1246 | serge | 236 | |
5078 | serge | 237 | reqmode->width, reqmode->height, crtc->base.id, |
238 | con_name); |
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239 | |||
1246 | serge | 240 | |
5078 | serge | 241 | |
1246 | serge | 242 | |
5078 | serge | 243 | vdisplay = mode->vdisplay; |
244 | |||
1246 | serge | 245 | |
5078 | serge | 246 | swap(hdisplay, vdisplay); |
247 | |||
1246 | serge | 248 | |
5078 | serge | 249 | |
1246 | serge | 250 | |
5078 | serge | 251 | fb->height = reqmode->height; |
252 | |||
1246 | serge | 253 | |
5078 | serge | 254 | fb->pitches[1] = |
255 | fb->pitches[2] = |
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256 | fb->pitches[3] = radeon_align_pitch(dev->dev_private, reqmode->width, 32, false) * ((32 + 1) / 8); |
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257 | fb->bits_per_pixel = 32; |
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258 | fb->depth = 24; |
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259 | |||
1246 | serge | 260 | |
5078 | serge | 261 | os_display->crtc = crtc; |
262 | |||
1986 | serge | 263 | |
5078 | serge | 264 | set.x = 0; |
265 | set.y = 0; |
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266 | set.mode = mode; |
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267 | set.connectors = &connector; |
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268 | set.num_connectors = 1; |
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269 | set.fb = fb; |
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270 | |||
2997 | Serge | 271 | |
5078 | serge | 272 | |
1246 | serge | 273 | |
5078 | serge | 274 | |
1246 | serge | 275 | |
5078 | serge | 276 | radeon_show_cursor_kms(crtc); |
277 | |||
1246 | serge | 278 | |
5078 | serge | 279 | { |
280 | os_display->width = fb->width; |
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281 | os_display->height = fb->height; |
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282 | os_display->vrefresh = drm_mode_vrefresh(mode); |
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283 | |||
1246 | serge | 284 | |
5078 | serge | 285 | |
1246 | serge | 286 | |
5078 | serge | 287 | fb->width, fb->height, fb->pitches[0]); |
2997 | Serge | 288 | } |
1246 | serge | 289 | else |
5078 | serge | 290 | DRM_ERROR("failed to set mode %d_%d on crtc %p\n", |
291 | fb->width, fb->height, crtc); |
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292 | |||
1246 | serge | 293 | |
294 | } |
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5078 | serge | 295 | |
1246 | serge | 296 | |
297 | { |
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298 | struct drm_display_mode *mode; |
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299 | int count = 0; |
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300 | |||
301 | |||
302 | { |
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303 | count++; |
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304 | }; |
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305 | return count; |
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306 | }; |
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307 | |||
308 | |||
5078 | serge | 309 | { |
1246 | serge | 310 | struct drm_crtc *tmp_crtc; |
5078 | serge | 311 | int crtc_mask = 1; |
312 | |||
313 | |||
314 | { |
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315 | if (encoder->possible_crtcs & crtc_mask) |
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316 | { |
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317 | encoder->crtc = tmp_crtc; |
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318 | DRM_DEBUG_KMS("use CRTC %p ID %d\n", tmp_crtc, tmp_crtc->base.id); |
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319 | return tmp_crtc; |
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320 | }; |
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321 | crtc_mask <<= 1; |
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322 | }; |
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323 | return NULL; |
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324 | }; |
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325 | |||
326 | |||
327 | struct drm_crtc **boot_crtc) |
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328 | { |
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329 | struct drm_connector_helper_funcs *connector_funcs; |
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1963 | serge | 330 | struct drm_connector *connector; |
5078 | serge | 331 | struct drm_encoder *encoder; |
332 | struct drm_crtc *crtc; |
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333 | |||
1963 | serge | 334 | |
1246 | serge | 335 | { |
336 | if( connector->status != connector_status_connected) |
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337 | continue; |
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338 | |||
339 | |||
5078 | serge | 340 | |
1246 | serge | 341 | |
5078 | serge | 342 | { |
343 | connector_funcs = connector->helper_private; |
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344 | encoder = connector_funcs->best_encoder(connector); |
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345 | |||
1963 | serge | 346 | |
5078 | serge | 347 | { |
348 | DRM_DEBUG_KMS("CONNECTOR %x ID: %d no active encoders\n", |
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349 | connector, connector->base.id); |
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350 | continue; |
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351 | }; |
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352 | } |
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353 | |||
354 | |||
1246 | serge | 355 | if(crtc == NULL) |
5078 | serge | 356 | crtc = get_possible_crtc(dev, encoder); |
357 | |||
1963 | serge | 358 | |
5078 | serge | 359 | { |
360 | *boot_connector = connector; |
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361 | *boot_crtc = crtc; |
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362 | connector->encoder = encoder; |
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363 | DRM_DEBUG_KMS("CONNECTOR %p ID:%d status:%d ENCODER %p ID: %d CRTC %p ID:%d\n", |
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364 | connector, connector->base.id, connector->status, |
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365 | encoder, encoder->base.id, crtc, crtc->base.id ); |
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366 | return 0; |
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367 | } |
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368 | else |
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369 | DRM_DEBUG_KMS("No CRTC for encoder %d\n", encoder->base.id); |
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370 | |||
1246 | serge | 371 | |
372 | |||
373 | |||
5078 | serge | 374 | }; |
1246 | serge | 375 | |
376 | |||
5078 | serge | 377 | { |
378 | struct drm_display_mode *mode; |
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379 | |||
1986 | serge | 380 | |
5078 | serge | 381 | { |
382 | DRM_DEBUG_KMS("check mode w:%d h:%d %dHz\n", |
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383 | mode->hdisplay, mode->vdisplay, |
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384 | drm_mode_vrefresh(mode)); |
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385 | |||
1986 | serge | 386 | |
5078 | serge | 387 | os_display->height == mode->vdisplay && |
388 | drm_mode_vrefresh(mode) == 60) |
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389 | { |
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390 | usermode->width = os_display->width; |
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391 | usermode->height = os_display->height; |
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392 | usermode->freq = 60; |
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393 | return 1; |
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394 | } |
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395 | } |
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396 | return 0; |
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397 | } |
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398 | |||
399 | |||
400 | { |
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1246 | serge | 401 | struct drm_connector_helper_funcs *connector_funcs; |
2997 | Serge | 402 | struct drm_connector *connector = NULL; |
5078 | serge | 403 | struct drm_crtc *crtc = NULL; |
2997 | Serge | 404 | struct drm_framebuffer *fb; |
405 | |||
406 | |||
5271 | serge | 407 | u32 ifl; |
408 | int ret; |
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5078 | serge | 409 | |
1246 | serge | 410 | |
5078 | serge | 411 | |
1986 | serge | 412 | |
5078 | serge | 413 | if(ret) |
414 | { |
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2997 | Serge | 415 | DRM_DEBUG_KMS("No active connectors!\n"); |
5078 | serge | 416 | mutex_unlock(&dev->mode_config.mutex); |
417 | return -1; |
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2997 | Serge | 418 | }; |
419 | |||
420 | |||
421 | struct drm_display_mode *tmp, *native = NULL; |
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5078 | serge | 422 | struct radeon_device *rdev = dev->dev_private; |
423 | |||
2997 | Serge | 424 | |
425 | if (tmp->hdisplay > 16384 || |
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5078 | serge | 426 | tmp->vdisplay > 16384) |
427 | continue; |
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2997 | Serge | 428 | if (tmp->type & DRM_MODE_TYPE_PREFERRED) |
429 | { |
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430 | native = tmp; |
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431 | break; |
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432 | }; |
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433 | } |
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434 | |||
435 | |||
5078 | serge | 436 | { |
1246 | serge | 437 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(connector->encoder); |
5078 | serge | 438 | radeon_encoder->rmx_type = RMX_FULL; |
439 | radeon_encoder->native_mode = *native; |
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440 | }; |
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1246 | serge | 441 | } |
5078 | serge | 442 | |
1246 | serge | 443 | |
5078 | serge | 444 | mutex_lock(&dev->object_name_lock); |
445 | idr_preload(GFP_KERNEL); |
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446 | |||
1986 | serge | 447 | |
5078 | serge | 448 | ret = idr_alloc(&dev->object_name_idr, &main_fb_obj, 1, 0, GFP_NOWAIT); |
449 | |||
1986 | serge | 450 | |
5078 | serge | 451 | |
1986 | serge | 452 | |
5078 | serge | 453 | drm_gem_object_reference(main_fb_obj); |
454 | |||
1986 | serge | 455 | |
5078 | serge | 456 | } |
457 | |||
1986 | serge | 458 | |
5078 | serge | 459 | mutex_unlock(&dev->object_name_lock); |
460 | drm_gem_object_unreference(main_fb_obj); |
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461 | #endif |
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462 | |||
1986 | serge | 463 | |
5078 | serge | 464 | os_display->ddev = dev; |
465 | os_display->connector = connector; |
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466 | os_display->crtc = crtc; |
||
467 | |||
1986 | serge | 468 | |
5078 | serge | 469 | |
1986 | serge | 470 | |
2997 | Serge | 471 | { |
472 | list_for_each_entry(cursor, &os_display->cursors, list) |
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5078 | serge | 473 | { |
2997 | Serge | 474 | init_cursor(cursor); |
475 | }; |
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476 | |||
1986 | serge | 477 | |
5078 | serge | 478 | os_display->init_cursor = init_cursor; |
479 | os_display->select_cursor = select_cursor_kms; |
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480 | os_display->show_cursor = NULL; |
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481 | os_display->move_cursor = move_cursor_kms; |
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482 | os_display->restore_cursor = restore_cursor; |
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483 | os_display->disable_mouse = disable_mouse; |
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484 | select_cursor_kms(os_display->cursor); |
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485 | }; |
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1246 | serge | 486 | safe_sti(ifl); |
2997 | Serge | 487 | |
1246 | serge | 488 | |
1986 | serge | 489 | |
5078 | serge | 490 | // os_display->width, os_display->height, os_display->vrefresh); |
491 | // dbgprintf("user mode mode %d x %d x %d\n", |
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492 | // usermode->width, usermode->height, usermode->freq); |
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493 | |||
1268 | serge | 494 | |
5078 | serge | 495 | (usermode->height == 0)) |
496 | { |
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1246 | serge | 497 | if( !get_boot_mode(connector, usermode)) |
5078 | serge | 498 | { |
499 | struct drm_display_mode *mode; |
||
500 | |||
1246 | serge | 501 | |
5078 | serge | 502 | usermode->width = mode->hdisplay; |
503 | usermode->height = mode->vdisplay; |
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504 | usermode->freq = drm_mode_vrefresh(mode); |
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505 | }; |
||
506 | }; |
||
2997 | Serge | 507 | |
1246 | serge | 508 | |
5078 | serge | 509 | |
1268 | serge | 510 | |
5078 | serge | 511 | |
1246 | serge | 512 | |
5078 | serge | 513 | |
3120 | serge | 514 | |
5078 | serge | 515 | }; |
1246 | serge | 516 | |
517 | |||
5078 | serge | 518 | |
519 | { |
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1246 | serge | 520 | int err = -1; |
521 | |||
522 | |||
523 | { |
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524 | *count = os_display->supported_modes; |
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5078 | serge | 525 | err = 0; |
1246 | serge | 526 | } |
527 | else if( mode != NULL ) |
||
528 | { |
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529 | struct drm_display_mode *drmmode; |
||
530 | int i = 0; |
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531 | |||
532 | |||
5078 | serge | 533 | *count = os_display->supported_modes; |
534 | |||
1246 | serge | 535 | |
5078 | serge | 536 | { |
1246 | serge | 537 | if( i < *count) |
538 | { |
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539 | mode->width = drmmode->hdisplay; |
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5078 | serge | 540 | mode->height = drmmode->vdisplay; |
541 | mode->bpp = 32; |
||
1246 | serge | 542 | mode->freq = drm_mode_vrefresh(drmmode); |
543 | i++; |
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544 | mode++; |
||
545 | } |
||
546 | else break; |
||
547 | }; |
||
548 | *count = i; |
||
549 | err = 0; |
||
550 | }; |
||
551 | return err; |
||
552 | }; |
||
5078 | serge | 553 | |
1246 | serge | 554 | |
1403 | serge | 555 | { |
1246 | serge | 556 | int err = -1; |
557 | |||
558 | |||
559 | (mode->height != 0) && |
||
560 | (mode->freq != 0 ) && |
||
561 | ( (mode->width != os_display->width) || |
||
5078 | serge | 562 | (mode->height != os_display->height) || |
563 | (mode->freq != os_display->vrefresh) ) ) |
||
564 | { |
||
1246 | serge | 565 | return set_mode(os_display->ddev, os_display->connector, os_display->crtc, mode, true); |
5078 | serge | 566 | }; |
1246 | serge | 567 | |
568 | |||
5078 | serge | 569 | }; |
1246 | serge | 570 | |
571 | |||
1986 | serge | 572 | |
1404 | serge | 573 | |
1986 | serge | 574 | |
2997 | Serge | 575 | |
3764 | Serge | 576 | typedef struct |
3120 | serge | 577 | { |
578 | int left; |
||
579 | int top; |
||
580 | int right; |
||
581 | int bottom; |
||
582 | }rect_t; |
||
583 | |||
584 | |||
585 | struct drm_device *main_device; |
||
5078 | serge | 586 | |
3120 | serge | 587 | |
588 | |||
589 | |||
590 | |||
591 | |||
592 | { |
||
593 | u32_t addr; |
||
594 | |||
595 | |||
5078 | serge | 596 | addr+= sizeof(display_t); /* shoot me */ |
3120 | serge | 597 | return *(u32_t*)addr; |
598 | } |
||
599 | |||
600 | |||
601 | #include "r100d.h" |
||
602 | |||
603 | |||
3764 | Serge | 604 | # define PACKET3_TRANS_BITBLT 0x9C |
3124 | serge | 605 | # define R5XX_SRC_CMP_EQ_COLOR (4 << 0) |
606 | # define R5XX_SRC_CMP_NEQ_COLOR (5 << 0) |
||
607 | # define R5XX_CLR_CMP_SRC_SOURCE (1 << 24) |
||
608 | |||
3120 | serge | 609 | |
610 | int src_x, int src_y, u32 w, u32 h) |
||
611 | { |
||
612 | struct context *context; |
||
613 | |||
614 | |||
615 | rect_t winrc; |
||
616 | clip_t dst_clip; |
||
617 | clip_t src_clip; |
||
618 | u32_t width; |
||
619 | u32_t height; |
||
620 | |||
621 | |||
622 | u32_t offset; |
||
623 | u8 slot; |
||
624 | int n=0; |
||
625 | int ret; |
||
626 | |||
627 | |||
628 | return -1; |
||
629 | |||
630 | |||
631 | |||
632 | |||
633 | return -1; |
||
634 | |||
635 | |||
636 | if(unlikely(context == NULL)) |
||
637 | return -1; |
||
638 | |||
639 | |||
640 | { |
||
641 | static warn_count; |
||
642 | |||
643 | |||
644 | { |
||
645 | printf("left %d top %d right %d bottom %d\n", |
||
646 | winrc.left, winrc.top, winrc.right, winrc.bottom); |
||
647 | printf("bitmap width %d height %d\n", w, h); |
||
648 | warn_count++; |
||
649 | }; |
||
650 | }; |
||
651 | |||
652 | |||
653 | |||
654 | dst_clip.ymin = 0; |
||
655 | dst_clip.xmax = winrc.right-winrc.left; |
||
656 | dst_clip.ymax = winrc.bottom -winrc.top; |
||
657 | |||
658 | |||
659 | src_clip.ymin = 0; |
||
660 | src_clip.xmax = bitmap->width - 1; |
||
661 | src_clip.ymax = bitmap->height - 1; |
||
662 | |||
663 | |||
664 | height = h; |
||
665 | |||
666 | |||
667 | &src_clip, &src_x, &src_y, |
||
668 | &width, &height) ) |
||
669 | return 0; |
||
670 | |||
671 | |||
672 | dst_y+= winrc.top; |
||
673 | |||
674 | |||
675 | |||
676 | |||
677 | |||
678 | |||
679 | #if 0 |
||
3124 | serge | 680 | #else |
3120 | serge | 681 | u8* src_offset; |
682 | u8* dst_offset; |
||
683 | u32 color; |
||
3124 | serge | 684 | |
685 | |||
3120 | serge | 686 | |
687 | |||
688 | src_offset += (u32)bitmap->uaddr; |
||
689 | |||
690 | |||
5078 | serge | 691 | dst_offset+= get_display_map(); |
3120 | serge | 692 | |
693 | |||
694 | |||
695 | |||
696 | while( tmp_h--) |
||
697 | { |
||
698 | u32 tmp_w = width; |
||
3124 | serge | 699 | |
3120 | serge | 700 | |
3124 | serge | 701 | u8* tmp_dst = dst_offset; |
3764 | Serge | 702 | |
3120 | serge | 703 | |
704 | dst_offset+= os_display->width; |
||
5078 | serge | 705 | |
3120 | serge | 706 | |
707 | { |
||
708 | color = *tmp_src; |
||
3124 | serge | 709 | |
710 | |||
711 | color |= 0xFF000000; |
||
712 | else |
||
713 | color = 0x00; |
||
714 | |||
715 | |||
716 | tmp_src++; |
||
717 | tmp_dst++; |
||
3120 | serge | 718 | }; |
719 | }; |
||
720 | safe_sti(ifl); |
||
721 | #endif |
||
722 | } |
||
723 | |||
724 | |||
725 | static warn_count; |
||
726 | |||
727 | |||
728 | { |
||
729 | printf("blit width %d height %d\n", |
||
730 | width, height); |
||
731 | warn_count++; |
||
732 | }; |
||
733 | }; |
||
734 | |||
735 | |||
736 | |||
737 | // context->cmd_buffer&= 0xFFFFF000; |
||
738 | |||
739 | |||
740 | |||
741 | |||
742 | |||
743 | |||
744 | |||
745 | |||
746 | |||
747 | struct radeon_ib *ib = &context->ib; |
||
748 | |||
749 | |||
3124 | serge | 750 | ib->ptr[1] = 0xFFFFFFFF; |
751 | ib->ptr[2] = PACKET3(PACKET3_TRANS_BITBLT, 11); |
||
752 | ib->ptr[3] = RADEON_GMC_SRC_PITCH_OFFSET_CNTL | |
||
753 | RADEON_GMC_DST_PITCH_OFFSET_CNTL | |
||
3120 | serge | 754 | RADEON_GMC_SRC_CLIPPING | |
755 | RADEON_GMC_DST_CLIPPING | |
||
756 | RADEON_GMC_BRUSH_NONE | |
||
757 | (RADEON_COLOR_FORMAT_ARGB8888 << 8) | |
||
758 | RADEON_GMC_SRC_DATATYPE_COLOR | |
||
759 | RADEON_ROP3_S | |
||
760 | RADEON_DP_SRC_SOURCE_MEMORY | |
||
761 | RADEON_GMC_WR_MSK_DIS; |
||
762 | |||
763 | |||
3124 | serge | 764 | ib->ptr[5] = ((os_display->pitch/64) << 22) | (rdev->mc.vram_start >> 10); |
5078 | serge | 765 | ib->ptr[6] = (0x1fff) | (0x1fff << 16); |
3120 | serge | 766 | ib->ptr[7] = 0; |
3124 | serge | 767 | ib->ptr[8] = (0x1fff) | (0x1fff << 16); |
768 | |||
3120 | serge | 769 | |
3124 | serge | 770 | ib->ptr[10] = 0x00000000; |
771 | ib->ptr[11] = 0xFFFFFFFF; |
||
772 | |||
3120 | serge | 773 | |
3124 | serge | 774 | ib->ptr[13] = (dst_x << 16) | dst_y; |
775 | ib->ptr[14] = (width << 16) | height; |
||
776 | |||
777 | |||
3120 | serge | 778 | |
779 | |||
780 | |||
781 | |||
782 | if (ret) { |
||
783 | DRM_ERROR("radeon: failed to schedule ib (%d).\n", ret); |
||
784 | goto fail; |
||
785 | } |
||
786 | |||
787 | |||
788 | if (ret) { |
||
789 | DRM_ERROR("radeon: fence wait failed (%d).\n", ret); |
||
790 | goto fail; |
||
791 | } |
||
792 | |||
793 | |||
3192 | Serge | 794 | |
795 | |||
3120 | serge | 796 | return ret; |
797 | }; |
||
798 | |||
799 | |||
3764 | Serge | 800 |