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Rev | Author | Line No. | Line |
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1246 | serge | 1 | |
2 | #include |
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5078 | serge | 3 | #include |
1246 | serge | 4 | #include |
5 | #include "radeon.h" |
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6 | #include "radeon_object.h" |
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7 | #include "drm_fb_helper.h" |
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3120 | serge | 8 | #include "hmm.h" |
9 | #include "bitmap.h" |
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10 | #include "display.h" |
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1246 | serge | 11 | |
12 | |||
5078 | serge | 13 | extern struct drm_gem_object *main_fb_obj; |
14 | |||
1246 | serge | 15 | |
5078 | serge | 16 | |
1986 | serge | 17 | |
1246 | serge | 18 | static void __stdcall move_cursor_kms(cursor_t *cursor, int x, int y); |
19 | |||
20 | |||
21 | |||
22 | |||
1313 | serge | 23 | |
24 | |||
1246 | serge | 25 | { |
26 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
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27 | struct radeon_device *rdev = crtc->dev->dev_private; |
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28 | |||
29 | |||
2004 | serge | 30 | WREG32(RADEON_MM_INDEX, EVERGREEN_CUR_CONTROL + radeon_crtc->crtc_offset); |
31 | WREG32(RADEON_MM_DATA, EVERGREEN_CURSOR_EN | |
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32 | EVERGREEN_CURSOR_MODE(EVERGREEN_CURSOR_24_8_PRE_MULT)); |
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33 | } else if (ASIC_IS_AVIVO(rdev)) { |
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34 | WREG32(RADEON_MM_INDEX, AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset); |
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1246 | serge | 35 | WREG32(RADEON_MM_DATA, AVIVO_D1CURSOR_EN | |
36 | (AVIVO_D1CURSOR_MODE_24BPP << AVIVO_D1CURSOR_MODE_SHIFT)); |
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37 | } else { |
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38 | switch (radeon_crtc->crtc_id) { |
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39 | case 0: |
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40 | WREG32(RADEON_MM_INDEX, RADEON_CRTC_GEN_CNTL); |
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41 | break; |
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42 | case 1: |
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43 | WREG32(RADEON_MM_INDEX, RADEON_CRTC2_GEN_CNTL); |
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44 | break; |
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45 | default: |
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46 | return; |
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47 | } |
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48 | |||
49 | |||
50 | (RADEON_CRTC_CUR_MODE_24BPP << RADEON_CRTC_CUR_MODE_SHIFT)), |
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51 | ~(RADEON_CRTC_CUR_EN | RADEON_CRTC_CUR_MODE_MASK)); |
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52 | } |
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53 | } |
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54 | |||
55 | |||
56 | { |
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57 | struct radeon_device *rdev = crtc->dev->dev_private; |
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58 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
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59 | uint32_t cur_lock; |
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60 | |||
61 | |||
2004 | serge | 62 | cur_lock = RREG32(EVERGREEN_CUR_UPDATE + radeon_crtc->crtc_offset); |
63 | if (lock) |
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64 | cur_lock |= EVERGREEN_CURSOR_UPDATE_LOCK; |
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65 | else |
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66 | cur_lock &= ~EVERGREEN_CURSOR_UPDATE_LOCK; |
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67 | WREG32(EVERGREEN_CUR_UPDATE + radeon_crtc->crtc_offset, cur_lock); |
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68 | } else if (ASIC_IS_AVIVO(rdev)) { |
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69 | cur_lock = RREG32(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset); |
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1246 | serge | 70 | if (lock) |
71 | cur_lock |= AVIVO_D1CURSOR_UPDATE_LOCK; |
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72 | else |
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73 | cur_lock &= ~AVIVO_D1CURSOR_UPDATE_LOCK; |
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74 | WREG32(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset, cur_lock); |
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75 | } else { |
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76 | cur_lock = RREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset); |
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77 | if (lock) |
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78 | cur_lock |= RADEON_CUR_LOCK; |
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79 | else |
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80 | cur_lock &= ~RADEON_CUR_LOCK; |
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81 | WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, cur_lock); |
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82 | } |
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83 | } |
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84 | |||
85 | |||
86 | { |
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87 | struct radeon_device *rdev; |
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88 | struct radeon_crtc *radeon_crtc; |
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89 | cursor_t *old; |
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90 | uint32_t gpu_addr; |
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91 | |||
92 | |||
5078 | serge | 93 | radeon_crtc = to_radeon_crtc(os_display->crtc); |
94 | |||
1246 | serge | 95 | |
5078 | serge | 96 | |
1246 | serge | 97 | |
5078 | serge | 98 | gpu_addr = radeon_bo_gpu_offset(cursor->robj); |
1404 | serge | 99 | |
1246 | serge | 100 | |
2004 | serge | 101 | WREG32(EVERGREEN_CUR_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, |
102 | 0); |
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103 | WREG32(EVERGREEN_CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset, |
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104 | gpu_addr); |
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105 | } else if (ASIC_IS_AVIVO(rdev)) { |
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106 | if (rdev->family >= CHIP_RV770) |
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107 | WREG32(R700_D1CUR_SURFACE_ADDRESS_HIGH, 0); |
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108 | WREG32(AVIVO_D1CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset, gpu_addr); |
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1246 | serge | 109 | } |
2004 | serge | 110 | else { |
1246 | serge | 111 | radeon_crtc->legacy_cursor_offset = gpu_addr - rdev->mc.vram_start; |
1430 | serge | 112 | /* offset is from DISP(2)_BASE_ADDRESS */ |
1246 | serge | 113 | WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, radeon_crtc->legacy_cursor_offset); |
114 | } |
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115 | |||
116 | |||
117 | }; |
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118 | |||
119 | |||
120 | { |
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121 | struct radeon_device *rdev; |
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122 | rdev = (struct radeon_device *)os_display->ddev->dev_private; |
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5078 | serge | 123 | struct drm_crtc *crtc = os_display->crtc; |
124 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
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1246 | serge | 125 | |
126 | |||
127 | int hot_y = cursor->hot_y; |
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128 | int w = 32; |
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2004 | serge | 129 | |
1246 | serge | 130 | |
131 | |||
132 | |||
2004 | serge | 133 | WREG32(EVERGREEN_CUR_POSITION + radeon_crtc->crtc_offset, |
134 | (x << 16) | y); |
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135 | WREG32(EVERGREEN_CUR_HOT_SPOT + radeon_crtc->crtc_offset, |
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136 | (hot_x << 16) | hot_y); |
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137 | WREG32(EVERGREEN_CUR_SIZE + radeon_crtc->crtc_offset, |
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138 | ((w - 1) << 16) | 31); |
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139 | } else if (ASIC_IS_AVIVO(rdev)) { |
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140 | WREG32(AVIVO_D1CUR_POSITION + radeon_crtc->crtc_offset, |
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1246 | serge | 141 | (x << 16) | y); |
142 | WREG32(AVIVO_D1CUR_HOT_SPOT + radeon_crtc->crtc_offset, |
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143 | (hot_x << 16) | hot_y); |
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144 | WREG32(AVIVO_D1CUR_SIZE + radeon_crtc->crtc_offset, |
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145 | ((w - 1) << 16) | 31); |
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146 | } else { |
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147 | if (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN) |
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148 | y *= 2; |
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149 | |||
150 | |||
1404 | serge | 151 | int xorg =0, yorg=0; |
152 | |||
153 | |||
154 | y = y - hot_y; |
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155 | |||
156 | |||
157 | { |
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158 | xorg = -x + 1; |
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159 | x = 0; |
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160 | } |
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161 | |||
162 | |||
163 | { |
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164 | yorg = -hot_y + 1; |
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165 | y = 0; |
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166 | }; |
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167 | |||
168 | |||
169 | (RADEON_CUR_LOCK | (xorg << 16) | yorg )); |
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170 | WREG32(RADEON_CUR_HORZ_VERT_POSN, |
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171 | (RADEON_CUR_LOCK | (x << 16) | y)); |
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1246 | serge | 172 | |
173 | |||
1404 | serge | 174 | |
175 | |||
1246 | serge | 176 | WREG32(RADEON_CUR_OFFSET, |
1404 | serge | 177 | (gpu_addr - rdev->mc.vram_start + (yorg * 256))); |
1430 | serge | 178 | } |
1246 | serge | 179 | radeon_lock_cursor_kms(crtc, false); |
180 | } |
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181 | |||
182 | |||
183 | { |
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184 | static char name[4]; |
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185 | |||
186 | |||
187 | name[1] = ((x[0] & 0x03) << 3) + ((x[1] & 0xE0) >> 5) + '@'; |
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188 | name[2] = (x[1] & 0x1F) + '@'; |
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189 | name[3] = 0; |
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190 | |||
191 | |||
192 | } |
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193 | |||
194 | |||
5078 | serge | 195 | struct drm_crtc *crtc, videomode_t *reqmode, bool strict) |
196 | { |
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1246 | serge | 197 | struct drm_display_mode *mode = NULL, *tmpmode; |
198 | struct drm_framebuffer *fb = NULL; |
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5078 | serge | 199 | struct drm_mode_set set; |
200 | const char *con_name; |
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201 | unsigned hdisplay, vdisplay; |
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202 | int ret; |
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203 | |||
1246 | serge | 204 | |
5078 | serge | 205 | |
1986 | serge | 206 | |
1246 | serge | 207 | { |
208 | if( (tmpmode->hdisplay == reqmode->width) && |
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5078 | serge | 209 | (tmpmode->vdisplay == reqmode->height) && |
210 | (drm_mode_vrefresh(tmpmode) == reqmode->freq) ) |
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1246 | serge | 211 | { |
212 | mode = tmpmode; |
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213 | goto do_set; |
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214 | } |
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215 | }; |
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5078 | serge | 216 | |
1246 | serge | 217 | |
218 | { |
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219 | list_for_each_entry(tmpmode, &connector->modes, head) |
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220 | { |
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221 | if( (tmpmode->hdisplay == reqmode->width) && |
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5078 | serge | 222 | (tmpmode->vdisplay == reqmode->height) ) |
223 | { |
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1246 | serge | 224 | mode = tmpmode; |
225 | goto do_set; |
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226 | } |
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227 | }; |
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5078 | serge | 228 | }; |
1246 | serge | 229 | |
230 | |||
5078 | serge | 231 | |
232 | |||
233 | |||
234 | |||
1246 | serge | 235 | |
236 | |||
5078 | serge | 237 | |
1246 | serge | 238 | |
5078 | serge | 239 | reqmode->width, reqmode->height, crtc->base.id, |
240 | con_name); |
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241 | |||
1246 | serge | 242 | |
5078 | serge | 243 | |
1246 | serge | 244 | |
5078 | serge | 245 | vdisplay = mode->vdisplay; |
246 | |||
1246 | serge | 247 | |
5078 | serge | 248 | swap(hdisplay, vdisplay); |
249 | |||
1246 | serge | 250 | |
5078 | serge | 251 | |
1246 | serge | 252 | |
5078 | serge | 253 | fb->height = reqmode->height; |
254 | |||
1246 | serge | 255 | |
5078 | serge | 256 | fb->pitches[1] = |
257 | fb->pitches[2] = |
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258 | fb->pitches[3] = radeon_align_pitch(dev->dev_private, reqmode->width, 32, false) * ((32 + 1) / 8); |
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259 | fb->bits_per_pixel = 32; |
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260 | fb->depth = 24; |
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261 | |||
1246 | serge | 262 | |
5078 | serge | 263 | os_display->crtc = crtc; |
264 | |||
1986 | serge | 265 | |
5078 | serge | 266 | set.x = 0; |
267 | set.y = 0; |
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268 | set.mode = mode; |
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269 | set.connectors = &connector; |
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270 | set.num_connectors = 1; |
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271 | set.fb = fb; |
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272 | |||
2997 | Serge | 273 | |
5078 | serge | 274 | |
1246 | serge | 275 | |
5078 | serge | 276 | |
1246 | serge | 277 | |
5078 | serge | 278 | radeon_show_cursor_kms(crtc); |
279 | |||
1246 | serge | 280 | |
5078 | serge | 281 | { |
282 | os_display->width = fb->width; |
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283 | os_display->height = fb->height; |
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284 | os_display->vrefresh = drm_mode_vrefresh(mode); |
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285 | |||
1246 | serge | 286 | |
5078 | serge | 287 | |
1246 | serge | 288 | |
5078 | serge | 289 | fb->width, fb->height, fb->pitches[0]); |
2997 | Serge | 290 | } |
1246 | serge | 291 | else |
5078 | serge | 292 | DRM_ERROR("failed to set mode %d_%d on crtc %p\n", |
293 | fb->width, fb->height, crtc); |
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294 | |||
1246 | serge | 295 | |
296 | } |
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5078 | serge | 297 | |
1246 | serge | 298 | |
299 | { |
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300 | struct drm_display_mode *mode; |
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301 | int count = 0; |
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302 | |||
303 | |||
304 | { |
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305 | count++; |
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306 | }; |
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307 | return count; |
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308 | }; |
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309 | |||
310 | |||
5078 | serge | 311 | { |
1246 | serge | 312 | struct drm_crtc *tmp_crtc; |
5078 | serge | 313 | int crtc_mask = 1; |
314 | |||
315 | |||
316 | { |
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317 | if (encoder->possible_crtcs & crtc_mask) |
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318 | { |
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319 | encoder->crtc = tmp_crtc; |
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320 | DRM_DEBUG_KMS("use CRTC %p ID %d\n", tmp_crtc, tmp_crtc->base.id); |
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321 | return tmp_crtc; |
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322 | }; |
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323 | crtc_mask <<= 1; |
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324 | }; |
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325 | return NULL; |
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326 | }; |
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327 | |||
328 | |||
329 | struct drm_crtc **boot_crtc) |
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330 | { |
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331 | struct drm_connector_helper_funcs *connector_funcs; |
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1963 | serge | 332 | struct drm_connector *connector; |
5078 | serge | 333 | struct drm_encoder *encoder; |
334 | struct drm_crtc *crtc; |
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335 | |||
1963 | serge | 336 | |
1246 | serge | 337 | { |
338 | if( connector->status != connector_status_connected) |
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339 | continue; |
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340 | |||
341 | |||
5078 | serge | 342 | |
1246 | serge | 343 | |
5078 | serge | 344 | { |
345 | connector_funcs = connector->helper_private; |
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346 | encoder = connector_funcs->best_encoder(connector); |
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347 | |||
1963 | serge | 348 | |
5078 | serge | 349 | { |
350 | DRM_DEBUG_KMS("CONNECTOR %x ID: %d no active encoders\n", |
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351 | connector, connector->base.id); |
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352 | continue; |
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353 | }; |
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354 | } |
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355 | |||
356 | |||
1246 | serge | 357 | if(crtc == NULL) |
5078 | serge | 358 | crtc = get_possible_crtc(dev, encoder); |
359 | |||
1963 | serge | 360 | |
5078 | serge | 361 | { |
362 | *boot_connector = connector; |
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363 | *boot_crtc = crtc; |
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364 | connector->encoder = encoder; |
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365 | DRM_DEBUG_KMS("CONNECTOR %p ID:%d status:%d ENCODER %p ID: %d CRTC %p ID:%d\n", |
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366 | connector, connector->base.id, connector->status, |
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367 | encoder, encoder->base.id, crtc, crtc->base.id ); |
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368 | return 0; |
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369 | } |
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370 | else |
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371 | DRM_DEBUG_KMS("No CRTC for encoder %d\n", encoder->base.id); |
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372 | |||
1246 | serge | 373 | |
374 | |||
375 | |||
5078 | serge | 376 | }; |
1246 | serge | 377 | |
378 | |||
5078 | serge | 379 | { |
380 | struct drm_display_mode *mode; |
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381 | |||
1986 | serge | 382 | |
5078 | serge | 383 | { |
384 | DRM_DEBUG_KMS("check mode w:%d h:%d %dHz\n", |
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385 | mode->hdisplay, mode->vdisplay, |
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386 | drm_mode_vrefresh(mode)); |
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387 | |||
1986 | serge | 388 | |
5078 | serge | 389 | os_display->height == mode->vdisplay && |
390 | drm_mode_vrefresh(mode) == 60) |
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391 | { |
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392 | usermode->width = os_display->width; |
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393 | usermode->height = os_display->height; |
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394 | usermode->freq = 60; |
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395 | return 1; |
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396 | } |
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397 | } |
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398 | return 0; |
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399 | } |
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400 | |||
401 | |||
402 | { |
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1246 | serge | 403 | struct drm_connector_helper_funcs *connector_funcs; |
2997 | Serge | 404 | struct drm_connector *connector = NULL; |
5078 | serge | 405 | struct drm_crtc *crtc = NULL; |
2997 | Serge | 406 | struct drm_framebuffer *fb; |
407 | |||
408 | |||
1246 | serge | 409 | u32_t ifl; |
410 | int ret; |
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5078 | serge | 411 | |
1246 | serge | 412 | |
5078 | serge | 413 | |
1986 | serge | 414 | |
5078 | serge | 415 | if(ret) |
416 | { |
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2997 | Serge | 417 | DRM_DEBUG_KMS("No active connectors!\n"); |
5078 | serge | 418 | mutex_unlock(&dev->mode_config.mutex); |
419 | return -1; |
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2997 | Serge | 420 | }; |
421 | |||
422 | |||
423 | struct drm_display_mode *tmp, *native = NULL; |
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5078 | serge | 424 | struct radeon_device *rdev = dev->dev_private; |
425 | |||
2997 | Serge | 426 | |
427 | if (tmp->hdisplay > 16384 || |
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5078 | serge | 428 | tmp->vdisplay > 16384) |
429 | continue; |
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2997 | Serge | 430 | if (tmp->type & DRM_MODE_TYPE_PREFERRED) |
431 | { |
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432 | native = tmp; |
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433 | break; |
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434 | }; |
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435 | } |
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436 | |||
437 | |||
5078 | serge | 438 | { |
1246 | serge | 439 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(connector->encoder); |
5078 | serge | 440 | radeon_encoder->rmx_type = RMX_FULL; |
441 | radeon_encoder->native_mode = *native; |
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442 | }; |
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1246 | serge | 443 | } |
5078 | serge | 444 | |
1246 | serge | 445 | |
5078 | serge | 446 | mutex_lock(&dev->object_name_lock); |
447 | idr_preload(GFP_KERNEL); |
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448 | |||
1986 | serge | 449 | |
5078 | serge | 450 | ret = idr_alloc(&dev->object_name_idr, &main_fb_obj, 1, 0, GFP_NOWAIT); |
451 | |||
1986 | serge | 452 | |
5078 | serge | 453 | |
1986 | serge | 454 | |
5078 | serge | 455 | drm_gem_object_reference(main_fb_obj); |
456 | |||
1986 | serge | 457 | |
5078 | serge | 458 | } |
459 | |||
1986 | serge | 460 | |
5078 | serge | 461 | mutex_unlock(&dev->object_name_lock); |
462 | drm_gem_object_unreference(main_fb_obj); |
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463 | #endif |
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464 | |||
1986 | serge | 465 | |
5078 | serge | 466 | os_display->ddev = dev; |
467 | os_display->connector = connector; |
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468 | os_display->crtc = crtc; |
||
469 | |||
1986 | serge | 470 | |
5078 | serge | 471 | |
1986 | serge | 472 | |
2997 | Serge | 473 | { |
474 | list_for_each_entry(cursor, &os_display->cursors, list) |
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5078 | serge | 475 | { |
2997 | Serge | 476 | init_cursor(cursor); |
477 | }; |
||
478 | |||
1986 | serge | 479 | |
5078 | serge | 480 | os_display->init_cursor = init_cursor; |
481 | os_display->select_cursor = select_cursor_kms; |
||
482 | os_display->show_cursor = NULL; |
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483 | os_display->move_cursor = move_cursor_kms; |
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484 | os_display->restore_cursor = restore_cursor; |
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485 | os_display->disable_mouse = disable_mouse; |
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486 | select_cursor_kms(os_display->cursor); |
||
487 | }; |
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1246 | serge | 488 | safe_sti(ifl); |
2997 | Serge | 489 | |
1246 | serge | 490 | |
1986 | serge | 491 | |
5078 | serge | 492 | // os_display->width, os_display->height, os_display->vrefresh); |
493 | // dbgprintf("user mode mode %d x %d x %d\n", |
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494 | // usermode->width, usermode->height, usermode->freq); |
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495 | |||
1268 | serge | 496 | |
5078 | serge | 497 | (usermode->height == 0)) |
498 | { |
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1246 | serge | 499 | if( !get_boot_mode(connector, usermode)) |
5078 | serge | 500 | { |
501 | struct drm_display_mode *mode; |
||
502 | |||
1246 | serge | 503 | |
5078 | serge | 504 | usermode->width = mode->hdisplay; |
505 | usermode->height = mode->vdisplay; |
||
506 | usermode->freq = drm_mode_vrefresh(mode); |
||
507 | }; |
||
508 | }; |
||
2997 | Serge | 509 | |
1246 | serge | 510 | |
5078 | serge | 511 | |
1268 | serge | 512 | |
5078 | serge | 513 | |
1246 | serge | 514 | |
5078 | serge | 515 | |
3120 | serge | 516 | |
5078 | serge | 517 | }; |
1246 | serge | 518 | |
519 | |||
5078 | serge | 520 | |
521 | { |
||
1246 | serge | 522 | int err = -1; |
523 | |||
524 | |||
525 | { |
||
526 | *count = os_display->supported_modes; |
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5078 | serge | 527 | err = 0; |
1246 | serge | 528 | } |
529 | else if( mode != NULL ) |
||
530 | { |
||
531 | struct drm_display_mode *drmmode; |
||
532 | int i = 0; |
||
533 | |||
534 | |||
5078 | serge | 535 | *count = os_display->supported_modes; |
536 | |||
1246 | serge | 537 | |
5078 | serge | 538 | { |
1246 | serge | 539 | if( i < *count) |
540 | { |
||
541 | mode->width = drmmode->hdisplay; |
||
5078 | serge | 542 | mode->height = drmmode->vdisplay; |
543 | mode->bpp = 32; |
||
1246 | serge | 544 | mode->freq = drm_mode_vrefresh(drmmode); |
545 | i++; |
||
546 | mode++; |
||
547 | } |
||
548 | else break; |
||
549 | }; |
||
550 | *count = i; |
||
551 | err = 0; |
||
552 | }; |
||
553 | return err; |
||
554 | }; |
||
5078 | serge | 555 | |
1246 | serge | 556 | |
1403 | serge | 557 | { |
1246 | serge | 558 | int err = -1; |
559 | |||
560 | |||
561 | (mode->height != 0) && |
||
562 | (mode->freq != 0 ) && |
||
563 | ( (mode->width != os_display->width) || |
||
5078 | serge | 564 | (mode->height != os_display->height) || |
565 | (mode->freq != os_display->vrefresh) ) ) |
||
566 | { |
||
1246 | serge | 567 | return set_mode(os_display->ddev, os_display->connector, os_display->crtc, mode, true); |
5078 | serge | 568 | }; |
1246 | serge | 569 | |
570 | |||
5078 | serge | 571 | }; |
1246 | serge | 572 | |
573 | |||
1986 | serge | 574 | |
1404 | serge | 575 | |
1986 | serge | 576 | |
2997 | Serge | 577 | |
3764 | Serge | 578 | typedef struct |
3120 | serge | 579 | { |
580 | int left; |
||
581 | int top; |
||
582 | int right; |
||
583 | int bottom; |
||
584 | }rect_t; |
||
585 | |||
586 | |||
587 | struct drm_device *main_device; |
||
5078 | serge | 588 | |
3120 | serge | 589 | |
590 | |||
591 | |||
592 | |||
593 | |||
594 | { |
||
595 | u32_t addr; |
||
596 | |||
597 | |||
5078 | serge | 598 | addr+= sizeof(display_t); /* shoot me */ |
3120 | serge | 599 | return *(u32_t*)addr; |
600 | } |
||
601 | |||
602 | |||
603 | #include "r100d.h" |
||
604 | |||
605 | |||
3764 | Serge | 606 | # define PACKET3_TRANS_BITBLT 0x9C |
3124 | serge | 607 | # define R5XX_SRC_CMP_EQ_COLOR (4 << 0) |
608 | # define R5XX_SRC_CMP_NEQ_COLOR (5 << 0) |
||
609 | # define R5XX_CLR_CMP_SRC_SOURCE (1 << 24) |
||
610 | |||
3120 | serge | 611 | |
612 | int src_x, int src_y, u32 w, u32 h) |
||
613 | { |
||
614 | struct context *context; |
||
615 | |||
616 | |||
617 | rect_t winrc; |
||
618 | clip_t dst_clip; |
||
619 | clip_t src_clip; |
||
620 | u32_t width; |
||
621 | u32_t height; |
||
622 | |||
623 | |||
624 | u32_t offset; |
||
625 | u8 slot; |
||
626 | int n=0; |
||
627 | int ret; |
||
628 | |||
629 | |||
630 | return -1; |
||
631 | |||
632 | |||
633 | |||
634 | |||
635 | return -1; |
||
636 | |||
637 | |||
638 | if(unlikely(context == NULL)) |
||
639 | return -1; |
||
640 | |||
641 | |||
642 | { |
||
643 | static warn_count; |
||
644 | |||
645 | |||
646 | { |
||
647 | printf("left %d top %d right %d bottom %d\n", |
||
648 | winrc.left, winrc.top, winrc.right, winrc.bottom); |
||
649 | printf("bitmap width %d height %d\n", w, h); |
||
650 | warn_count++; |
||
651 | }; |
||
652 | }; |
||
653 | |||
654 | |||
655 | |||
656 | dst_clip.ymin = 0; |
||
657 | dst_clip.xmax = winrc.right-winrc.left; |
||
658 | dst_clip.ymax = winrc.bottom -winrc.top; |
||
659 | |||
660 | |||
661 | src_clip.ymin = 0; |
||
662 | src_clip.xmax = bitmap->width - 1; |
||
663 | src_clip.ymax = bitmap->height - 1; |
||
664 | |||
665 | |||
666 | height = h; |
||
667 | |||
668 | |||
669 | &src_clip, &src_x, &src_y, |
||
670 | &width, &height) ) |
||
671 | return 0; |
||
672 | |||
673 | |||
674 | dst_y+= winrc.top; |
||
675 | |||
676 | |||
677 | |||
678 | |||
679 | |||
680 | |||
681 | #if 0 |
||
3124 | serge | 682 | #else |
3120 | serge | 683 | u8* src_offset; |
684 | u8* dst_offset; |
||
685 | u32 color; |
||
3124 | serge | 686 | |
687 | |||
3120 | serge | 688 | |
689 | |||
690 | src_offset += (u32)bitmap->uaddr; |
||
691 | |||
692 | |||
5078 | serge | 693 | dst_offset+= get_display_map(); |
3120 | serge | 694 | |
695 | |||
696 | |||
697 | |||
698 | while( tmp_h--) |
||
699 | { |
||
700 | u32 tmp_w = width; |
||
3124 | serge | 701 | |
3120 | serge | 702 | |
3124 | serge | 703 | u8* tmp_dst = dst_offset; |
3764 | Serge | 704 | |
3120 | serge | 705 | |
706 | dst_offset+= os_display->width; |
||
5078 | serge | 707 | |
3120 | serge | 708 | |
709 | { |
||
710 | color = *tmp_src; |
||
3124 | serge | 711 | |
712 | |||
713 | color |= 0xFF000000; |
||
714 | else |
||
715 | color = 0x00; |
||
716 | |||
717 | |||
718 | tmp_src++; |
||
719 | tmp_dst++; |
||
3120 | serge | 720 | }; |
721 | }; |
||
722 | safe_sti(ifl); |
||
723 | #endif |
||
724 | } |
||
725 | |||
726 | |||
727 | static warn_count; |
||
728 | |||
729 | |||
730 | { |
||
731 | printf("blit width %d height %d\n", |
||
732 | width, height); |
||
733 | warn_count++; |
||
734 | }; |
||
735 | }; |
||
736 | |||
737 | |||
738 | |||
739 | // context->cmd_buffer&= 0xFFFFF000; |
||
740 | |||
741 | |||
742 | |||
743 | |||
744 | |||
745 | |||
746 | |||
747 | |||
748 | |||
749 | struct radeon_ib *ib = &context->ib; |
||
750 | |||
751 | |||
3124 | serge | 752 | ib->ptr[1] = 0xFFFFFFFF; |
753 | ib->ptr[2] = PACKET3(PACKET3_TRANS_BITBLT, 11); |
||
754 | ib->ptr[3] = RADEON_GMC_SRC_PITCH_OFFSET_CNTL | |
||
755 | RADEON_GMC_DST_PITCH_OFFSET_CNTL | |
||
3120 | serge | 756 | RADEON_GMC_SRC_CLIPPING | |
757 | RADEON_GMC_DST_CLIPPING | |
||
758 | RADEON_GMC_BRUSH_NONE | |
||
759 | (RADEON_COLOR_FORMAT_ARGB8888 << 8) | |
||
760 | RADEON_GMC_SRC_DATATYPE_COLOR | |
||
761 | RADEON_ROP3_S | |
||
762 | RADEON_DP_SRC_SOURCE_MEMORY | |
||
763 | RADEON_GMC_WR_MSK_DIS; |
||
764 | |||
765 | |||
3124 | serge | 766 | ib->ptr[5] = ((os_display->pitch/64) << 22) | (rdev->mc.vram_start >> 10); |
5078 | serge | 767 | ib->ptr[6] = (0x1fff) | (0x1fff << 16); |
3120 | serge | 768 | ib->ptr[7] = 0; |
3124 | serge | 769 | ib->ptr[8] = (0x1fff) | (0x1fff << 16); |
770 | |||
3120 | serge | 771 | |
3124 | serge | 772 | ib->ptr[10] = 0x00000000; |
773 | ib->ptr[11] = 0xFFFFFFFF; |
||
774 | |||
3120 | serge | 775 | |
3124 | serge | 776 | ib->ptr[13] = (dst_x << 16) | dst_y; |
777 | ib->ptr[14] = (width << 16) | height; |
||
778 | |||
779 | |||
3120 | serge | 780 | |
781 | |||
782 | |||
783 | |||
784 | if (ret) { |
||
785 | DRM_ERROR("radeon: failed to schedule ib (%d).\n", ret); |
||
786 | goto fail; |
||
787 | } |
||
788 | |||
789 | |||
790 | if (ret) { |
||
791 | DRM_ERROR("radeon: fence wait failed (%d).\n", ret); |
||
792 | goto fail; |
||
793 | } |
||
794 | |||
795 | |||
3192 | Serge | 796 | |
797 | |||
3120 | serge | 798 | return ret; |
799 | }; |
||
800 | |||
801 | |||
3764 | Serge | 802 |