Rev 1275 | Rev 1403 | Go to most recent revision | Details | Compare with Previous | Last modification | View Log | RSS feed
Rev | Author | Line No. | Line |
---|---|---|---|
1246 | serge | 1 | |
2 | #include |
||
3 | #include |
||
4 | #include |
||
5 | #include "radeon_drm.h" |
||
6 | #include "radeon.h" |
||
7 | #include "radeon_object.h" |
||
8 | #include "display.h" |
||
9 | |||
10 | |||
11 | |||
12 | static void __stdcall move_cursor_kms(cursor_t *cursor, int x, int y); |
||
13 | |||
14 | |||
15 | |||
16 | |||
1313 | serge | 17 | |
18 | |||
1246 | serge | 19 | { |
20 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
||
21 | struct radeon_device *rdev = crtc->dev->dev_private; |
||
22 | |||
23 | |||
24 | WREG32(RADEON_MM_INDEX, AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset); |
||
25 | WREG32(RADEON_MM_DATA, AVIVO_D1CURSOR_EN | |
||
26 | (AVIVO_D1CURSOR_MODE_24BPP << AVIVO_D1CURSOR_MODE_SHIFT)); |
||
27 | } else { |
||
28 | switch (radeon_crtc->crtc_id) { |
||
29 | case 0: |
||
30 | WREG32(RADEON_MM_INDEX, RADEON_CRTC_GEN_CNTL); |
||
31 | break; |
||
32 | case 1: |
||
33 | WREG32(RADEON_MM_INDEX, RADEON_CRTC2_GEN_CNTL); |
||
34 | break; |
||
35 | default: |
||
36 | return; |
||
37 | } |
||
38 | |||
39 | |||
40 | (RADEON_CRTC_CUR_MODE_24BPP << RADEON_CRTC_CUR_MODE_SHIFT)), |
||
41 | ~(RADEON_CRTC_CUR_EN | RADEON_CRTC_CUR_MODE_MASK)); |
||
42 | } |
||
43 | } |
||
44 | |||
45 | |||
46 | { |
||
47 | struct radeon_device *rdev = crtc->dev->dev_private; |
||
48 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
||
49 | uint32_t cur_lock; |
||
50 | |||
51 | |||
52 | cur_lock = RREG32(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset); |
||
53 | if (lock) |
||
54 | cur_lock |= AVIVO_D1CURSOR_UPDATE_LOCK; |
||
55 | else |
||
56 | cur_lock &= ~AVIVO_D1CURSOR_UPDATE_LOCK; |
||
57 | WREG32(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset, cur_lock); |
||
58 | } else { |
||
59 | cur_lock = RREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset); |
||
60 | if (lock) |
||
61 | cur_lock |= RADEON_CUR_LOCK; |
||
62 | else |
||
63 | cur_lock &= ~RADEON_CUR_LOCK; |
||
64 | WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, cur_lock); |
||
65 | } |
||
66 | } |
||
67 | |||
68 | |||
69 | { |
||
70 | struct radeon_device *rdev; |
||
71 | struct radeon_crtc *radeon_crtc; |
||
72 | cursor_t *old; |
||
73 | uint32_t gpu_addr; |
||
74 | |||
75 | |||
76 | radeon_crtc = to_radeon_crtc(rdisplay->crtc); |
||
77 | |||
78 | |||
79 | |||
80 | |||
81 | gpu_addr = cursor->robj->gpu_addr; |
||
82 | |||
83 | |||
84 | WREG32(AVIVO_D1CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset, gpu_addr); |
||
85 | else { |
||
86 | radeon_crtc->legacy_cursor_offset = gpu_addr - rdev->mc.vram_location; |
||
1275 | serge | 87 | /* offset is from DISP(2)_BASE_ADDRESS */ |
1246 | serge | 88 | WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, radeon_crtc->legacy_cursor_offset); |
89 | } |
||
90 | |||
91 | |||
92 | }; |
||
93 | |||
94 | |||
95 | { |
||
96 | struct radeon_device *rdev; |
||
97 | rdev = (struct radeon_device *)rdisplay->ddev->dev_private; |
||
98 | struct drm_crtc *crtc = rdisplay->crtc; |
||
99 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
||
100 | |||
101 | |||
102 | int hot_y = cursor->hot_y; |
||
103 | |||
104 | |||
105 | if (ASIC_IS_AVIVO(rdev)) |
||
106 | { |
||
107 | int w = 32; |
||
108 | int i = 0; |
||
109 | struct drm_crtc *crtc_p; |
||
110 | |||
111 | |||
112 | // x += crtc->x; |
||
113 | // y += crtc->y; |
||
114 | |||
115 | |||
116 | #if 0 |
||
117 | /* avivo cursor image can't end on 128 pixel boundry or |
||
118 | * go past the end of the frame if both crtcs are enabled |
||
119 | */ |
||
120 | list_for_each_entry(crtc_p, &crtc->dev->mode_config.crtc_list, head) { |
||
121 | if (crtc_p->enabled) |
||
122 | i++; |
||
123 | } |
||
124 | if (i > 1) { |
||
125 | int cursor_end, frame_end; |
||
126 | |||
127 | |||
128 | frame_end = crtc->x + crtc->mode.crtc_hdisplay; |
||
129 | if (cursor_end >= frame_end) { |
||
130 | w = w - (cursor_end - frame_end); |
||
131 | if (!(frame_end & 0x7f)) |
||
132 | w--; |
||
133 | } else { |
||
134 | if (!(cursor_end & 0x7f)) |
||
135 | w--; |
||
136 | } |
||
137 | if (w <= 0) |
||
138 | w = 1; |
||
139 | } |
||
140 | #endif |
||
141 | WREG32(AVIVO_D1CUR_POSITION + radeon_crtc->crtc_offset, |
||
142 | (x << 16) | y); |
||
143 | WREG32(AVIVO_D1CUR_HOT_SPOT + radeon_crtc->crtc_offset, |
||
144 | (hot_x << 16) | hot_y); |
||
145 | WREG32(AVIVO_D1CUR_SIZE + radeon_crtc->crtc_offset, |
||
146 | ((w - 1) << 16) | 31); |
||
147 | } else { |
||
148 | if (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN) |
||
149 | y *= 2; |
||
150 | |||
151 | |||
152 | (RADEON_CUR_LOCK | (hot_x << 16) | hot_y )); |
||
1275 | serge | 153 | WREG32(RADEON_CUR_HORZ_VERT_POSN + radeon_crtc->crtc_offset, |
1246 | serge | 154 | (RADEON_CUR_LOCK | (x << 16) | y)); |
155 | |||
156 | |||
157 | WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, |
||
158 | (radeon_crtc->legacy_cursor_offset + (hot_y * 256))); |
||
159 | } |
||
160 | radeon_lock_cursor_kms(crtc, false); |
||
161 | } |
||
162 | |||
163 | |||
164 | { |
||
165 | static char name[4]; |
||
166 | |||
167 | |||
168 | name[1] = ((x[0] & 0x03) << 3) + ((x[1] & 0xE0) >> 5) + '@'; |
||
169 | name[2] = (x[1] & 0x1F) + '@'; |
||
170 | name[3] = 0; |
||
171 | |||
172 | |||
173 | } |
||
174 | |||
175 | |||
176 | mode_t *reqmode, bool strict) |
||
177 | { |
||
178 | struct drm_display_mode *mode = NULL, *tmpmode; |
||
179 | |||
180 | |||
181 | |||
182 | |||
183 | |||
184 | |||
185 | reqmode->width, reqmode->height, reqmode->freq); |
||
186 | |||
187 | |||
188 | { |
||
189 | if( (drm_mode_width(tmpmode) == reqmode->width) && |
||
190 | (drm_mode_height(tmpmode) == reqmode->height) && |
||
191 | (drm_mode_vrefresh(tmpmode) == reqmode->freq) ) |
||
192 | { |
||
193 | mode = tmpmode; |
||
194 | goto do_set; |
||
195 | } |
||
196 | }; |
||
197 | |||
198 | |||
199 | { |
||
200 | list_for_each_entry(tmpmode, &connector->modes, head) |
||
201 | { |
||
202 | if( (drm_mode_width(tmpmode) == reqmode->width) && |
||
203 | (drm_mode_height(tmpmode) == reqmode->height) ) |
||
204 | { |
||
205 | mode = tmpmode; |
||
206 | goto do_set; |
||
207 | } |
||
208 | }; |
||
209 | }; |
||
210 | |||
211 | |||
212 | |||
213 | |||
214 | { |
||
215 | struct drm_framebuffer *fb; |
||
216 | struct drm_encoder *encoder; |
||
217 | struct drm_crtc *crtc; |
||
218 | |||
219 | |||
220 | char *con_name; |
||
221 | char *enc_name; |
||
222 | |||
223 | |||
224 | crtc = encoder->crtc; |
||
225 | |||
226 | |||
227 | struct drm_framebuffer, filp_head); |
||
228 | |||
229 | |||
230 | |||
231 | |||
232 | // manufacturer_name(con_edid + 0x08), |
||
233 | // (unsigned short)(con_edid[0x0A] + (con_edid[0x0B] << 8)), |
||
234 | // (unsigned int)(con_edid[0x0C] + (con_edid[0x0D] << 8) |
||
235 | // + (con_edid[0x0E] << 16) + (con_edid[0x0F] << 24))); |
||
236 | |||
237 | |||
238 | enc_name = drm_get_encoder_name(encoder); |
||
239 | |||
240 | |||
241 | reqmode->width, reqmode->height, con_name, enc_name); |
||
242 | |||
243 | |||
244 | fb->height = reqmode->height; |
||
245 | fb->pitch = radeon_align_pitch(dev->dev_private, reqmode->width, 32, false) * ((32 + 1) / 8); |
||
246 | |||
247 | |||
248 | crtc->enabled = true; |
||
249 | rdisplay->crtc = crtc; |
||
250 | |||
251 | |||
252 | |||
253 | |||
254 | radeon_show_cursor_kms(crtc); |
||
255 | |||
256 | |||
257 | { |
||
258 | rdisplay->width = fb->width; |
||
259 | rdisplay->height = fb->height; |
||
260 | rdisplay->pitch = fb->pitch; |
||
261 | rdisplay->vrefresh = drm_mode_vrefresh(mode); |
||
262 | |||
263 | |||
264 | |||
265 | |||
266 | fb->width, fb->height, fb->pitch); |
||
267 | } |
||
268 | else |
||
269 | DRM_ERROR("failed to set mode %d_%d on crtc %p\n", |
||
270 | fb->width, fb->height, crtc); |
||
271 | } |
||
272 | |||
273 | |||
274 | return ret; |
||
275 | }; |
||
276 | |||
277 | |||
278 | { |
||
279 | struct drm_display_mode *mode; |
||
280 | int count = 0; |
||
281 | |||
282 | |||
283 | { |
||
284 | count++; |
||
285 | }; |
||
286 | return count; |
||
287 | }; |
||
288 | |||
289 | |||
290 | { |
||
291 | struct drm_connector *connector; |
||
292 | struct drm_connector *def_connector = NULL; |
||
293 | |||
294 | |||
295 | { |
||
296 | struct drm_encoder *encoder; |
||
297 | struct drm_crtc *crtc; |
||
298 | |||
299 | |||
300 | continue; |
||
301 | |||
302 | |||
303 | if( encoder == NULL) |
||
304 | continue; |
||
305 | |||
306 | |||
307 | if(crtc == NULL) |
||
308 | continue; |
||
309 | |||
310 | |||
311 | break; |
||
312 | }; |
||
313 | |||
314 | |||
315 | }; |
||
316 | |||
317 | |||
318 | { |
||
319 | struct drm_device *dev; |
||
320 | |||
321 | |||
322 | bool retval = false; |
||
323 | u32_t ifl; |
||
324 | |||
325 | |||
326 | |||
327 | |||
328 | |||
329 | |||
330 | |||
331 | |||
332 | { |
||
333 | list_for_each_entry(cursor, &rdisplay->cursors, list) |
||
334 | { |
||
335 | init_cursor(cursor); |
||
336 | }; |
||
337 | }; |
||
338 | safe_sti(ifl); |
||
339 | |||
340 | |||
341 | if( rdisplay->connector == 0 ) |
||
342 | { |
||
343 | dbgprintf("no active connectors\n"); |
||
344 | return false; |
||
345 | }; |
||
346 | |||
347 | |||
348 | rdisplay->supported_modes = count_connector_modes(rdisplay->connector); |
||
349 | |||
350 | |||
1268 | serge | 351 | rdisplay->width, rdisplay->height, rdisplay->vrefresh); |
352 | dbgprintf("user mode mode %d x %d x %d\n", |
||
353 | usermode->width, usermode->height, usermode->freq); |
||
354 | |||
355 | |||
1246 | serge | 356 | (usermode->height != 0) && |
357 | ( (usermode->width != rdisplay->width) || |
||
358 | (usermode->height != rdisplay->height) || |
||
359 | (usermode->freq != rdisplay->vrefresh) ) ) |
||
360 | { |
||
361 | |||
362 | |||
363 | } |
||
364 | |||
365 | |||
366 | { |
||
367 | rdisplay->restore_cursor(0,0); |
||
368 | rdisplay->init_cursor = init_cursor; |
||
369 | rdisplay->select_cursor = select_cursor_kms; |
||
370 | rdisplay->show_cursor = NULL; |
||
371 | rdisplay->move_cursor = move_cursor_kms; |
||
372 | rdisplay->restore_cursor = restore_cursor; |
||
373 | rdisplay->disable_mouse = disable_mouse; |
||
1313 | serge | 374 | |
1268 | serge | 375 | |
376 | radeon_show_cursor_kms(rdisplay->crtc); |
||
1246 | serge | 377 | }; |
378 | safe_sti(ifl); |
||
379 | |||
380 | |||
381 | |||
382 | |||
383 | }; |
||
384 | |||
385 | |||
386 | { |
||
387 | int err = -1; |
||
388 | |||
389 | |||
390 | |||
391 | |||
392 | |||
393 | |||
394 | { |
||
395 | *count = rdisplay->supported_modes; |
||
396 | err = 0; |
||
397 | } |
||
398 | else if( mode != NULL ) |
||
399 | { |
||
400 | struct drm_display_mode *drmmode; |
||
401 | int i = 0; |
||
402 | |||
403 | |||
404 | *count = rdisplay->supported_modes; |
||
405 | |||
406 | |||
407 | { |
||
408 | if( i < *count) |
||
409 | { |
||
410 | mode->width = drm_mode_width(drmmode); |
||
411 | mode->height = drm_mode_height(drmmode); |
||
412 | mode->bpp = 32; |
||
413 | mode->freq = drm_mode_vrefresh(drmmode); |
||
414 | i++; |
||
415 | mode++; |
||
416 | } |
||
417 | else break; |
||
418 | }; |
||
419 | *count = i; |
||
420 | err = 0; |
||
421 | }; |
||
422 | LEAVE(); |
||
423 | return err; |
||
424 | } |
||
425 | |||
426 | |||
427 | { |
||
428 | int err = -1; |
||
429 | |||
430 | |||
431 | |||
432 | |||
433 | mode->width, mode->height, mode->freq); |
||
434 | |||
435 | |||
436 | (mode->height != 0) && |
||
437 | (mode->freq != 0 ) && |
||
438 | ( (mode->width != rdisplay->width) || |
||
439 | (mode->height != rdisplay->height) || |
||
440 | (mode->freq != rdisplay->vrefresh) ) ) |
||
441 | { |
||
442 | if( set_mode(rdisplay->ddev, rdisplay->connector, mode, true) ) |
||
443 | err = 0; |
||
444 | }; |
||
445 | |||
446 | |||
447 | return err; |
||
448 | };>><>><>><>><>><>><>><>><>><>><>=>><>><> |
||
449 |