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Rev | Author | Line No. | Line |
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1246 | serge | 1 | |
2 | #include |
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3 | #include |
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4 | #include |
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5 | #include "radeon_drm.h" |
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6 | #include "radeon.h" |
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7 | #include "radeon_object.h" |
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8 | #include "display.h" |
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9 | |||
10 | |||
11 | |||
12 | static void __stdcall move_cursor_kms(cursor_t *cursor, int x, int y); |
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13 | |||
14 | |||
15 | |||
16 | |||
17 | { |
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18 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
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19 | struct radeon_device *rdev = crtc->dev->dev_private; |
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20 | |||
21 | |||
22 | WREG32(RADEON_MM_INDEX, AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset); |
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23 | WREG32(RADEON_MM_DATA, AVIVO_D1CURSOR_EN | |
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24 | (AVIVO_D1CURSOR_MODE_24BPP << AVIVO_D1CURSOR_MODE_SHIFT)); |
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25 | } else { |
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26 | switch (radeon_crtc->crtc_id) { |
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27 | case 0: |
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28 | WREG32(RADEON_MM_INDEX, RADEON_CRTC_GEN_CNTL); |
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29 | break; |
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30 | case 1: |
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31 | WREG32(RADEON_MM_INDEX, RADEON_CRTC2_GEN_CNTL); |
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32 | break; |
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33 | default: |
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34 | return; |
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35 | } |
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36 | |||
37 | |||
38 | (RADEON_CRTC_CUR_MODE_24BPP << RADEON_CRTC_CUR_MODE_SHIFT)), |
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39 | ~(RADEON_CRTC_CUR_EN | RADEON_CRTC_CUR_MODE_MASK)); |
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40 | } |
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41 | } |
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42 | |||
43 | |||
44 | { |
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45 | struct radeon_device *rdev = crtc->dev->dev_private; |
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46 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
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47 | uint32_t cur_lock; |
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48 | |||
49 | |||
50 | cur_lock = RREG32(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset); |
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51 | if (lock) |
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52 | cur_lock |= AVIVO_D1CURSOR_UPDATE_LOCK; |
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53 | else |
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54 | cur_lock &= ~AVIVO_D1CURSOR_UPDATE_LOCK; |
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55 | WREG32(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset, cur_lock); |
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56 | } else { |
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57 | cur_lock = RREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset); |
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58 | if (lock) |
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59 | cur_lock |= RADEON_CUR_LOCK; |
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60 | else |
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61 | cur_lock &= ~RADEON_CUR_LOCK; |
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62 | WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, cur_lock); |
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63 | } |
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64 | } |
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65 | |||
66 | |||
67 | { |
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68 | struct radeon_device *rdev; |
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69 | struct radeon_crtc *radeon_crtc; |
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70 | cursor_t *old; |
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71 | uint32_t gpu_addr; |
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72 | |||
73 | |||
74 | radeon_crtc = to_radeon_crtc(rdisplay->crtc); |
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75 | |||
76 | |||
77 | |||
78 | |||
79 | gpu_addr = cursor->robj->gpu_addr; |
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80 | |||
81 | |||
82 | WREG32(AVIVO_D1CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset, gpu_addr); |
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83 | else { |
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84 | radeon_crtc->legacy_cursor_offset = gpu_addr - radeon_crtc->legacy_display_base_addr; |
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85 | /* offset is from DISP(2)_BASE_ADDRESS */ |
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86 | WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, radeon_crtc->legacy_cursor_offset); |
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87 | } |
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88 | |||
89 | |||
90 | }; |
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91 | |||
92 | |||
93 | { |
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94 | struct radeon_device *rdev; |
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95 | rdev = (struct radeon_device *)rdisplay->ddev->dev_private; |
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96 | struct drm_crtc *crtc = rdisplay->crtc; |
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97 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
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98 | |||
99 | |||
100 | int hot_y = cursor->hot_y; |
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101 | |||
102 | |||
103 | if (ASIC_IS_AVIVO(rdev)) |
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104 | { |
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105 | int w = 32; |
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106 | int i = 0; |
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107 | struct drm_crtc *crtc_p; |
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108 | |||
109 | |||
110 | // x += crtc->x; |
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111 | // y += crtc->y; |
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112 | |||
113 | |||
114 | #if 0 |
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115 | /* avivo cursor image can't end on 128 pixel boundry or |
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116 | * go past the end of the frame if both crtcs are enabled |
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117 | */ |
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118 | list_for_each_entry(crtc_p, &crtc->dev->mode_config.crtc_list, head) { |
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119 | if (crtc_p->enabled) |
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120 | i++; |
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121 | } |
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122 | if (i > 1) { |
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123 | int cursor_end, frame_end; |
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124 | |||
125 | |||
126 | frame_end = crtc->x + crtc->mode.crtc_hdisplay; |
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127 | if (cursor_end >= frame_end) { |
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128 | w = w - (cursor_end - frame_end); |
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129 | if (!(frame_end & 0x7f)) |
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130 | w--; |
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131 | } else { |
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132 | if (!(cursor_end & 0x7f)) |
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133 | w--; |
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134 | } |
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135 | if (w <= 0) |
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136 | w = 1; |
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137 | } |
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138 | #endif |
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139 | WREG32(AVIVO_D1CUR_POSITION + radeon_crtc->crtc_offset, |
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140 | (x << 16) | y); |
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141 | WREG32(AVIVO_D1CUR_HOT_SPOT + radeon_crtc->crtc_offset, |
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142 | (hot_x << 16) | hot_y); |
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143 | WREG32(AVIVO_D1CUR_SIZE + radeon_crtc->crtc_offset, |
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144 | ((w - 1) << 16) | 31); |
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145 | } else { |
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146 | if (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN) |
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147 | y *= 2; |
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148 | |||
149 | |||
150 | (RADEON_CUR_LOCK | (hot_x << 16) | (hot_y << 16))); |
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151 | WREG32(RADEON_CUR_HORZ_VERT_POSN + radeon_crtc->crtc_offset, |
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152 | (RADEON_CUR_LOCK | (x << 16) | y)); |
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153 | |||
154 | |||
155 | WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, |
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156 | (radeon_crtc->legacy_cursor_offset + (hot_y * 256))); |
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157 | } |
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158 | radeon_lock_cursor_kms(crtc, false); |
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159 | } |
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160 | |||
161 | |||
162 | { |
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163 | static char name[4]; |
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164 | |||
165 | |||
166 | name[1] = ((x[0] & 0x03) << 3) + ((x[1] & 0xE0) >> 5) + '@'; |
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167 | name[2] = (x[1] & 0x1F) + '@'; |
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168 | name[3] = 0; |
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169 | |||
170 | |||
171 | } |
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172 | |||
173 | |||
174 | mode_t *reqmode, bool strict) |
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175 | { |
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176 | struct drm_display_mode *mode = NULL, *tmpmode; |
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177 | |||
178 | |||
179 | |||
180 | |||
181 | |||
182 | |||
183 | reqmode->width, reqmode->height, reqmode->freq); |
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184 | |||
185 | |||
186 | { |
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187 | if( (drm_mode_width(tmpmode) == reqmode->width) && |
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188 | (drm_mode_height(tmpmode) == reqmode->height) && |
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189 | (drm_mode_vrefresh(tmpmode) == reqmode->freq) ) |
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190 | { |
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191 | mode = tmpmode; |
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192 | goto do_set; |
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193 | } |
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194 | }; |
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195 | |||
196 | |||
197 | { |
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198 | list_for_each_entry(tmpmode, &connector->modes, head) |
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199 | { |
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200 | if( (drm_mode_width(tmpmode) == reqmode->width) && |
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201 | (drm_mode_height(tmpmode) == reqmode->height) ) |
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202 | { |
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203 | mode = tmpmode; |
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204 | goto do_set; |
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205 | } |
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206 | }; |
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207 | }; |
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208 | |||
209 | |||
210 | |||
211 | |||
212 | { |
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213 | struct drm_framebuffer *fb; |
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214 | struct drm_encoder *encoder; |
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215 | struct drm_crtc *crtc; |
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216 | |||
217 | |||
218 | char *con_name; |
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219 | char *enc_name; |
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220 | |||
221 | |||
222 | crtc = encoder->crtc; |
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223 | |||
224 | |||
225 | struct drm_framebuffer, filp_head); |
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226 | |||
227 | |||
228 | |||
229 | |||
230 | // manufacturer_name(con_edid + 0x08), |
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231 | // (unsigned short)(con_edid[0x0A] + (con_edid[0x0B] << 8)), |
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232 | // (unsigned int)(con_edid[0x0C] + (con_edid[0x0D] << 8) |
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233 | // + (con_edid[0x0E] << 16) + (con_edid[0x0F] << 24))); |
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234 | |||
235 | |||
236 | enc_name = drm_get_encoder_name(encoder); |
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237 | |||
238 | |||
239 | reqmode->width, reqmode->height, con_name, enc_name); |
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240 | |||
241 | |||
242 | fb->height = reqmode->height; |
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243 | fb->pitch = radeon_align_pitch(dev->dev_private, reqmode->width, 32, false) * ((32 + 1) / 8); |
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244 | |||
245 | |||
246 | crtc->enabled = true; |
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247 | rdisplay->crtc = crtc; |
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248 | |||
249 | |||
250 | |||
251 | |||
252 | radeon_show_cursor_kms(crtc); |
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253 | |||
254 | |||
255 | { |
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256 | rdisplay->width = fb->width; |
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257 | rdisplay->height = fb->height; |
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258 | rdisplay->pitch = fb->pitch; |
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259 | rdisplay->vrefresh = drm_mode_vrefresh(mode); |
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260 | |||
261 | |||
262 | |||
263 | |||
264 | fb->width, fb->height, fb->pitch); |
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265 | } |
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266 | else |
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267 | DRM_ERROR("failed to set mode %d_%d on crtc %p\n", |
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268 | fb->width, fb->height, crtc); |
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269 | } |
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270 | |||
271 | |||
272 | return ret; |
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273 | }; |
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274 | |||
275 | |||
276 | { |
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277 | struct drm_display_mode *mode; |
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278 | int count = 0; |
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279 | |||
280 | |||
281 | { |
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282 | count++; |
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283 | }; |
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284 | return count; |
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285 | }; |
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286 | |||
287 | |||
288 | { |
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289 | struct drm_connector *connector; |
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290 | struct drm_connector *def_connector = NULL; |
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291 | |||
292 | |||
293 | { |
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294 | struct drm_encoder *encoder; |
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295 | struct drm_crtc *crtc; |
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296 | |||
297 | |||
298 | continue; |
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299 | |||
300 | |||
301 | if( encoder == NULL) |
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302 | continue; |
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303 | |||
304 | |||
305 | if(crtc == NULL) |
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306 | continue; |
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307 | |||
308 | |||
309 | break; |
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310 | }; |
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311 | |||
312 | |||
313 | }; |
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314 | |||
315 | |||
316 | { |
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317 | struct drm_device *dev; |
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318 | |||
319 | |||
320 | bool retval = false; |
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321 | u32_t ifl; |
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322 | |||
323 | |||
324 | |||
325 | |||
326 | |||
327 | |||
328 | |||
329 | |||
330 | { |
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331 | list_for_each_entry(cursor, &rdisplay->cursors, list) |
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332 | { |
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333 | init_cursor(cursor); |
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334 | }; |
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335 | }; |
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336 | safe_sti(ifl); |
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337 | |||
338 | |||
339 | if( rdisplay->connector == 0 ) |
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340 | { |
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341 | dbgprintf("no active connectors\n"); |
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342 | return false; |
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343 | }; |
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344 | |||
345 | |||
346 | rdisplay->supported_modes = count_connector_modes(rdisplay->connector); |
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347 | |||
348 | |||
1268 | serge | 349 | rdisplay->width, rdisplay->height, rdisplay->vrefresh); |
350 | dbgprintf("user mode mode %d x %d x %d\n", |
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351 | usermode->width, usermode->height, usermode->freq); |
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352 | |||
353 | |||
1246 | serge | 354 | (usermode->height != 0) && |
355 | ( (usermode->width != rdisplay->width) || |
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356 | (usermode->height != rdisplay->height) || |
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357 | (usermode->freq != rdisplay->vrefresh) ) ) |
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358 | { |
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359 | |||
360 | |||
361 | } |
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362 | |||
363 | |||
364 | { |
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365 | rdisplay->restore_cursor(0,0); |
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366 | rdisplay->init_cursor = init_cursor; |
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367 | rdisplay->select_cursor = select_cursor_kms; |
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368 | rdisplay->show_cursor = NULL; |
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369 | rdisplay->move_cursor = move_cursor_kms; |
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370 | rdisplay->restore_cursor = restore_cursor; |
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371 | |||
1268 | serge | 372 | |
373 | radeon_show_cursor_kms(rdisplay->crtc); |
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1246 | serge | 374 | }; |
375 | safe_sti(ifl); |
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376 | |||
377 | |||
378 | |||
379 | |||
380 | }; |
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381 | |||
382 | |||
383 | { |
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384 | int err = -1; |
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385 | |||
386 | |||
387 | |||
388 | |||
389 | |||
390 | |||
391 | { |
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392 | *count = rdisplay->supported_modes; |
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393 | err = 0; |
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394 | } |
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395 | else if( mode != NULL ) |
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396 | { |
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397 | struct drm_display_mode *drmmode; |
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398 | int i = 0; |
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399 | |||
400 | |||
401 | *count = rdisplay->supported_modes; |
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402 | |||
403 | |||
404 | { |
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405 | if( i < *count) |
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406 | { |
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407 | mode->width = drm_mode_width(drmmode); |
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408 | mode->height = drm_mode_height(drmmode); |
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409 | mode->bpp = 32; |
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410 | mode->freq = drm_mode_vrefresh(drmmode); |
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411 | i++; |
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412 | mode++; |
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413 | } |
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414 | else break; |
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415 | }; |
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416 | *count = i; |
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417 | err = 0; |
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418 | }; |
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419 | LEAVE(); |
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420 | return err; |
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421 | } |
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422 | |||
423 | |||
424 | { |
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425 | int err = -1; |
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426 | |||
427 | |||
428 | |||
429 | |||
430 | mode->width, mode->height, mode->freq); |
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431 | |||
432 | |||
433 | (mode->height != 0) && |
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434 | (mode->freq != 0 ) && |
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435 | ( (mode->width != rdisplay->width) || |
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436 | (mode->height != rdisplay->height) || |
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437 | (mode->freq != rdisplay->vrefresh) ) ) |
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438 | { |
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439 | if( set_mode(rdisplay->ddev, rdisplay->connector, mode, true) ) |
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440 | err = 0; |
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441 | }; |
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442 | |||
443 | |||
444 | return err; |
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445 | };>><>><>><>><>><>><>><>><>><>><>><>=>><>><> |
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446 |