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Rev | Author | Line No. | Line |
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1221 | serge | 1 | |
2 | #include |
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3 | #include |
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4 | #include |
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5 | #include "radeon_drm.h" |
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6 | #include "radeon.h" |
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7 | #include "radeon_object.h" |
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8 | #include "display.h" |
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1246 | serge | 9 | |
1221 | serge | 10 | |
1246 | serge | 11 | |
1221 | serge | 12 | |
1246 | serge | 13 | static void __stdcall move_cursor(cursor_t *cursor, int x, int y); |
14 | |||
1221 | serge | 15 | |
1313 | serge | 16 | |
17 | |||
18 | {}; |
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19 | |||
20 | |||
1221 | serge | 21 | { |
22 | struct radeon_device *rdev; |
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23 | |||
24 | |||
25 | uint32_t *src; |
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26 | |||
27 | |||
28 | int r; |
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29 | |||
30 | |||
31 | |||
32 | |||
33 | false, |
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34 | RADEON_GEM_DOMAIN_VRAM, |
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35 | false, &cursor->robj); |
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36 | |||
37 | |||
38 | return r; |
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39 | |||
40 | |||
1246 | serge | 41 | |
1221 | serge | 42 | |
43 | if (r) { |
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44 | DRM_ERROR("radeon: failed to map cursor (%d).\n", r); |
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45 | return r; |
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46 | }; |
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47 | |||
48 | |||
49 | |||
50 | |||
51 | { |
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52 | for(j = 0; j < 32; j++) |
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53 | *bits++ = *src++; |
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54 | for(j = 32; j < CURSOR_WIDTH; j++) |
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1230 | serge | 55 | *bits++ = 0; |
1221 | serge | 56 | } |
57 | for(i = 0; i < CURSOR_WIDTH*(CURSOR_HEIGHT-32); i++) |
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58 | *bits++ = 0; |
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59 | |||
60 | |||
61 | |||
62 | |||
1313 | serge | 63 | |
64 | |||
1221 | serge | 65 | }; |
66 | |||
67 | |||
1313 | serge | 68 | { |
69 | list_del(&cursor->list); |
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70 | radeon_object_unpin(cursor->robj); |
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71 | KernelFree(cursor->data); |
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72 | __DestroyObject(cursor); |
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73 | }; |
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74 | |||
75 | |||
76 | |||
1246 | serge | 77 | { |
1221 | serge | 78 | struct radeon_device *rdev = (struct radeon_device *)rdisplay->ddev->dev_private; |
1246 | serge | 79 | |
1230 | serge | 80 | |
81 | WREG32(RADEON_MM_INDEX, AVIVO_D1CUR_CONTROL); |
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1246 | serge | 82 | WREG32(RADEON_MM_DATA, AVIVO_D1CURSOR_EN | |
1230 | serge | 83 | (AVIVO_D1CURSOR_MODE_24BPP << AVIVO_D1CURSOR_MODE_SHIFT)); |
84 | } else { |
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85 | WREG32(RADEON_MM_INDEX, RADEON_CRTC_GEN_CNTL); |
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1275 | serge | 86 | WREG32_P(RADEON_MM_DATA, (RADEON_CRTC_CUR_EN | |
1230 | serge | 87 | (RADEON_CRTC_CUR_MODE_24BPP << RADEON_CRTC_CUR_MODE_SHIFT)), |
88 | ~(RADEON_CRTC_CUR_EN | RADEON_CRTC_CUR_MODE_MASK)); |
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89 | } |
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90 | } |
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91 | |||
92 | |||
93 | { |
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1221 | serge | 94 | struct radeon_device *rdev; |
95 | cursor_t *old; |
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96 | uint32_t gpu_addr; |
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97 | |||
98 | |||
99 | |||
100 | |||
1230 | serge | 101 | |
1221 | serge | 102 | |
1230 | serge | 103 | gpu_addr = cursor->robj->gpu_addr; |
1221 | serge | 104 | |
105 | |||
106 | WREG32(AVIVO_D1CUR_SURFACE_ADDRESS, gpu_addr); |
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1246 | serge | 107 | else { |
1221 | serge | 108 | WREG32(RADEON_CUR_OFFSET, gpu_addr - rdev->mc.vram_location); |
1246 | serge | 109 | } |
1221 | serge | 110 | |
1230 | serge | 111 | |
1221 | serge | 112 | }; |
113 | |||
114 | |||
1246 | serge | 115 | { |
116 | struct radeon_device *rdev; |
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117 | |||
1221 | serge | 118 | |
1246 | serge | 119 | |
120 | |||
121 | |||
122 | |||
123 | cur_lock = RREG32(AVIVO_D1CUR_UPDATE); |
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124 | if (lock) |
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125 | cur_lock |= AVIVO_D1CURSOR_UPDATE_LOCK; |
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126 | else |
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127 | cur_lock &= ~AVIVO_D1CURSOR_UPDATE_LOCK; |
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128 | WREG32(AVIVO_D1CUR_UPDATE, cur_lock); |
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129 | } else { |
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130 | cur_lock = RREG32(RADEON_CUR_OFFSET); |
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131 | if (lock) |
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132 | cur_lock |= RADEON_CUR_LOCK; |
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133 | else |
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134 | cur_lock &= ~RADEON_CUR_LOCK; |
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135 | WREG32(RADEON_CUR_OFFSET, cur_lock); |
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136 | } |
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137 | } |
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138 | |||
139 | |||
140 | |||
1230 | serge | 141 | { |
1221 | serge | 142 | struct radeon_device *rdev; |
1230 | serge | 143 | rdev = (struct radeon_device *)rdisplay->ddev->dev_private; |
144 | |||
1221 | serge | 145 | |
1230 | serge | 146 | int hot_y = cursor->hot_y; |
147 | |||
1221 | serge | 148 | |
1246 | serge | 149 | if (ASIC_IS_AVIVO(rdev)) |
1221 | serge | 150 | { |
151 | int w = 32; |
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152 | int i = 0; |
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153 | |||
154 | |||
1246 | serge | 155 | WREG32(AVIVO_D1CUR_HOT_SPOT, (hot_x << 16) | hot_y); |
156 | WREG32(AVIVO_D1CUR_SIZE, ((w - 1) << 16) | 31); |
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157 | } else { |
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1275 | serge | 158 | uint32_t gpu_addr; |
1246 | serge | 159 | |
1221 | serge | 160 | |
1246 | serge | 161 | (RADEON_CUR_LOCK | (hot_x << 16) | hot_y )); |
1275 | serge | 162 | WREG32(RADEON_CUR_HORZ_VERT_POSN, |
1246 | serge | 163 | (RADEON_CUR_LOCK | (x << 16) | y)); |
1221 | serge | 164 | |
165 | |||
1246 | serge | 166 | |
167 | |||
1221 | serge | 168 | WREG32(RADEON_CUR_OFFSET, |
1246 | serge | 169 | (gpu_addr - rdev->mc.vram_location + (hot_y * 256))); |
170 | } |
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1221 | serge | 171 | radeon_lock_cursor(false); |
1246 | serge | 172 | } |
1221 | serge | 173 | |
174 | |||
1230 | serge | 175 | { |
176 | }; |
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177 | |||
1221 | serge | 178 | |
1233 | serge | 179 | |
1239 | serge | 180 | { |
1233 | serge | 181 | struct drm_device *dev; |
1275 | serge | 182 | |
1246 | serge | 183 | |
1275 | serge | 184 | bool retval = true; |
1268 | serge | 185 | u32_t ifl; |
1246 | serge | 186 | |
1233 | serge | 187 | |
188 | |||
189 | |||
190 | |||
191 | |||
1239 | serge | 192 | |
1233 | serge | 193 | |
1246 | serge | 194 | { |
195 | list_for_each_entry(cursor, &rdisplay->cursors, list) |
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1275 | serge | 196 | { |
197 | init_cursor(cursor); |
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198 | }; |
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199 | |||
1233 | serge | 200 | |
1275 | serge | 201 | rdisplay->init_cursor = init_cursor; |
202 | rdisplay->select_cursor = select_cursor; |
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203 | rdisplay->show_cursor = NULL; |
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204 | rdisplay->move_cursor = move_cursor; |
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205 | rdisplay->restore_cursor = restore_cursor; |
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206 | rdisplay->disable_mouse = disable_mouse; |
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1313 | serge | 207 | |
1233 | serge | 208 | |
1246 | serge | 209 | radeon_show_cursor(); |
210 | }; |
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211 | safe_sti(ifl); |
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212 | |||
213 | |||
1233 | serge | 214 | |
215 | |||
1239 | serge | 216 | };><>><>><>><>><>><>><>>>>> |
1233 | serge | 217 |