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#include 

#include 

#include 

#include "radeon_drm.h"

#include "radeon.h"

#include "radeon_object.h"

#define CURSOR_HEIGHT 64

typedef struct tag_display display_t;

{

    uint32_t   magic;

    void      *destroy;

    kobj_t    *fd;

    kobj_t    *bk;

    uint32_t   pid;

};

{

    kobj_t     header;

    uint32_t   hot_x;

    uint32_t   hot_y;

    struct radeon_object *robj;

}cursor_t;

{

    int  x;

    int  y;

    int  width;

    int  height;

    int  bpp;

    int  vrefresh;

    int  pitch;

    int  lfb;

    struct drm_crtc   *crtc;

    int       (*init_cursor)(cursor_t*);

    cursor_t* (*select_cursor)(display_t*, cursor_t*);

    void      (*show_cursor)(int show);

    void      (*move_cursor)(int x, int y);

};

{

    struct radeon_device *rdev;

    uint32_t *src;

    int       r;

                     false,

                     RADEON_GEM_DOMAIN_VRAM,

                     false, &cursor->robj);

        return r;

    if (r) {

         DRM_ERROR("radeon: failed to map cursor (%d).\n", r);

         return r;

    };

    {

        for(j = 0; j < 32; j++)

            *bits++ = *src++;

        for(j = 0; j < CURSOR_WIDTH-32; j++)

            *bits++ = 0;

    }

    for(i = 0; i < CURSOR_WIDTH*(CURSOR_HEIGHT-32); i++)

        *bits++ = 0;

};

{

    cursor_t  *cursor;

    {

        init_cursor(cursor);

    };

    return 1;

};

{

    struct radeon_device *rdev = crtc->dev->dev_private;

    struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

    uint32_t cur_lock;

        cur_lock = RREG32(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset);

        if (lock)

            cur_lock |= AVIVO_D1CURSOR_UPDATE_LOCK;

        else

            cur_lock &= ~AVIVO_D1CURSOR_UPDATE_LOCK;

        WREG32(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset, cur_lock);

    } else {

        cur_lock = RREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset);

        if (lock)

            cur_lock |= RADEON_CUR_LOCK;

        else

            cur_lock &= ~RADEON_CUR_LOCK;

        WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, cur_lock);

    }

}

{

    struct radeon_device *rdev;

    struct radeon_crtc   *radeon_crtc;

    cursor_t *old;

    uint32_t  gpu_addr;

    radeon_crtc = to_radeon_crtc(rdisplay->crtc);

    gpu_addr = cursor->robj->gpu_addr;

        WREG32(AVIVO_D1CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset, gpu_addr);

    else {

        radeon_crtc->legacy_cursor_offset = gpu_addr - radeon_crtc->legacy_display_base_addr;

        /* offset is from DISP(2)_BASE_ADDRESS */

        WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, radeon_crtc->legacy_cursor_offset);

    }

    return old;

};

{

    struct drm_crtc *crtc = rdisplay->crtc;

    struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

    struct radeon_device *rdev = crtc->dev->dev_private;

    int hot_y = rdisplay->cursor->hot_y - 1;

    if (ASIC_IS_AVIVO(rdev))

    {

        int w = 32;

        int i = 0;

        struct drm_crtc *crtc_p;

        x += crtc->x;

        y += crtc->y;

#if 0

        /* avivo cursor image can't end on 128 pixel boundry or

         * go past the end of the frame if both crtcs are enabled

         */

        list_for_each_entry(crtc_p, &crtc->dev->mode_config.crtc_list, head) {

            if (crtc_p->enabled)

                i++;

        }

        if (i > 1) {

            int cursor_end, frame_end;

            frame_end = crtc->x + crtc->mode.crtc_hdisplay;

            if (cursor_end >= frame_end) {

                w = w - (cursor_end - frame_end);

                if (!(frame_end & 0x7f))

                    w--;

            } else {

                if (!(cursor_end & 0x7f))

                    w--;

            }

            if (w <= 0)

                w = 1;

        }

#endif

               (x << 16) | y);

        WREG32(AVIVO_D1CUR_HOT_SPOT + radeon_crtc->crtc_offset,

               (hot_x << 16) | hot_y-1);

        WREG32(AVIVO_D1CUR_SIZE + radeon_crtc->crtc_offset,

               ((w - 1) << 16) | 31);

    } else {

        if (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)

            y *= 2;

               (RADEON_CUR_LOCK | (hot_x << 16) | (hot_y << 16)));

        WREG32(RADEON_CUR_HORZ_VERT_POSN + radeon_crtc->crtc_offset,

               (RADEON_CUR_LOCK | (x << 16) | y));

        WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset,

         (radeon_crtc->legacy_cursor_offset + (hot_y * 256)));

    }

    radeon_lock_cursor(crtc, false);

}