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| Rev | Author | Line No. | Line |
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| 5078 | serge | 1 | /* |
| 2 | * Copyright 2012 Advanced Micro Devices, Inc. |
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| 3 | * |
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| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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| 5 | * copy of this software and associated documentation files (the "Software"), |
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| 6 | * to deal in the Software without restriction, including without limitation |
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| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
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| 9 | * Software is furnished to do so, subject to the following conditions: |
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| 10 | * |
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| 11 | * The above copyright notice and this permission notice shall be included in |
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| 12 | * all copies or substantial portions of the Software. |
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| 13 | * |
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| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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| 20 | * OTHER DEALINGS IN THE SOFTWARE. |
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| 21 | * |
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| 22 | */ |
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| 23 | #ifndef __RADEON_UCODE_H__ |
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| 24 | #define __RADEON_UCODE_H__ |
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| 25 | |||
| 26 | /* CP */ |
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| 27 | #define R600_PFP_UCODE_SIZE 576 |
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| 28 | #define R600_PM4_UCODE_SIZE 1792 |
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| 29 | #define R700_PFP_UCODE_SIZE 848 |
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| 30 | #define R700_PM4_UCODE_SIZE 1360 |
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| 31 | #define EVERGREEN_PFP_UCODE_SIZE 1120 |
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| 32 | #define EVERGREEN_PM4_UCODE_SIZE 1376 |
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| 33 | #define CAYMAN_PFP_UCODE_SIZE 2176 |
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| 34 | #define CAYMAN_PM4_UCODE_SIZE 2176 |
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| 35 | #define SI_PFP_UCODE_SIZE 2144 |
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| 36 | #define SI_PM4_UCODE_SIZE 2144 |
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| 37 | #define SI_CE_UCODE_SIZE 2144 |
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| 38 | #define CIK_PFP_UCODE_SIZE 2144 |
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| 39 | #define CIK_ME_UCODE_SIZE 2144 |
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| 40 | #define CIK_CE_UCODE_SIZE 2144 |
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| 41 | |||
| 42 | /* MEC */ |
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| 43 | #define CIK_MEC_UCODE_SIZE 4192 |
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| 44 | |||
| 45 | /* RLC */ |
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| 46 | #define R600_RLC_UCODE_SIZE 768 |
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| 47 | #define R700_RLC_UCODE_SIZE 1024 |
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| 48 | #define EVERGREEN_RLC_UCODE_SIZE 768 |
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| 49 | #define CAYMAN_RLC_UCODE_SIZE 1024 |
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| 50 | #define ARUBA_RLC_UCODE_SIZE 1536 |
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| 51 | #define SI_RLC_UCODE_SIZE 2048 |
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| 52 | #define BONAIRE_RLC_UCODE_SIZE 2048 |
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| 53 | #define KB_RLC_UCODE_SIZE 2560 |
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| 54 | #define KV_RLC_UCODE_SIZE 2560 |
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| 55 | #define ML_RLC_UCODE_SIZE 2560 |
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| 56 | |||
| 57 | /* MC */ |
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| 58 | #define BTC_MC_UCODE_SIZE 6024 |
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| 59 | #define CAYMAN_MC_UCODE_SIZE 6037 |
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| 60 | #define SI_MC_UCODE_SIZE 7769 |
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| 61 | #define TAHITI_MC_UCODE_SIZE 7808 |
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| 62 | #define PITCAIRN_MC_UCODE_SIZE 7775 |
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| 63 | #define VERDE_MC_UCODE_SIZE 7875 |
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| 64 | #define OLAND_MC_UCODE_SIZE 7863 |
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| 65 | #define BONAIRE_MC_UCODE_SIZE 7866 |
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| 66 | #define BONAIRE_MC2_UCODE_SIZE 7948 |
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| 67 | #define HAWAII_MC_UCODE_SIZE 7933 |
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| 68 | #define HAWAII_MC2_UCODE_SIZE 8091 |
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| 69 | |||
| 70 | /* SDMA */ |
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| 71 | #define CIK_SDMA_UCODE_SIZE 1050 |
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| 72 | #define CIK_SDMA_UCODE_VERSION 64 |
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| 73 | |||
| 74 | /* SMC */ |
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| 75 | #define RV770_SMC_UCODE_START 0x0100 |
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| 76 | #define RV770_SMC_UCODE_SIZE 0x410d |
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| 77 | #define RV770_SMC_INT_VECTOR_START 0xffc0 |
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| 78 | #define RV770_SMC_INT_VECTOR_SIZE 0x0040 |
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| 79 | |||
| 80 | #define RV730_SMC_UCODE_START 0x0100 |
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| 81 | #define RV730_SMC_UCODE_SIZE 0x412c |
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| 82 | #define RV730_SMC_INT_VECTOR_START 0xffc0 |
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| 83 | #define RV730_SMC_INT_VECTOR_SIZE 0x0040 |
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| 84 | |||
| 85 | #define RV710_SMC_UCODE_START 0x0100 |
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| 86 | #define RV710_SMC_UCODE_SIZE 0x3f1f |
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| 87 | #define RV710_SMC_INT_VECTOR_START 0xffc0 |
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| 88 | #define RV710_SMC_INT_VECTOR_SIZE 0x0040 |
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| 89 | |||
| 90 | #define RV740_SMC_UCODE_START 0x0100 |
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| 91 | #define RV740_SMC_UCODE_SIZE 0x41c5 |
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| 92 | #define RV740_SMC_INT_VECTOR_START 0xffc0 |
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| 93 | #define RV740_SMC_INT_VECTOR_SIZE 0x0040 |
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| 94 | |||
| 95 | #define CEDAR_SMC_UCODE_START 0x0100 |
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| 96 | #define CEDAR_SMC_UCODE_SIZE 0x5d50 |
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| 97 | #define CEDAR_SMC_INT_VECTOR_START 0xffc0 |
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| 98 | #define CEDAR_SMC_INT_VECTOR_SIZE 0x0040 |
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| 99 | |||
| 100 | #define REDWOOD_SMC_UCODE_START 0x0100 |
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| 101 | #define REDWOOD_SMC_UCODE_SIZE 0x5f0a |
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| 102 | #define REDWOOD_SMC_INT_VECTOR_START 0xffc0 |
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| 103 | #define REDWOOD_SMC_INT_VECTOR_SIZE 0x0040 |
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| 104 | |||
| 105 | #define JUNIPER_SMC_UCODE_START 0x0100 |
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| 106 | #define JUNIPER_SMC_UCODE_SIZE 0x5f1f |
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| 107 | #define JUNIPER_SMC_INT_VECTOR_START 0xffc0 |
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| 108 | #define JUNIPER_SMC_INT_VECTOR_SIZE 0x0040 |
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| 109 | |||
| 110 | #define CYPRESS_SMC_UCODE_START 0x0100 |
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| 111 | #define CYPRESS_SMC_UCODE_SIZE 0x61f7 |
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| 112 | #define CYPRESS_SMC_INT_VECTOR_START 0xffc0 |
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| 113 | #define CYPRESS_SMC_INT_VECTOR_SIZE 0x0040 |
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| 114 | |||
| 115 | #define BARTS_SMC_UCODE_START 0x0100 |
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| 116 | #define BARTS_SMC_UCODE_SIZE 0x6107 |
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| 117 | #define BARTS_SMC_INT_VECTOR_START 0xffc0 |
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| 118 | #define BARTS_SMC_INT_VECTOR_SIZE 0x0040 |
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| 119 | |||
| 120 | #define TURKS_SMC_UCODE_START 0x0100 |
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| 121 | #define TURKS_SMC_UCODE_SIZE 0x605b |
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| 122 | #define TURKS_SMC_INT_VECTOR_START 0xffc0 |
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| 123 | #define TURKS_SMC_INT_VECTOR_SIZE 0x0040 |
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| 124 | |||
| 125 | #define CAICOS_SMC_UCODE_START 0x0100 |
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| 126 | #define CAICOS_SMC_UCODE_SIZE 0x5fbd |
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| 127 | #define CAICOS_SMC_INT_VECTOR_START 0xffc0 |
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| 128 | #define CAICOS_SMC_INT_VECTOR_SIZE 0x0040 |
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| 129 | |||
| 130 | #define CAYMAN_SMC_UCODE_START 0x0100 |
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| 131 | #define CAYMAN_SMC_UCODE_SIZE 0x79ec |
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| 132 | #define CAYMAN_SMC_INT_VECTOR_START 0xffc0 |
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| 133 | #define CAYMAN_SMC_INT_VECTOR_SIZE 0x0040 |
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| 134 | |||
| 135 | #define TAHITI_SMC_UCODE_START 0x10000 |
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| 136 | #define TAHITI_SMC_UCODE_SIZE 0xf458 |
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| 137 | |||
| 138 | #define PITCAIRN_SMC_UCODE_START 0x10000 |
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| 139 | #define PITCAIRN_SMC_UCODE_SIZE 0xe9f4 |
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| 140 | |||
| 141 | #define VERDE_SMC_UCODE_START 0x10000 |
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| 142 | #define VERDE_SMC_UCODE_SIZE 0xebe4 |
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| 143 | |||
| 144 | #define OLAND_SMC_UCODE_START 0x10000 |
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| 145 | #define OLAND_SMC_UCODE_SIZE 0xe7b4 |
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| 146 | |||
| 147 | #define HAINAN_SMC_UCODE_START 0x10000 |
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| 148 | #define HAINAN_SMC_UCODE_SIZE 0xe67C |
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| 149 | |||
| 150 | #define BONAIRE_SMC_UCODE_START 0x20000 |
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| 151 | #define BONAIRE_SMC_UCODE_SIZE 0x1FDEC |
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| 152 | |||
| 153 | #define HAWAII_SMC_UCODE_START 0x20000 |
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| 154 | #define HAWAII_SMC_UCODE_SIZE 0x1FDEC |
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| 155 | |||
| 156 | struct common_firmware_header { |
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| 157 | uint32_t size_bytes; /* size of the entire header+image(s) in bytes */ |
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| 158 | uint32_t header_size_bytes; /* size of just the header in bytes */ |
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| 159 | uint16_t header_version_major; /* header version */ |
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| 160 | uint16_t header_version_minor; /* header version */ |
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| 161 | uint16_t ip_version_major; /* IP version */ |
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| 162 | uint16_t ip_version_minor; /* IP version */ |
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| 163 | uint32_t ucode_version; |
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| 164 | uint32_t ucode_size_bytes; /* size of ucode in bytes */ |
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| 165 | uint32_t ucode_array_offset_bytes; /* payload offset from the start of the header */ |
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| 166 | uint32_t crc32; /* crc32 checksum of the payload */ |
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| 167 | }; |
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| 168 | |||
| 169 | /* version_major=1, version_minor=0 */ |
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| 170 | struct mc_firmware_header_v1_0 { |
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| 171 | struct common_firmware_header header; |
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| 172 | uint32_t io_debug_size_bytes; /* size of debug array in dwords */ |
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| 173 | uint32_t io_debug_array_offset_bytes; /* payload offset from the start of the header */ |
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| 174 | }; |
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| 175 | |||
| 176 | /* version_major=1, version_minor=0 */ |
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| 177 | struct smc_firmware_header_v1_0 { |
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| 178 | struct common_firmware_header header; |
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| 179 | uint32_t ucode_start_addr; |
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| 180 | }; |
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| 181 | |||
| 182 | /* version_major=1, version_minor=0 */ |
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| 183 | struct gfx_firmware_header_v1_0 { |
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| 184 | struct common_firmware_header header; |
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| 185 | uint32_t ucode_feature_version; |
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| 186 | uint32_t jt_offset; /* jt location */ |
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| 187 | uint32_t jt_size; /* size of jt */ |
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| 188 | }; |
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| 189 | |||
| 190 | /* version_major=1, version_minor=0 */ |
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| 191 | struct rlc_firmware_header_v1_0 { |
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| 192 | struct common_firmware_header header; |
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| 193 | uint32_t ucode_feature_version; |
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| 194 | uint32_t save_and_restore_offset; |
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| 195 | uint32_t clear_state_descriptor_offset; |
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| 196 | uint32_t avail_scratch_ram_locations; |
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| 197 | uint32_t master_pkt_description_offset; |
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| 198 | }; |
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| 199 | |||
| 200 | /* version_major=1, version_minor=0 */ |
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| 201 | struct sdma_firmware_header_v1_0 { |
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| 202 | struct common_firmware_header header; |
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| 203 | uint32_t ucode_feature_version; |
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| 204 | uint32_t ucode_change_version; |
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| 205 | uint32_t jt_offset; /* jt location */ |
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| 206 | uint32_t jt_size; /* size of jt */ |
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| 207 | }; |
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| 208 | |||
| 209 | /* header is fixed size */ |
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| 210 | union radeon_firmware_header { |
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| 211 | struct common_firmware_header common; |
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| 212 | struct mc_firmware_header_v1_0 mc; |
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| 213 | struct smc_firmware_header_v1_0 smc; |
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| 214 | struct gfx_firmware_header_v1_0 gfx; |
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| 215 | struct rlc_firmware_header_v1_0 rlc; |
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| 216 | struct sdma_firmware_header_v1_0 sdma; |
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| 217 | uint8_t raw[0x100]; |
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| 218 | }; |
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| 219 | |||
| 220 | void radeon_ucode_print_mc_hdr(const struct common_firmware_header *hdr); |
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| 221 | void radeon_ucode_print_smc_hdr(const struct common_firmware_header *hdr); |
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| 222 | void radeon_ucode_print_gfx_hdr(const struct common_firmware_header *hdr); |
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| 223 | void radeon_ucode_print_rlc_hdr(const struct common_firmware_header *hdr); |
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| 224 | void radeon_ucode_print_sdma_hdr(const struct common_firmware_header *hdr); |
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| 225 | int radeon_ucode_validate(const struct firmware *fw); |
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| 226 | |||
| 227 | #endif |