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1404 | serge | 1 | /* |
2 | * Copyright 2009 Jerome Glisse. |
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3 | * All Rights Reserved. |
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4 | * |
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5 | * Permission is hereby granted, free of charge, to any person obtaining a |
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6 | * copy of this software and associated documentation files (the |
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7 | * "Software"), to deal in the Software without restriction, including |
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8 | * without limitation the rights to use, copy, modify, merge, publish, |
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9 | * distribute, sub license, and/or sell copies of the Software, and to |
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10 | * permit persons to whom the Software is furnished to do so, subject to |
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11 | * the following conditions: |
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12 | * |
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13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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14 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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15 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL |
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16 | * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, |
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17 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR |
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18 | * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE |
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19 | * USE OR OTHER DEALINGS IN THE SOFTWARE. |
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20 | * |
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21 | * The above copyright notice and this permission notice (including the |
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22 | * next paragraph) shall be included in all copies or substantial portions |
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23 | * of the Software. |
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24 | * |
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25 | */ |
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26 | /* |
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27 | * Authors: |
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28 | * Jerome Glisse |
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29 | * Thomas Hellstrom |
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30 | * Dave Airlie |
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31 | */ |
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32 | #include |
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33 | #include |
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34 | #include |
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35 | #include |
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2997 | Serge | 36 | #include |
1404 | serge | 37 | #include |
38 | #include |
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39 | #include |
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2997 | Serge | 40 | #include |
1404 | serge | 41 | #include "radeon_reg.h" |
42 | #include "radeon.h" |
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43 | |||
44 | #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT) |
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45 | |||
46 | static int radeon_ttm_debugfs_init(struct radeon_device *rdev); |
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47 | |||
48 | static struct radeon_device *radeon_get_rdev(struct ttm_bo_device *bdev) |
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49 | { |
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50 | struct radeon_mman *mman; |
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51 | struct radeon_device *rdev; |
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52 | |||
53 | mman = container_of(bdev, struct radeon_mman, bdev); |
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54 | rdev = container_of(mman, struct radeon_device, mman); |
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55 | return rdev; |
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56 | } |
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57 | |||
58 | |||
59 | /* |
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60 | * Global memory. |
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61 | */ |
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2997 | Serge | 62 | static int radeon_ttm_mem_global_init(struct drm_global_reference *ref) |
1404 | serge | 63 | { |
64 | return ttm_mem_global_init(ref->object); |
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65 | } |
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66 | |||
2997 | Serge | 67 | static void radeon_ttm_mem_global_release(struct drm_global_reference *ref) |
1404 | serge | 68 | { |
69 | ttm_mem_global_release(ref->object); |
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70 | } |
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71 | |||
72 | static int radeon_ttm_global_init(struct radeon_device *rdev) |
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73 | { |
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2997 | Serge | 74 | struct drm_global_reference *global_ref; |
1404 | serge | 75 | int r; |
76 | |||
77 | rdev->mman.mem_global_referenced = false; |
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78 | global_ref = &rdev->mman.mem_global_ref; |
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2997 | Serge | 79 | global_ref->global_type = DRM_GLOBAL_TTM_MEM; |
1404 | serge | 80 | global_ref->size = sizeof(struct ttm_mem_global); |
81 | global_ref->init = &radeon_ttm_mem_global_init; |
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82 | global_ref->release = &radeon_ttm_mem_global_release; |
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2997 | Serge | 83 | r = drm_global_item_ref(global_ref); |
1404 | serge | 84 | if (r != 0) { |
85 | DRM_ERROR("Failed setting up TTM memory accounting " |
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86 | "subsystem.\n"); |
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87 | return r; |
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88 | } |
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89 | |||
90 | rdev->mman.bo_global_ref.mem_glob = |
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91 | rdev->mman.mem_global_ref.object; |
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92 | global_ref = &rdev->mman.bo_global_ref.ref; |
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2997 | Serge | 93 | global_ref->global_type = DRM_GLOBAL_TTM_BO; |
1404 | serge | 94 | global_ref->size = sizeof(struct ttm_bo_global); |
95 | global_ref->init = &ttm_bo_global_init; |
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96 | global_ref->release = &ttm_bo_global_release; |
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2997 | Serge | 97 | r = drm_global_item_ref(global_ref); |
1404 | serge | 98 | if (r != 0) { |
99 | DRM_ERROR("Failed setting up TTM BO subsystem.\n"); |
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2997 | Serge | 100 | drm_global_item_unref(&rdev->mman.mem_global_ref); |
1404 | serge | 101 | return r; |
102 | } |
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103 | |||
104 | rdev->mman.mem_global_referenced = true; |
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105 | return 0; |
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106 | } |
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107 | |||
108 | |||
2997 | Serge | 109 | static int radeon_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags) |
110 | { |
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111 | return 0; |
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112 | } |
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1404 | serge | 113 | |
114 | static int radeon_init_mem_type(struct ttm_bo_device *bdev, uint32_t type, |
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115 | struct ttm_mem_type_manager *man) |
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116 | { |
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117 | struct radeon_device *rdev; |
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118 | |||
119 | rdev = radeon_get_rdev(bdev); |
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120 | |||
121 | switch (type) { |
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122 | case TTM_PL_SYSTEM: |
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123 | /* System memory */ |
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124 | man->flags = TTM_MEMTYPE_FLAG_MAPPABLE; |
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125 | man->available_caching = TTM_PL_MASK_CACHING; |
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126 | man->default_caching = TTM_PL_FLAG_CACHED; |
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127 | break; |
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128 | case TTM_PL_TT: |
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2997 | Serge | 129 | man->func = &ttm_bo_manager_func; |
130 | man->gpu_offset = rdev->mc.gtt_start; |
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1404 | serge | 131 | man->available_caching = TTM_PL_MASK_CACHING; |
132 | man->default_caching = TTM_PL_FLAG_CACHED; |
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133 | man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA; |
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134 | #if __OS_HAS_AGP |
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135 | if (rdev->flags & RADEON_IS_AGP) { |
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136 | if (!(drm_core_has_AGP(rdev->ddev) && rdev->ddev->agp)) { |
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137 | DRM_ERROR("AGP is not enabled for memory type %u\n", |
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138 | (unsigned)type); |
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139 | return -EINVAL; |
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140 | } |
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141 | if (!rdev->ddev->agp->cant_use_aperture) |
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2997 | Serge | 142 | man->flags = TTM_MEMTYPE_FLAG_MAPPABLE; |
1404 | serge | 143 | man->available_caching = TTM_PL_FLAG_UNCACHED | |
144 | TTM_PL_FLAG_WC; |
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145 | man->default_caching = TTM_PL_FLAG_WC; |
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2997 | Serge | 146 | } |
1404 | serge | 147 | #endif |
148 | break; |
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149 | case TTM_PL_VRAM: |
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150 | /* "On-card" video ram */ |
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2997 | Serge | 151 | man->func = &ttm_bo_manager_func; |
152 | man->gpu_offset = rdev->mc.vram_start; |
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1404 | serge | 153 | man->flags = TTM_MEMTYPE_FLAG_FIXED | |
154 | TTM_MEMTYPE_FLAG_MAPPABLE; |
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155 | man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC; |
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156 | man->default_caching = TTM_PL_FLAG_WC; |
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157 | break; |
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158 | default: |
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159 | DRM_ERROR("Unsupported memory type %u\n", (unsigned)type); |
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160 | return -EINVAL; |
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161 | } |
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162 | return 0; |
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163 | } |
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164 | |||
165 | static struct ttm_bo_driver radeon_bo_driver = { |
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166 | // .create_ttm_backend_entry = &radeon_create_ttm_backend_entry, |
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167 | // .invalidate_caches = &radeon_invalidate_caches, |
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168 | .init_mem_type = &radeon_init_mem_type, |
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169 | // .evict_flags = &radeon_evict_flags, |
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170 | // .move = &radeon_bo_move, |
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171 | // .verify_access = &radeon_verify_access, |
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172 | // .sync_obj_signaled = &radeon_sync_obj_signaled, |
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173 | // .sync_obj_wait = &radeon_sync_obj_wait, |
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174 | // .sync_obj_flush = &radeon_sync_obj_flush, |
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175 | // .sync_obj_unref = &radeon_sync_obj_unref, |
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176 | // .sync_obj_ref = &radeon_sync_obj_ref, |
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177 | // .move_notify = &radeon_bo_move_notify, |
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178 | // .fault_reserve_notify = &radeon_bo_fault_reserve_notify, |
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179 | }; |
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180 | |||
181 | int radeon_ttm_init(struct radeon_device *rdev) |
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182 | { |
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183 | int r; |
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184 | |||
185 | r = radeon_ttm_global_init(rdev); |
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186 | if (r) { |
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187 | return r; |
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188 | } |
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189 | /* No others user of address space so set it to 0 */ |
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190 | r = ttm_bo_device_init(&rdev->mman.bdev, |
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191 | rdev->mman.bo_global_ref.ref.object, |
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192 | &radeon_bo_driver, DRM_FILE_PAGE_OFFSET, |
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193 | rdev->need_dma32); |
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194 | if (r) { |
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195 | DRM_ERROR("failed initializing buffer object driver(%d).\n", r); |
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196 | return r; |
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197 | } |
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198 | rdev->mman.initialized = true; |
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199 | r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_VRAM, |
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200 | rdev->mc.real_vram_size >> PAGE_SHIFT); |
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201 | if (r) { |
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202 | DRM_ERROR("Failed initializing VRAM heap.\n"); |
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203 | return r; |
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204 | } |
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205 | r = radeon_bo_create(rdev, NULL, 256 * 1024, true, |
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206 | RADEON_GEM_DOMAIN_VRAM, |
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207 | &rdev->stollen_vga_memory); |
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208 | if (r) { |
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209 | return r; |
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210 | } |
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211 | r = radeon_bo_reserve(rdev->stollen_vga_memory, false); |
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212 | if (r) |
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213 | return r; |
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214 | r = radeon_bo_pin(rdev->stollen_vga_memory, RADEON_GEM_DOMAIN_VRAM, NULL); |
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215 | radeon_bo_unreserve(rdev->stollen_vga_memory); |
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216 | if (r) { |
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217 | radeon_bo_unref(&rdev->stollen_vga_memory); |
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218 | return r; |
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219 | } |
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220 | DRM_INFO("radeon: %uM of VRAM memory ready\n", |
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221 | (unsigned)rdev->mc.real_vram_size / (1024 * 1024)); |
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222 | r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_TT, |
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223 | rdev->mc.gtt_size >> PAGE_SHIFT); |
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224 | if (r) { |
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225 | DRM_ERROR("Failed initializing GTT heap.\n"); |
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226 | return r; |
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227 | } |
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228 | DRM_INFO("radeon: %uM of GTT memory ready.\n", |
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229 | (unsigned)(rdev->mc.gtt_size / (1024 * 1024))); |
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230 | if (unlikely(rdev->mman.bdev.dev_mapping == NULL)) { |
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231 | rdev->mman.bdev.dev_mapping = rdev->ddev->dev_mapping; |
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232 | } |
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233 | |||
234 | r = radeon_ttm_debugfs_init(rdev); |
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235 | if (r) { |
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236 | DRM_ERROR("Failed to init debugfs\n"); |
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237 | return r; |
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238 | } |
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239 | return 0; |
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240 | } |
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241 | |||
242 | static struct vm_operations_struct radeon_ttm_vm_ops; |
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243 | static const struct vm_operations_struct *ttm_vm_ops = NULL; |
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244 |