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1404 | serge | 1 | /* |
2 | * Copyright 2009 Jerome Glisse. |
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3 | * All Rights Reserved. |
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4 | * |
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5 | * Permission is hereby granted, free of charge, to any person obtaining a |
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6 | * copy of this software and associated documentation files (the |
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7 | * "Software"), to deal in the Software without restriction, including |
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8 | * without limitation the rights to use, copy, modify, merge, publish, |
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9 | * distribute, sub license, and/or sell copies of the Software, and to |
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10 | * permit persons to whom the Software is furnished to do so, subject to |
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11 | * the following conditions: |
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12 | * |
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13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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14 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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15 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL |
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16 | * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, |
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17 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR |
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18 | * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE |
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19 | * USE OR OTHER DEALINGS IN THE SOFTWARE. |
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20 | * |
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21 | * The above copyright notice and this permission notice (including the |
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22 | * next paragraph) shall be included in all copies or substantial portions |
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23 | * of the Software. |
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24 | * |
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25 | */ |
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26 | /* |
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27 | * Authors: |
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28 | * Jerome Glisse |
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29 | * Thomas Hellstrom |
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30 | * Dave Airlie |
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31 | */ |
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32 | #include |
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33 | #include |
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34 | #include |
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35 | #include |
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36 | #include |
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37 | #include |
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38 | #include |
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39 | #include "radeon_reg.h" |
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40 | #include "radeon.h" |
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41 | |||
42 | #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT) |
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43 | |||
44 | static int radeon_ttm_debugfs_init(struct radeon_device *rdev); |
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45 | |||
46 | static struct radeon_device *radeon_get_rdev(struct ttm_bo_device *bdev) |
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47 | { |
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48 | struct radeon_mman *mman; |
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49 | struct radeon_device *rdev; |
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50 | |||
51 | mman = container_of(bdev, struct radeon_mman, bdev); |
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52 | rdev = container_of(mman, struct radeon_device, mman); |
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53 | return rdev; |
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54 | } |
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55 | |||
56 | |||
57 | /* |
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58 | * Global memory. |
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59 | */ |
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60 | static int radeon_ttm_mem_global_init(struct ttm_global_reference *ref) |
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61 | { |
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62 | return ttm_mem_global_init(ref->object); |
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63 | } |
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64 | |||
65 | static void radeon_ttm_mem_global_release(struct ttm_global_reference *ref) |
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66 | { |
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67 | ttm_mem_global_release(ref->object); |
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68 | } |
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69 | |||
70 | static int radeon_ttm_global_init(struct radeon_device *rdev) |
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71 | { |
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72 | struct ttm_global_reference *global_ref; |
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73 | int r; |
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74 | |||
75 | rdev->mman.mem_global_referenced = false; |
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76 | global_ref = &rdev->mman.mem_global_ref; |
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77 | global_ref->global_type = TTM_GLOBAL_TTM_MEM; |
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78 | global_ref->size = sizeof(struct ttm_mem_global); |
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79 | global_ref->init = &radeon_ttm_mem_global_init; |
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80 | global_ref->release = &radeon_ttm_mem_global_release; |
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81 | r = ttm_global_item_ref(global_ref); |
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82 | if (r != 0) { |
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83 | DRM_ERROR("Failed setting up TTM memory accounting " |
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84 | "subsystem.\n"); |
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85 | return r; |
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86 | } |
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87 | |||
88 | rdev->mman.bo_global_ref.mem_glob = |
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89 | rdev->mman.mem_global_ref.object; |
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90 | global_ref = &rdev->mman.bo_global_ref.ref; |
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91 | global_ref->global_type = TTM_GLOBAL_TTM_BO; |
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92 | global_ref->size = sizeof(struct ttm_bo_global); |
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93 | global_ref->init = &ttm_bo_global_init; |
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94 | global_ref->release = &ttm_bo_global_release; |
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95 | r = ttm_global_item_ref(global_ref); |
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96 | if (r != 0) { |
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97 | DRM_ERROR("Failed setting up TTM BO subsystem.\n"); |
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98 | ttm_global_item_unref(&rdev->mman.mem_global_ref); |
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99 | return r; |
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100 | } |
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101 | |||
102 | rdev->mman.mem_global_referenced = true; |
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103 | return 0; |
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104 | } |
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105 | |||
106 | |||
107 | struct ttm_backend *radeon_ttm_backend_create(struct radeon_device *rdev); |
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108 | |||
109 | |||
110 | static int radeon_init_mem_type(struct ttm_bo_device *bdev, uint32_t type, |
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111 | struct ttm_mem_type_manager *man) |
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112 | { |
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113 | struct radeon_device *rdev; |
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114 | |||
115 | rdev = radeon_get_rdev(bdev); |
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116 | |||
117 | switch (type) { |
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118 | case TTM_PL_SYSTEM: |
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119 | /* System memory */ |
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120 | man->flags = TTM_MEMTYPE_FLAG_MAPPABLE; |
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121 | man->available_caching = TTM_PL_MASK_CACHING; |
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122 | man->default_caching = TTM_PL_FLAG_CACHED; |
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123 | break; |
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124 | case TTM_PL_TT: |
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125 | man->gpu_offset = rdev->mc.gtt_location; |
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126 | man->available_caching = TTM_PL_MASK_CACHING; |
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127 | man->default_caching = TTM_PL_FLAG_CACHED; |
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128 | man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA; |
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129 | #if __OS_HAS_AGP |
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130 | if (rdev->flags & RADEON_IS_AGP) { |
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131 | if (!(drm_core_has_AGP(rdev->ddev) && rdev->ddev->agp)) { |
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132 | DRM_ERROR("AGP is not enabled for memory type %u\n", |
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133 | (unsigned)type); |
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134 | return -EINVAL; |
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135 | } |
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136 | man->io_offset = rdev->mc.agp_base; |
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137 | man->io_size = rdev->mc.gtt_size; |
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138 | man->io_addr = NULL; |
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139 | if (!rdev->ddev->agp->cant_use_aperture) |
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140 | man->flags = TTM_MEMTYPE_FLAG_NEEDS_IOREMAP | |
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141 | TTM_MEMTYPE_FLAG_MAPPABLE; |
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142 | man->available_caching = TTM_PL_FLAG_UNCACHED | |
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143 | TTM_PL_FLAG_WC; |
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144 | man->default_caching = TTM_PL_FLAG_WC; |
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145 | } else |
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146 | #endif |
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147 | { |
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148 | man->io_offset = 0; |
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149 | man->io_size = 0; |
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150 | man->io_addr = NULL; |
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151 | } |
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152 | break; |
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153 | case TTM_PL_VRAM: |
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154 | /* "On-card" video ram */ |
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155 | man->gpu_offset = rdev->mc.vram_location; |
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156 | man->flags = TTM_MEMTYPE_FLAG_FIXED | |
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157 | TTM_MEMTYPE_FLAG_NEEDS_IOREMAP | |
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158 | TTM_MEMTYPE_FLAG_MAPPABLE; |
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159 | man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC; |
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160 | man->default_caching = TTM_PL_FLAG_WC; |
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161 | man->io_addr = NULL; |
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162 | man->io_offset = rdev->mc.aper_base; |
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163 | man->io_size = rdev->mc.aper_size; |
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164 | break; |
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165 | default: |
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166 | DRM_ERROR("Unsupported memory type %u\n", (unsigned)type); |
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167 | return -EINVAL; |
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168 | } |
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169 | return 0; |
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170 | } |
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171 | |||
172 | static struct ttm_bo_driver radeon_bo_driver = { |
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173 | // .create_ttm_backend_entry = &radeon_create_ttm_backend_entry, |
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174 | // .invalidate_caches = &radeon_invalidate_caches, |
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175 | .init_mem_type = &radeon_init_mem_type, |
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176 | // .evict_flags = &radeon_evict_flags, |
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177 | // .move = &radeon_bo_move, |
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178 | // .verify_access = &radeon_verify_access, |
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179 | // .sync_obj_signaled = &radeon_sync_obj_signaled, |
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180 | // .sync_obj_wait = &radeon_sync_obj_wait, |
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181 | // .sync_obj_flush = &radeon_sync_obj_flush, |
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182 | // .sync_obj_unref = &radeon_sync_obj_unref, |
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183 | // .sync_obj_ref = &radeon_sync_obj_ref, |
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184 | // .move_notify = &radeon_bo_move_notify, |
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185 | // .fault_reserve_notify = &radeon_bo_fault_reserve_notify, |
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186 | }; |
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187 | |||
188 | int radeon_ttm_init(struct radeon_device *rdev) |
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189 | { |
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190 | int r; |
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191 | |||
192 | r = radeon_ttm_global_init(rdev); |
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193 | if (r) { |
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194 | return r; |
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195 | } |
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196 | /* No others user of address space so set it to 0 */ |
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197 | r = ttm_bo_device_init(&rdev->mman.bdev, |
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198 | rdev->mman.bo_global_ref.ref.object, |
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199 | &radeon_bo_driver, DRM_FILE_PAGE_OFFSET, |
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200 | rdev->need_dma32); |
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201 | if (r) { |
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202 | DRM_ERROR("failed initializing buffer object driver(%d).\n", r); |
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203 | return r; |
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204 | } |
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205 | rdev->mman.initialized = true; |
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206 | r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_VRAM, |
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207 | rdev->mc.real_vram_size >> PAGE_SHIFT); |
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208 | if (r) { |
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209 | DRM_ERROR("Failed initializing VRAM heap.\n"); |
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210 | return r; |
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211 | } |
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212 | r = radeon_bo_create(rdev, NULL, 256 * 1024, true, |
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213 | RADEON_GEM_DOMAIN_VRAM, |
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214 | &rdev->stollen_vga_memory); |
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215 | if (r) { |
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216 | return r; |
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217 | } |
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218 | r = radeon_bo_reserve(rdev->stollen_vga_memory, false); |
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219 | if (r) |
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220 | return r; |
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221 | r = radeon_bo_pin(rdev->stollen_vga_memory, RADEON_GEM_DOMAIN_VRAM, NULL); |
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222 | radeon_bo_unreserve(rdev->stollen_vga_memory); |
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223 | if (r) { |
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224 | radeon_bo_unref(&rdev->stollen_vga_memory); |
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225 | return r; |
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226 | } |
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227 | DRM_INFO("radeon: %uM of VRAM memory ready\n", |
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228 | (unsigned)rdev->mc.real_vram_size / (1024 * 1024)); |
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229 | r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_TT, |
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230 | rdev->mc.gtt_size >> PAGE_SHIFT); |
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231 | if (r) { |
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232 | DRM_ERROR("Failed initializing GTT heap.\n"); |
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233 | return r; |
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234 | } |
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235 | DRM_INFO("radeon: %uM of GTT memory ready.\n", |
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236 | (unsigned)(rdev->mc.gtt_size / (1024 * 1024))); |
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237 | if (unlikely(rdev->mman.bdev.dev_mapping == NULL)) { |
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238 | rdev->mman.bdev.dev_mapping = rdev->ddev->dev_mapping; |
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239 | } |
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240 | |||
241 | r = radeon_ttm_debugfs_init(rdev); |
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242 | if (r) { |
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243 | DRM_ERROR("Failed to init debugfs\n"); |
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244 | return r; |
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245 | } |
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246 | return 0; |
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247 | } |
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248 | |||
249 | static struct vm_operations_struct radeon_ttm_vm_ops; |
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250 | static const struct vm_operations_struct *ttm_vm_ops = NULL; |
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251 |