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1117 | serge | 1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
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3 | * Copyright 2008 Red Hat Inc. |
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4 | * Copyright 2009 Jerome Glisse. |
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5 | * |
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6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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7 | * copy of this software and associated documentation files (the "Software"), |
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8 | * to deal in the Software without restriction, including without limitation |
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9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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10 | * and/or sell copies of the Software, and to permit persons to whom the |
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11 | * Software is furnished to do so, subject to the following conditions: |
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12 | * |
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13 | * The above copyright notice and this permission notice shall be included in |
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14 | * all copies or substantial portions of the Software. |
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15 | * |
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16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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22 | * OTHER DEALINGS IN THE SOFTWARE. |
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23 | * |
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24 | * Authors: Dave Airlie |
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25 | * Alex Deucher |
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26 | * Jerome Glisse |
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2997 | Serge | 27 | * Christian Konig |
1117 | serge | 28 | */ |
1179 | serge | 29 | #include |
1963 | serge | 30 | #include |
2997 | Serge | 31 | #include |
32 | #include |
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1117 | serge | 33 | #include "radeon_reg.h" |
34 | #include "radeon.h" |
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35 | #include "atom.h" |
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36 | |||
37 | /* |
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2997 | Serge | 38 | * IB |
39 | * IBs (Indirect Buffers) and areas of GPU accessible memory where |
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40 | * commands are stored. You can put a pointer to the IB in the |
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41 | * command ring and the hw will fetch the commands from the IB |
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42 | * and execute them. Generally userspace acceleration drivers |
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43 | * produce command buffers which are send to the kernel and |
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44 | * put in IBs for execution by the requested ring. |
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1117 | serge | 45 | */ |
2997 | Serge | 46 | static int radeon_debugfs_sa_init(struct radeon_device *rdev); |
47 | |||
48 | /** |
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49 | * radeon_ib_get - request an IB (Indirect Buffer) |
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50 | * |
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51 | * @rdev: radeon_device pointer |
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52 | * @ring: ring index the IB is associated with |
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53 | * @ib: IB object returned |
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54 | * @size: requested IB size |
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55 | * |
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56 | * Request an IB (all asics). IBs are allocated using the |
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57 | * suballocator. |
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58 | * Returns 0 on success, error on failure. |
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59 | */ |
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60 | int radeon_ib_get(struct radeon_device *rdev, int ring, |
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61 | struct radeon_ib *ib, struct radeon_vm *vm, |
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62 | unsigned size) |
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1117 | serge | 63 | { |
2997 | Serge | 64 | int i, r; |
1117 | serge | 65 | |
2997 | Serge | 66 | r = radeon_sa_bo_new(rdev, &rdev->ring_tmp_bo, &ib->sa_bo, size, 256, true); |
1117 | serge | 67 | if (r) { |
2997 | Serge | 68 | dev_err(rdev->dev, "failed to get a new IB (%d)\n", r); |
1117 | serge | 69 | return r; |
70 | } |
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2997 | Serge | 71 | |
72 | r = radeon_semaphore_create(rdev, &ib->semaphore); |
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2005 | serge | 73 | if (r) { |
74 | return r; |
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75 | } |
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2997 | Serge | 76 | |
77 | ib->ring = ring; |
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78 | ib->fence = NULL; |
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79 | ib->ptr = radeon_sa_bo_cpu_addr(ib->sa_bo); |
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80 | ib->vm = vm; |
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81 | if (vm) { |
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82 | /* ib pool is bound at RADEON_VA_IB_OFFSET in virtual address |
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83 | * space and soffset is the offset inside the pool bo |
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84 | */ |
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85 | ib->gpu_addr = ib->sa_bo->soffset + RADEON_VA_IB_OFFSET; |
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86 | } else { |
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87 | ib->gpu_addr = radeon_sa_bo_gpu_addr(ib->sa_bo); |
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2005 | serge | 88 | } |
2997 | Serge | 89 | ib->is_const_ib = false; |
90 | for (i = 0; i < RADEON_NUM_RINGS; ++i) |
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91 | ib->sync_to[i] = NULL; |
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92 | |||
1428 | serge | 93 | return 0; |
1117 | serge | 94 | } |
95 | |||
2997 | Serge | 96 | /** |
97 | * radeon_ib_free - free an IB (Indirect Buffer) |
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98 | * |
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99 | * @rdev: radeon_device pointer |
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100 | * @ib: IB object to free |
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101 | * |
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102 | * Free an IB (all asics). |
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103 | */ |
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104 | void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib) |
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1117 | serge | 105 | { |
2997 | Serge | 106 | radeon_semaphore_free(rdev, &ib->semaphore, ib->fence); |
107 | radeon_sa_bo_free(rdev, &ib->sa_bo, ib->fence); |
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108 | radeon_fence_unref(&ib->fence); |
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1117 | serge | 109 | } |
110 | |||
2997 | Serge | 111 | /** |
112 | * radeon_ib_schedule - schedule an IB (Indirect Buffer) on the ring |
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113 | * |
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114 | * @rdev: radeon_device pointer |
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115 | * @ib: IB object to schedule |
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116 | * @const_ib: Const IB to schedule (SI only) |
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117 | * |
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118 | * Schedule an IB on the associated ring (all asics). |
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119 | * Returns 0 on success, error on failure. |
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120 | * |
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121 | * On SI, there are two parallel engines fed from the primary ring, |
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122 | * the CE (Constant Engine) and the DE (Drawing Engine). Since |
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123 | * resource descriptors have moved to memory, the CE allows you to |
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124 | * prime the caches while the DE is updating register state so that |
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125 | * the resource descriptors will be already in cache when the draw is |
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126 | * processed. To accomplish this, the userspace driver submits two |
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127 | * IBs, one for the CE and one for the DE. If there is a CE IB (called |
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128 | * a CONST_IB), it will be put on the ring prior to the DE IB. Prior |
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129 | * to SI there was just a DE IB. |
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130 | */ |
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131 | int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib, |
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132 | struct radeon_ib *const_ib) |
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1117 | serge | 133 | { |
2997 | Serge | 134 | struct radeon_ring *ring = &rdev->ring[ib->ring]; |
135 | bool need_sync = false; |
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136 | int i, r = 0; |
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1117 | serge | 137 | |
2997 | Serge | 138 | if (!ib->length_dw || !ring->ready) { |
1117 | serge | 139 | /* TODO: Nothings in the ib we should report. */ |
2997 | Serge | 140 | dev_err(rdev->dev, "couldn't schedule ib\n"); |
1117 | serge | 141 | return -EINVAL; |
142 | } |
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1179 | serge | 143 | |
144 | /* 64 dwords should be enough for fence too */ |
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2997 | Serge | 145 | r = radeon_ring_lock(rdev, ring, 64 + RADEON_NUM_RINGS * 8); |
1117 | serge | 146 | if (r) { |
2997 | Serge | 147 | dev_err(rdev->dev, "scheduling IB failed (%d).\n", r); |
1117 | serge | 148 | return r; |
149 | } |
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2997 | Serge | 150 | for (i = 0; i < RADEON_NUM_RINGS; ++i) { |
151 | struct radeon_fence *fence = ib->sync_to[i]; |
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152 | if (radeon_fence_need_sync(fence, ib->ring)) { |
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153 | need_sync = true; |
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154 | radeon_semaphore_sync_rings(rdev, ib->semaphore, |
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155 | fence->ring, ib->ring); |
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156 | radeon_fence_note_sync(fence, ib->ring); |
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157 | } |
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158 | } |
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159 | /* immediately free semaphore when we don't need to sync */ |
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160 | if (!need_sync) { |
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161 | radeon_semaphore_free(rdev, &ib->semaphore, NULL); |
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162 | } |
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163 | /* if we can't remember our last VM flush then flush now! */ |
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164 | if (ib->vm && !ib->vm->last_flush) { |
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165 | radeon_ring_vm_flush(rdev, ib->ring, ib->vm); |
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166 | } |
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167 | if (const_ib) { |
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168 | radeon_ring_ib_execute(rdev, const_ib->ring, const_ib); |
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169 | radeon_semaphore_free(rdev, &const_ib->semaphore, NULL); |
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170 | } |
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171 | radeon_ring_ib_execute(rdev, ib->ring, ib); |
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172 | r = radeon_fence_emit(rdev, &ib->fence, ib->ring); |
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173 | if (r) { |
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174 | dev_err(rdev->dev, "failed to emit fence for new IB (%d)\n", r); |
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175 | radeon_ring_unlock_undo(rdev, ring); |
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176 | return r; |
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177 | } |
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178 | if (const_ib) { |
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179 | const_ib->fence = radeon_fence_ref(ib->fence); |
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180 | } |
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181 | /* we just flushed the VM, remember that */ |
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182 | if (ib->vm && !ib->vm->last_flush) { |
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183 | ib->vm->last_flush = radeon_fence_ref(ib->fence); |
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184 | } |
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185 | radeon_ring_unlock_commit(rdev, ring); |
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1117 | serge | 186 | return 0; |
187 | } |
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188 | |||
2997 | Serge | 189 | /** |
190 | * radeon_ib_pool_init - Init the IB (Indirect Buffer) pool |
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191 | * |
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192 | * @rdev: radeon_device pointer |
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193 | * |
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194 | * Initialize the suballocator to manage a pool of memory |
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195 | * for use as IBs (all asics). |
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196 | * Returns 0 on success, error on failure. |
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197 | */ |
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1117 | serge | 198 | int radeon_ib_pool_init(struct radeon_device *rdev) |
199 | { |
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2997 | Serge | 200 | int r; |
1117 | serge | 201 | |
2997 | Serge | 202 | if (rdev->ib_pool_ready) { |
1179 | serge | 203 | return 0; |
1117 | serge | 204 | } |
2997 | Serge | 205 | r = radeon_sa_bo_manager_init(rdev, &rdev->ring_tmp_bo, |
206 | RADEON_IB_POOL_SIZE*64*1024, |
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207 | RADEON_GEM_DOMAIN_GTT); |
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1117 | serge | 208 | if (r) { |
209 | return r; |
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210 | } |
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2997 | Serge | 211 | |
212 | r = radeon_sa_bo_manager_start(rdev, &rdev->ring_tmp_bo); |
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1117 | serge | 213 | if (r) { |
214 | return r; |
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215 | } |
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216 | |||
2997 | Serge | 217 | rdev->ib_pool_ready = true; |
218 | if (radeon_debugfs_sa_init(rdev)) { |
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219 | dev_err(rdev->dev, "failed to register debugfs file for SA\n"); |
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1117 | serge | 220 | } |
2997 | Serge | 221 | return 0; |
1117 | serge | 222 | } |
223 | |||
2997 | Serge | 224 | /** |
225 | * radeon_ib_pool_fini - Free the IB (Indirect Buffer) pool |
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226 | * |
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227 | * @rdev: radeon_device pointer |
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228 | * |
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229 | * Tear down the suballocator managing the pool of memory |
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230 | * for use as IBs (all asics). |
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231 | */ |
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1117 | serge | 232 | void radeon_ib_pool_fini(struct radeon_device *rdev) |
233 | { |
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2997 | Serge | 234 | if (rdev->ib_pool_ready) { |
235 | radeon_sa_bo_manager_suspend(rdev, &rdev->ring_tmp_bo); |
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236 | radeon_sa_bo_manager_fini(rdev, &rdev->ring_tmp_bo); |
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237 | rdev->ib_pool_ready = false; |
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238 | } |
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239 | } |
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240 | |||
241 | /** |
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242 | * radeon_ib_ring_tests - test IBs on the rings |
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243 | * |
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244 | * @rdev: radeon_device pointer |
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245 | * |
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246 | * Test an IB (Indirect Buffer) on each ring. |
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247 | * If the test fails, disable the ring. |
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248 | * Returns 0 on success, error if the primary GFX ring |
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249 | * IB test fails. |
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250 | */ |
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251 | int radeon_ib_ring_tests(struct radeon_device *rdev) |
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252 | { |
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253 | unsigned i; |
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1404 | serge | 254 | int r; |
255 | |||
2997 | Serge | 256 | for (i = 0; i < RADEON_NUM_RINGS; ++i) { |
257 | struct radeon_ring *ring = &rdev->ring[i]; |
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258 | |||
259 | if (!ring->ready) |
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260 | continue; |
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261 | |||
262 | r = radeon_ib_test(rdev, i, ring); |
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263 | if (r) { |
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264 | ring->ready = false; |
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265 | |||
266 | if (i == RADEON_RING_TYPE_GFX_INDEX) { |
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267 | /* oh, oh, that's really bad */ |
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268 | DRM_ERROR("radeon: failed testing IB on GFX ring (%d).\n", r); |
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269 | rdev->accel_working = false; |
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270 | return r; |
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271 | |||
272 | } else { |
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273 | /* still not good, but we can live with it */ |
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274 | DRM_ERROR("radeon: failed testing IB on ring %d (%d).\n", i, r); |
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1117 | serge | 275 | } |
1404 | serge | 276 | } |
1117 | serge | 277 | } |
2997 | Serge | 278 | return 0; |
1117 | serge | 279 | } |
280 | |||
281 | /* |
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2997 | Serge | 282 | * Rings |
283 | * Most engines on the GPU are fed via ring buffers. Ring |
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284 | * buffers are areas of GPU accessible memory that the host |
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285 | * writes commands into and the GPU reads commands out of. |
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286 | * There is a rptr (read pointer) that determines where the |
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287 | * GPU is currently reading, and a wptr (write pointer) |
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288 | * which determines where the host has written. When the |
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289 | * pointers are equal, the ring is idle. When the host |
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290 | * writes commands to the ring buffer, it increments the |
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291 | * wptr. The GPU then starts fetching commands and executes |
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292 | * them until the pointers are equal again. |
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1117 | serge | 293 | */ |
2997 | Serge | 294 | static int radeon_debugfs_ring_init(struct radeon_device *rdev, struct radeon_ring *ring); |
295 | |||
296 | /** |
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297 | * radeon_ring_write - write a value to the ring |
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298 | * |
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299 | * @ring: radeon_ring structure holding ring information |
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300 | * @v: dword (dw) value to write |
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301 | * |
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302 | * Write a value to the requested ring buffer (all asics). |
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303 | */ |
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304 | void radeon_ring_write(struct radeon_ring *ring, uint32_t v) |
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1117 | serge | 305 | { |
2997 | Serge | 306 | #if DRM_DEBUG_CODE |
307 | if (ring->count_dw <= 0) { |
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308 | DRM_ERROR("radeon: writing more dwords to the ring than expected!\n"); |
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309 | } |
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310 | #endif |
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311 | ring->ring[ring->wptr++] = v; |
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312 | ring->wptr &= ring->ptr_mask; |
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313 | ring->count_dw--; |
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314 | ring->ring_free_dw--; |
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315 | } |
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316 | |||
317 | /** |
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318 | * radeon_ring_supports_scratch_reg - check if the ring supports |
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319 | * writing to scratch registers |
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320 | * |
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321 | * @rdev: radeon_device pointer |
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322 | * @ring: radeon_ring structure holding ring information |
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323 | * |
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324 | * Check if a specific ring supports writing to scratch registers (all asics). |
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325 | * Returns true if the ring supports writing to scratch regs, false if not. |
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326 | */ |
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327 | bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev, |
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328 | struct radeon_ring *ring) |
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329 | { |
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330 | switch (ring->idx) { |
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331 | case RADEON_RING_TYPE_GFX_INDEX: |
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332 | case CAYMAN_RING_TYPE_CP1_INDEX: |
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333 | case CAYMAN_RING_TYPE_CP2_INDEX: |
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334 | return true; |
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335 | default: |
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336 | return false; |
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337 | } |
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338 | } |
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339 | |||
340 | /** |
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341 | * radeon_ring_free_size - update the free size |
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342 | * |
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343 | * @rdev: radeon_device pointer |
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344 | * @ring: radeon_ring structure holding ring information |
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345 | * |
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346 | * Update the free dw slots in the ring buffer (all asics). |
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347 | */ |
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348 | void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *ring) |
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349 | { |
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350 | u32 rptr; |
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351 | |||
1963 | serge | 352 | if (rdev->wb.enabled) |
2997 | Serge | 353 | rptr = le32_to_cpu(rdev->wb.wb[ring->rptr_offs/4]); |
1179 | serge | 354 | else |
2997 | Serge | 355 | rptr = RREG32(ring->rptr_reg); |
356 | ring->rptr = (rptr & ring->ptr_reg_mask) >> ring->ptr_reg_shift; |
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1117 | serge | 357 | /* This works because ring_size is a power of 2 */ |
2997 | Serge | 358 | ring->ring_free_dw = (ring->rptr + (ring->ring_size / 4)); |
359 | ring->ring_free_dw -= ring->wptr; |
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360 | ring->ring_free_dw &= ring->ptr_mask; |
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361 | if (!ring->ring_free_dw) { |
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362 | ring->ring_free_dw = ring->ring_size / 4; |
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1117 | serge | 363 | } |
364 | } |
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365 | |||
2997 | Serge | 366 | /** |
367 | * radeon_ring_alloc - allocate space on the ring buffer |
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368 | * |
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369 | * @rdev: radeon_device pointer |
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370 | * @ring: radeon_ring structure holding ring information |
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371 | * @ndw: number of dwords to allocate in the ring buffer |
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372 | * |
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373 | * Allocate @ndw dwords in the ring buffer (all asics). |
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374 | * Returns 0 on success, error on failure. |
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375 | */ |
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376 | int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ndw) |
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1117 | serge | 377 | { |
378 | int r; |
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379 | |||
380 | /* Align requested size with padding so unlock_commit can |
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381 | * pad safely */ |
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2997 | Serge | 382 | ndw = (ndw + ring->align_mask) & ~ring->align_mask; |
383 | while (ndw > (ring->ring_free_dw - 1)) { |
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384 | radeon_ring_free_size(rdev, ring); |
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385 | if (ndw < ring->ring_free_dw) { |
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1117 | serge | 386 | break; |
387 | } |
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388 | // r = radeon_fence_wait_next(rdev); |
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389 | // if (r) { |
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390 | // mutex_unlock(&rdev->cp.mutex); |
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391 | // return r; |
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392 | // } |
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393 | } |
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2997 | Serge | 394 | ring->count_dw = ndw; |
395 | ring->wptr_old = ring->wptr; |
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1117 | serge | 396 | return 0; |
397 | } |
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398 | |||
2997 | Serge | 399 | /** |
400 | * radeon_ring_lock - lock the ring and allocate space on it |
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401 | * |
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402 | * @rdev: radeon_device pointer |
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403 | * @ring: radeon_ring structure holding ring information |
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404 | * @ndw: number of dwords to allocate in the ring buffer |
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405 | * |
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406 | * Lock the ring and allocate @ndw dwords in the ring buffer |
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407 | * (all asics). |
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408 | * Returns 0 on success, error on failure. |
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409 | */ |
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410 | int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ndw) |
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1117 | serge | 411 | { |
1963 | serge | 412 | int r; |
413 | |||
2997 | Serge | 414 | mutex_lock(&rdev->ring_lock); |
415 | r = radeon_ring_alloc(rdev, ring, ndw); |
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1963 | serge | 416 | if (r) { |
2997 | Serge | 417 | mutex_unlock(&rdev->ring_lock); |
1963 | serge | 418 | return r; |
419 | } |
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420 | return 0; |
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421 | } |
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422 | |||
2997 | Serge | 423 | /** |
424 | * radeon_ring_commit - tell the GPU to execute the new |
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425 | * commands on the ring buffer |
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426 | * |
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427 | * @rdev: radeon_device pointer |
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428 | * @ring: radeon_ring structure holding ring information |
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429 | * |
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430 | * Update the wptr (write pointer) to tell the GPU to |
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431 | * execute new commands on the ring buffer (all asics). |
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432 | */ |
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433 | void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *ring) |
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1963 | serge | 434 | { |
1117 | serge | 435 | /* We pad to match fetch size */ |
2997 | Serge | 436 | while (ring->wptr & ring->align_mask) { |
437 | radeon_ring_write(ring, ring->nop); |
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1117 | serge | 438 | } |
439 | DRM_MEMORYBARRIER(); |
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2997 | Serge | 440 | WREG32(ring->wptr_reg, (ring->wptr << ring->ptr_reg_shift) & ring->ptr_reg_mask); |
441 | (void)RREG32(ring->wptr_reg); |
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1963 | serge | 442 | } |
443 | |||
2997 | Serge | 444 | /** |
445 | * radeon_ring_unlock_commit - tell the GPU to execute the new |
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446 | * commands on the ring buffer and unlock it |
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447 | * |
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448 | * @rdev: radeon_device pointer |
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449 | * @ring: radeon_ring structure holding ring information |
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450 | * |
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451 | * Call radeon_ring_commit() then unlock the ring (all asics). |
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452 | */ |
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453 | void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *ring) |
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1963 | serge | 454 | { |
2997 | Serge | 455 | radeon_ring_commit(rdev, ring); |
456 | mutex_unlock(&rdev->ring_lock); |
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1117 | serge | 457 | } |
458 | |||
2997 | Serge | 459 | /** |
460 | * radeon_ring_undo - reset the wptr |
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461 | * |
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462 | * @ring: radeon_ring structure holding ring information |
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463 | * |
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464 | * Reset the driver's copy of the wtpr (all asics). |
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465 | */ |
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466 | void radeon_ring_undo(struct radeon_ring *ring) |
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1117 | serge | 467 | { |
2997 | Serge | 468 | ring->wptr = ring->wptr_old; |
1117 | serge | 469 | } |
470 | |||
2997 | Serge | 471 | /** |
472 | * radeon_ring_unlock_undo - reset the wptr and unlock the ring |
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473 | * |
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474 | * @ring: radeon_ring structure holding ring information |
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475 | * |
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476 | * Call radeon_ring_undo() then unlock the ring (all asics). |
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477 | */ |
||
478 | void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *ring) |
||
1117 | serge | 479 | { |
2997 | Serge | 480 | radeon_ring_undo(ring); |
481 | mutex_unlock(&rdev->ring_lock); |
||
482 | } |
||
483 | |||
484 | /** |
||
485 | * radeon_ring_force_activity - add some nop packets to the ring |
||
486 | * |
||
487 | * @rdev: radeon_device pointer |
||
488 | * @ring: radeon_ring structure holding ring information |
||
489 | * |
||
490 | * Add some nop packets to the ring to force activity (all asics). |
||
491 | * Used for lockup detection to see if the rptr is advancing. |
||
492 | */ |
||
493 | void radeon_ring_force_activity(struct radeon_device *rdev, struct radeon_ring *ring) |
||
494 | { |
||
1117 | serge | 495 | int r; |
496 | |||
2997 | Serge | 497 | radeon_ring_free_size(rdev, ring); |
498 | if (ring->rptr == ring->wptr) { |
||
499 | r = radeon_ring_alloc(rdev, ring, 1); |
||
500 | if (!r) { |
||
501 | radeon_ring_write(ring, ring->nop); |
||
502 | radeon_ring_commit(rdev, ring); |
||
503 | } |
||
504 | } |
||
505 | } |
||
506 | |||
507 | /** |
||
508 | * radeon_ring_force_activity - update lockup variables |
||
509 | * |
||
510 | * @ring: radeon_ring structure holding ring information |
||
511 | * |
||
512 | * Update the last rptr value and timestamp (all asics). |
||
513 | */ |
||
514 | void radeon_ring_lockup_update(struct radeon_ring *ring) |
||
515 | { |
||
516 | ring->last_rptr = ring->rptr; |
||
517 | ring->last_activity = GetTimerTicks(); |
||
518 | } |
||
519 | |||
520 | /** |
||
521 | * radeon_ring_test_lockup() - check if ring is lockedup by recording information |
||
522 | * @rdev: radeon device structure |
||
523 | * @ring: radeon_ring structure holding ring information |
||
524 | * |
||
525 | * We don't need to initialize the lockup tracking information as we will either |
||
526 | * have CP rptr to a different value of jiffies wrap around which will force |
||
527 | * initialization of the lockup tracking informations. |
||
528 | * |
||
529 | * A possible false positivie is if we get call after while and last_cp_rptr == |
||
530 | * the current CP rptr, even if it's unlikely it might happen. To avoid this |
||
531 | * if the elapsed time since last call is bigger than 2 second than we return |
||
532 | * false and update the tracking information. Due to this the caller must call |
||
533 | * radeon_ring_test_lockup several time in less than 2sec for lockup to be reported |
||
534 | * the fencing code should be cautious about that. |
||
535 | * |
||
536 | * Caller should write to the ring to force CP to do something so we don't get |
||
537 | * false positive when CP is just gived nothing to do. |
||
538 | * |
||
539 | **/ |
||
540 | bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring) |
||
541 | { |
||
542 | unsigned long cjiffies, elapsed; |
||
543 | uint32_t rptr; |
||
544 | |||
545 | cjiffies = GetTimerTicks(); |
||
546 | if (!time_after(cjiffies, ring->last_activity)) { |
||
547 | /* likely a wrap around */ |
||
548 | radeon_ring_lockup_update(ring); |
||
549 | return false; |
||
550 | } |
||
551 | rptr = RREG32(ring->rptr_reg); |
||
552 | ring->rptr = (rptr & ring->ptr_reg_mask) >> ring->ptr_reg_shift; |
||
553 | if (ring->rptr != ring->last_rptr) { |
||
554 | /* CP is still working no lockup */ |
||
555 | radeon_ring_lockup_update(ring); |
||
556 | return false; |
||
557 | } |
||
558 | elapsed = jiffies_to_msecs(cjiffies - ring->last_activity); |
||
559 | if (radeon_lockup_timeout && elapsed >= radeon_lockup_timeout) { |
||
560 | dev_err(rdev->dev, "GPU lockup CP stall for more than %lumsec\n", elapsed); |
||
561 | return true; |
||
562 | } |
||
563 | /* give a chance to the GPU ... */ |
||
564 | return false; |
||
565 | } |
||
566 | |||
567 | /** |
||
568 | * radeon_ring_backup - Back up the content of a ring |
||
569 | * |
||
570 | * @rdev: radeon_device pointer |
||
571 | * @ring: the ring we want to back up |
||
572 | * |
||
573 | * Saves all unprocessed commits from a ring, returns the number of dwords saved. |
||
574 | */ |
||
575 | unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring, |
||
576 | uint32_t **data) |
||
577 | { |
||
578 | unsigned size, ptr, i; |
||
579 | |||
580 | /* just in case lock the ring */ |
||
581 | mutex_lock(&rdev->ring_lock); |
||
582 | *data = NULL; |
||
583 | |||
584 | if (ring->ring_obj == NULL) { |
||
585 | mutex_unlock(&rdev->ring_lock); |
||
586 | return 0; |
||
587 | } |
||
588 | |||
589 | /* it doesn't make sense to save anything if all fences are signaled */ |
||
590 | if (!radeon_fence_count_emitted(rdev, ring->idx)) { |
||
591 | mutex_unlock(&rdev->ring_lock); |
||
592 | return 0; |
||
593 | } |
||
594 | |||
595 | /* calculate the number of dw on the ring */ |
||
596 | if (ring->rptr_save_reg) |
||
597 | ptr = RREG32(ring->rptr_save_reg); |
||
598 | else if (rdev->wb.enabled) |
||
599 | ptr = le32_to_cpu(*ring->next_rptr_cpu_addr); |
||
600 | else { |
||
601 | /* no way to read back the next rptr */ |
||
602 | mutex_unlock(&rdev->ring_lock); |
||
603 | return 0; |
||
604 | } |
||
605 | |||
606 | size = ring->wptr + (ring->ring_size / 4); |
||
607 | size -= ptr; |
||
608 | size &= ring->ptr_mask; |
||
609 | if (size == 0) { |
||
610 | mutex_unlock(&rdev->ring_lock); |
||
611 | return 0; |
||
612 | } |
||
613 | |||
614 | /* and then save the content of the ring */ |
||
615 | *data = kmalloc_array(size, sizeof(uint32_t), GFP_KERNEL); |
||
616 | if (!*data) { |
||
617 | mutex_unlock(&rdev->ring_lock); |
||
618 | return 0; |
||
619 | } |
||
620 | for (i = 0; i < size; ++i) { |
||
621 | (*data)[i] = ring->ring[ptr++]; |
||
622 | ptr &= ring->ptr_mask; |
||
623 | } |
||
624 | |||
625 | mutex_unlock(&rdev->ring_lock); |
||
626 | return size; |
||
627 | } |
||
628 | |||
629 | /** |
||
630 | * radeon_ring_restore - append saved commands to the ring again |
||
631 | * |
||
632 | * @rdev: radeon_device pointer |
||
633 | * @ring: ring to append commands to |
||
634 | * @size: number of dwords we want to write |
||
635 | * @data: saved commands |
||
636 | * |
||
637 | * Allocates space on the ring and restore the previously saved commands. |
||
638 | */ |
||
639 | int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring, |
||
640 | unsigned size, uint32_t *data) |
||
641 | { |
||
642 | int i, r; |
||
643 | |||
644 | if (!size || !data) |
||
645 | return 0; |
||
646 | |||
647 | /* restore the saved ring content */ |
||
648 | r = radeon_ring_lock(rdev, ring, size); |
||
649 | if (r) |
||
650 | return r; |
||
651 | |||
652 | for (i = 0; i < size; ++i) { |
||
653 | radeon_ring_write(ring, data[i]); |
||
654 | } |
||
655 | |||
656 | radeon_ring_unlock_commit(rdev, ring); |
||
657 | kfree(data); |
||
658 | return 0; |
||
659 | } |
||
660 | |||
661 | /** |
||
662 | * radeon_ring_init - init driver ring struct. |
||
663 | * |
||
664 | * @rdev: radeon_device pointer |
||
665 | * @ring: radeon_ring structure holding ring information |
||
666 | * @ring_size: size of the ring |
||
667 | * @rptr_offs: offset of the rptr writeback location in the WB buffer |
||
668 | * @rptr_reg: MMIO offset of the rptr register |
||
669 | * @wptr_reg: MMIO offset of the wptr register |
||
670 | * @ptr_reg_shift: bit offset of the rptr/wptr values |
||
671 | * @ptr_reg_mask: bit mask of the rptr/wptr values |
||
672 | * @nop: nop packet for this ring |
||
673 | * |
||
674 | * Initialize the driver information for the selected ring (all asics). |
||
675 | * Returns 0 on success, error on failure. |
||
676 | */ |
||
677 | int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ring_size, |
||
678 | unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg, |
||
679 | u32 ptr_reg_shift, u32 ptr_reg_mask, u32 nop) |
||
680 | { |
||
681 | int r; |
||
682 | |||
683 | ring->ring_size = ring_size; |
||
684 | ring->rptr_offs = rptr_offs; |
||
685 | ring->rptr_reg = rptr_reg; |
||
686 | ring->wptr_reg = wptr_reg; |
||
687 | ring->ptr_reg_shift = ptr_reg_shift; |
||
688 | ring->ptr_reg_mask = ptr_reg_mask; |
||
689 | ring->nop = nop; |
||
1120 | serge | 690 | /* Allocate ring buffer */ |
2997 | Serge | 691 | if (ring->ring_obj == NULL) { |
692 | r = radeon_bo_create(rdev, ring->ring_size, PAGE_SIZE, true, |
||
1117 | serge | 693 | RADEON_GEM_DOMAIN_GTT, |
2997 | Serge | 694 | NULL, &ring->ring_obj); |
1117 | serge | 695 | if (r) { |
1404 | serge | 696 | dev_err(rdev->dev, "(%d) ring create failed\n", r); |
1117 | serge | 697 | return r; |
698 | } |
||
2997 | Serge | 699 | r = radeon_bo_reserve(ring->ring_obj, false); |
1404 | serge | 700 | if (unlikely(r != 0)) |
701 | return r; |
||
2997 | Serge | 702 | r = radeon_bo_pin(ring->ring_obj, RADEON_GEM_DOMAIN_GTT, |
703 | &ring->gpu_addr); |
||
1117 | serge | 704 | if (r) { |
2997 | Serge | 705 | radeon_bo_unreserve(ring->ring_obj); |
1404 | serge | 706 | dev_err(rdev->dev, "(%d) ring pin failed\n", r); |
1117 | serge | 707 | return r; |
708 | } |
||
2997 | Serge | 709 | r = radeon_bo_kmap(ring->ring_obj, |
710 | (void **)&ring->ring); |
||
711 | radeon_bo_unreserve(ring->ring_obj); |
||
1117 | serge | 712 | if (r) { |
1404 | serge | 713 | dev_err(rdev->dev, "(%d) ring map failed\n", r); |
1117 | serge | 714 | return r; |
715 | } |
||
716 | } |
||
2997 | Serge | 717 | ring->ptr_mask = (ring->ring_size / 4) - 1; |
718 | ring->ring_free_dw = ring->ring_size / 4; |
||
719 | if (rdev->wb.enabled) { |
||
720 | u32 index = RADEON_WB_RING0_NEXT_RPTR + (ring->idx * 4); |
||
721 | ring->next_rptr_gpu_addr = rdev->wb.gpu_addr + index; |
||
722 | ring->next_rptr_cpu_addr = &rdev->wb.wb[index/4]; |
||
723 | } |
||
724 | if (radeon_debugfs_ring_init(rdev, ring)) { |
||
725 | DRM_ERROR("Failed to register debugfs file for rings !\n"); |
||
726 | } |
||
727 | radeon_ring_lockup_update(ring); |
||
1117 | serge | 728 | return 0; |
729 | } |
||
730 | |||
2997 | Serge | 731 | /** |
732 | * radeon_ring_fini - tear down the driver ring struct. |
||
733 | * |
||
734 | * @rdev: radeon_device pointer |
||
735 | * @ring: radeon_ring structure holding ring information |
||
736 | * |
||
737 | * Tear down the driver information for the selected ring (all asics). |
||
738 | */ |
||
739 | void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *ring) |
||
1117 | serge | 740 | { |
1404 | serge | 741 | int r; |
1963 | serge | 742 | struct radeon_bo *ring_obj; |
1404 | serge | 743 | |
2997 | Serge | 744 | mutex_lock(&rdev->ring_lock); |
745 | ring_obj = ring->ring_obj; |
||
746 | ring->ready = false; |
||
747 | ring->ring = NULL; |
||
748 | ring->ring_obj = NULL; |
||
749 | mutex_unlock(&rdev->ring_lock); |
||
1963 | serge | 750 | |
751 | if (ring_obj) { |
||
752 | r = radeon_bo_reserve(ring_obj, false); |
||
1404 | serge | 753 | if (likely(r == 0)) { |
1963 | serge | 754 | radeon_bo_kunmap(ring_obj); |
755 | radeon_bo_unpin(ring_obj); |
||
756 | radeon_bo_unreserve(ring_obj); |
||
1404 | serge | 757 | } |
1963 | serge | 758 | radeon_bo_unref(&ring_obj); |
1117 | serge | 759 | } |
760 | } |
||
761 | |||
762 | /* |
||
763 | * Debugfs info |
||
764 | */ |
||
765 | #if defined(CONFIG_DEBUG_FS) |
||
2997 | Serge | 766 | |
767 | static int radeon_debugfs_ring_info(struct seq_file *m, void *data) |
||
1117 | serge | 768 | { |
769 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
||
2997 | Serge | 770 | struct drm_device *dev = node->minor->dev; |
771 | struct radeon_device *rdev = dev->dev_private; |
||
772 | int ridx = *(int*)node->info_ent->data; |
||
773 | struct radeon_ring *ring = &rdev->ring[ridx]; |
||
774 | unsigned count, i, j; |
||
1117 | serge | 775 | |
2997 | Serge | 776 | radeon_ring_free_size(rdev, ring); |
777 | count = (ring->ring_size / 4) - ring->ring_free_dw; |
||
778 | seq_printf(m, "wptr(0x%04x): 0x%08x\n", ring->wptr_reg, RREG32(ring->wptr_reg)); |
||
779 | seq_printf(m, "rptr(0x%04x): 0x%08x\n", ring->rptr_reg, RREG32(ring->rptr_reg)); |
||
780 | if (ring->rptr_save_reg) { |
||
781 | seq_printf(m, "rptr next(0x%04x): 0x%08x\n", ring->rptr_save_reg, |
||
782 | RREG32(ring->rptr_save_reg)); |
||
1117 | serge | 783 | } |
2997 | Serge | 784 | seq_printf(m, "driver's copy of the wptr: 0x%08x\n", ring->wptr); |
785 | seq_printf(m, "driver's copy of the rptr: 0x%08x\n", ring->rptr); |
||
786 | seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw); |
||
787 | seq_printf(m, "%u dwords in ring\n", count); |
||
788 | i = ring->rptr; |
||
789 | for (j = 0; j <= count; j++) { |
||
790 | seq_printf(m, "r[%04d]=0x%08x\n", i, ring->ring[i]); |
||
791 | i = (i + 1) & ring->ptr_mask; |
||
1117 | serge | 792 | } |
793 | return 0; |
||
794 | } |
||
795 | |||
2997 | Serge | 796 | static int radeon_ring_type_gfx_index = RADEON_RING_TYPE_GFX_INDEX; |
797 | static int cayman_ring_type_cp1_index = CAYMAN_RING_TYPE_CP1_INDEX; |
||
798 | static int cayman_ring_type_cp2_index = CAYMAN_RING_TYPE_CP2_INDEX; |
||
799 | |||
800 | static struct drm_info_list radeon_debugfs_ring_info_list[] = { |
||
801 | {"radeon_ring_gfx", radeon_debugfs_ring_info, 0, &radeon_ring_type_gfx_index}, |
||
802 | {"radeon_ring_cp1", radeon_debugfs_ring_info, 0, &cayman_ring_type_cp1_index}, |
||
803 | {"radeon_ring_cp2", radeon_debugfs_ring_info, 0, &cayman_ring_type_cp2_index}, |
||
804 | }; |
||
805 | |||
806 | static int radeon_debugfs_sa_info(struct seq_file *m, void *data) |
||
1963 | serge | 807 | { |
808 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
||
2997 | Serge | 809 | struct drm_device *dev = node->minor->dev; |
810 | struct radeon_device *rdev = dev->dev_private; |
||
1963 | serge | 811 | |
2997 | Serge | 812 | radeon_sa_bo_dump_debug_info(&rdev->ring_tmp_bo, m); |
813 | |||
1963 | serge | 814 | return 0; |
2997 | Serge | 815 | |
1963 | serge | 816 | } |
817 | |||
2997 | Serge | 818 | static struct drm_info_list radeon_debugfs_sa_list[] = { |
819 | {"radeon_sa_info", &radeon_debugfs_sa_info, 0, NULL}, |
||
820 | }; |
||
1963 | serge | 821 | |
1117 | serge | 822 | #endif |
823 | |||
2997 | Serge | 824 | static int radeon_debugfs_ring_init(struct radeon_device *rdev, struct radeon_ring *ring) |
1117 | serge | 825 | { |
826 | #if defined(CONFIG_DEBUG_FS) |
||
827 | unsigned i; |
||
2997 | Serge | 828 | for (i = 0; i < ARRAY_SIZE(radeon_debugfs_ring_info_list); ++i) { |
829 | struct drm_info_list *info = &radeon_debugfs_ring_info_list[i]; |
||
830 | int ridx = *(int*)radeon_debugfs_ring_info_list[i].data; |
||
831 | unsigned r; |
||
1117 | serge | 832 | |
2997 | Serge | 833 | if (&rdev->ring[ridx] != ring) |
834 | continue; |
||
835 | |||
836 | r = radeon_debugfs_add_files(rdev, info, 1); |
||
1430 | serge | 837 | if (r) |
838 | return r; |
||
1117 | serge | 839 | } |
2997 | Serge | 840 | #endif |
841 | return 0; |
||
842 | } |
||
843 | |||
844 | static int radeon_debugfs_sa_init(struct radeon_device *rdev) |
||
845 | { |
||
846 | #if defined(CONFIG_DEBUG_FS) |
||
847 | return radeon_debugfs_add_files(rdev, radeon_debugfs_sa_list, 1); |
||
1117 | serge | 848 | #else |
849 | return 0; |
||
850 | #endif |
||
851 | }>=>>>><>>=>>>> |