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Rev | Author | Line No. | Line |
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1117 | serge | 1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
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3 | * Copyright 2008 Red Hat Inc. |
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4 | * Copyright 2009 Jerome Glisse. |
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5 | * |
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6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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7 | * copy of this software and associated documentation files (the "Software"), |
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8 | * to deal in the Software without restriction, including without limitation |
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9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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10 | * and/or sell copies of the Software, and to permit persons to whom the |
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11 | * Software is furnished to do so, subject to the following conditions: |
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12 | * |
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13 | * The above copyright notice and this permission notice shall be included in |
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14 | * all copies or substantial portions of the Software. |
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15 | * |
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16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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22 | * OTHER DEALINGS IN THE SOFTWARE. |
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23 | * |
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24 | * Authors: Dave Airlie |
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25 | * Alex Deucher |
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26 | * Jerome Glisse |
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27 | */ |
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1179 | serge | 28 | #include |
1963 | serge | 29 | #include |
1125 | serge | 30 | #include "drmP.h" |
1117 | serge | 31 | #include "radeon_drm.h" |
32 | #include "radeon_reg.h" |
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33 | #include "radeon.h" |
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34 | #include "atom.h" |
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35 | |||
36 | int radeon_debugfs_ib_init(struct radeon_device *rdev); |
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37 | |||
38 | /* |
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39 | * IB. |
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40 | */ |
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41 | int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib) |
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42 | { |
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43 | struct radeon_fence *fence; |
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44 | struct radeon_ib *nib; |
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1428 | serge | 45 | int r = 0, i, c; |
1117 | serge | 46 | |
47 | *ib = NULL; |
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48 | r = radeon_fence_create(rdev, &fence); |
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49 | if (r) { |
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1428 | serge | 50 | dev_err(rdev->dev, "failed to create fence for new IB\n"); |
1117 | serge | 51 | return r; |
52 | } |
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53 | mutex_lock(&rdev->ib_pool.mutex); |
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1428 | serge | 54 | for (i = rdev->ib_pool.head_id, c = 0, nib = NULL; c < RADEON_IB_POOL_SIZE; c++, i++) { |
55 | i &= (RADEON_IB_POOL_SIZE - 1); |
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56 | if (rdev->ib_pool.ibs[i].free) { |
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57 | nib = &rdev->ib_pool.ibs[i]; |
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58 | break; |
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2004 | serge | 59 | } |
1117 | serge | 60 | } |
1428 | serge | 61 | if (nib == NULL) { |
62 | /* This should never happen, it means we allocated all |
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63 | * IB and haven't scheduled one yet, return EBUSY to |
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64 | * userspace hoping that on ioctl recall we get better |
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65 | * luck |
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66 | */ |
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67 | dev_err(rdev->dev, "no free indirect buffer !\n"); |
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1179 | serge | 68 | mutex_unlock(&rdev->ib_pool.mutex); |
1428 | serge | 69 | radeon_fence_unref(&fence); |
70 | return -EBUSY; |
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1117 | serge | 71 | } |
1428 | serge | 72 | rdev->ib_pool.head_id = (nib->idx + 1) & (RADEON_IB_POOL_SIZE - 1); |
73 | nib->free = false; |
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2004 | serge | 74 | // if (nib->fence) { |
75 | // mutex_unlock(&rdev->ib_pool.mutex); |
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76 | // r = radeon_fence_wait(nib->fence, false); |
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77 | // if (r) { |
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78 | // dev_err(rdev->dev, "error waiting fence of IB(%u:0x%016lX:%u)\n", |
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79 | // nib->idx, (unsigned long)nib->gpu_addr, nib->length_dw); |
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80 | // mutex_lock(&rdev->ib_pool.mutex); |
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81 | // nib->free = true; |
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82 | // mutex_unlock(&rdev->ib_pool.mutex); |
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83 | // radeon_fence_unref(&fence); |
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84 | // return r; |
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85 | // } |
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86 | // mutex_lock(&rdev->ib_pool.mutex); |
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87 | // } |
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1117 | serge | 88 | radeon_fence_unref(&nib->fence); |
1428 | serge | 89 | nib->fence = fence; |
1117 | serge | 90 | nib->length_dw = 0; |
1179 | serge | 91 | mutex_unlock(&rdev->ib_pool.mutex); |
1117 | serge | 92 | *ib = nib; |
1428 | serge | 93 | return 0; |
1117 | serge | 94 | } |
95 | |||
96 | void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib) |
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97 | { |
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98 | struct radeon_ib *tmp = *ib; |
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99 | |||
100 | *ib = NULL; |
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101 | if (tmp == NULL) { |
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102 | return; |
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103 | } |
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1428 | serge | 104 | if (!tmp->fence->emited) |
105 | radeon_fence_unref(&tmp->fence); |
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1117 | serge | 106 | mutex_lock(&rdev->ib_pool.mutex); |
1428 | serge | 107 | tmp->free = true; |
1117 | serge | 108 | mutex_unlock(&rdev->ib_pool.mutex); |
109 | } |
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110 | |||
111 | int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib) |
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112 | { |
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113 | int r = 0; |
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114 | |||
115 | if (!ib->length_dw || !rdev->cp.ready) { |
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116 | /* TODO: Nothings in the ib we should report. */ |
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1428 | serge | 117 | DRM_ERROR("radeon: couldn't schedule IB(%u).\n", ib->idx); |
1117 | serge | 118 | return -EINVAL; |
119 | } |
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1179 | serge | 120 | |
121 | /* 64 dwords should be enough for fence too */ |
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1117 | serge | 122 | r = radeon_ring_lock(rdev, 64); |
123 | if (r) { |
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1963 | serge | 124 | DRM_ERROR("radeon: scheduling IB failed (%d).\n", r); |
1117 | serge | 125 | return r; |
126 | } |
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1179 | serge | 127 | radeon_ring_ib_execute(rdev, ib); |
1117 | serge | 128 | radeon_fence_emit(rdev, ib->fence); |
1179 | serge | 129 | mutex_lock(&rdev->ib_pool.mutex); |
1428 | serge | 130 | /* once scheduled IB is considered free and protected by the fence */ |
131 | ib->free = true; |
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1117 | serge | 132 | mutex_unlock(&rdev->ib_pool.mutex); |
1179 | serge | 133 | radeon_ring_unlock_commit(rdev); |
1117 | serge | 134 | return 0; |
135 | } |
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136 | |||
137 | int radeon_ib_pool_init(struct radeon_device *rdev) |
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138 | { |
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139 | void *ptr; |
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140 | uint64_t gpu_addr; |
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141 | int i; |
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142 | int r = 0; |
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143 | |||
1179 | serge | 144 | if (rdev->ib_pool.robj) |
145 | return 0; |
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1430 | serge | 146 | INIT_LIST_HEAD(&rdev->ib_pool.bogus_ib); |
1117 | serge | 147 | /* Allocate 1M object buffer */ |
1963 | serge | 148 | r = radeon_bo_create(rdev, RADEON_IB_POOL_SIZE*64*1024, |
149 | PAGE_SIZE, true, RADEON_GEM_DOMAIN_GTT, |
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1404 | serge | 150 | &rdev->ib_pool.robj); |
1117 | serge | 151 | if (r) { |
152 | DRM_ERROR("radeon: failed to ib pool (%d).\n", r); |
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153 | return r; |
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154 | } |
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1404 | serge | 155 | r = radeon_bo_reserve(rdev->ib_pool.robj, false); |
156 | if (unlikely(r != 0)) |
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157 | return r; |
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158 | r = radeon_bo_pin(rdev->ib_pool.robj, RADEON_GEM_DOMAIN_GTT, &gpu_addr); |
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1117 | serge | 159 | if (r) { |
1404 | serge | 160 | radeon_bo_unreserve(rdev->ib_pool.robj); |
1117 | serge | 161 | DRM_ERROR("radeon: failed to pin ib pool (%d).\n", r); |
162 | return r; |
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163 | } |
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1404 | serge | 164 | r = radeon_bo_kmap(rdev->ib_pool.robj, &ptr); |
165 | radeon_bo_unreserve(rdev->ib_pool.robj); |
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1117 | serge | 166 | if (r) { |
1963 | serge | 167 | DRM_ERROR("radeon: failed to map ib pool (%d).\n", r); |
1117 | serge | 168 | return r; |
169 | } |
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170 | for (i = 0; i < RADEON_IB_POOL_SIZE; i++) { |
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171 | unsigned offset; |
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172 | |||
173 | offset = i * 64 * 1024; |
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174 | rdev->ib_pool.ibs[i].gpu_addr = gpu_addr + offset; |
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175 | rdev->ib_pool.ibs[i].ptr = ptr + offset; |
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176 | rdev->ib_pool.ibs[i].idx = i; |
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177 | rdev->ib_pool.ibs[i].length_dw = 0; |
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1428 | serge | 178 | rdev->ib_pool.ibs[i].free = true; |
1117 | serge | 179 | } |
1428 | serge | 180 | rdev->ib_pool.head_id = 0; |
1117 | serge | 181 | rdev->ib_pool.ready = true; |
182 | DRM_INFO("radeon: ib pool ready.\n"); |
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1129 | serge | 183 | if (radeon_debugfs_ib_init(rdev)) { |
184 | DRM_ERROR("Failed to register debugfs file for IB !\n"); |
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185 | } |
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1117 | serge | 186 | return r; |
187 | } |
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188 | |||
189 | void radeon_ib_pool_fini(struct radeon_device *rdev) |
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190 | { |
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1404 | serge | 191 | int r; |
1963 | serge | 192 | struct radeon_bo *robj; |
1404 | serge | 193 | |
1117 | serge | 194 | if (!rdev->ib_pool.ready) { |
195 | return; |
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196 | } |
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1179 | serge | 197 | mutex_lock(&rdev->ib_pool.mutex); |
1963 | serge | 198 | // radeon_ib_bogus_cleanup(rdev); |
199 | robj = rdev->ib_pool.robj; |
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200 | rdev->ib_pool.robj = NULL; |
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201 | mutex_unlock(&rdev->ib_pool.mutex); |
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202 | |||
203 | if (robj) { |
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204 | r = radeon_bo_reserve(robj, false); |
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1404 | serge | 205 | if (likely(r == 0)) { |
1963 | serge | 206 | radeon_bo_kunmap(robj); |
207 | radeon_bo_unpin(robj); |
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208 | radeon_bo_unreserve(robj); |
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1404 | serge | 209 | } |
1963 | serge | 210 | radeon_bo_unref(&robj); |
1117 | serge | 211 | } |
212 | } |
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213 | |||
1120 | serge | 214 | |
1117 | serge | 215 | /* |
216 | * Ring. |
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217 | */ |
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218 | void radeon_ring_free_size(struct radeon_device *rdev) |
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219 | { |
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1963 | serge | 220 | if (rdev->wb.enabled) |
221 | rdev->cp.rptr = le32_to_cpu(rdev->wb.wb[RADEON_WB_CP_RPTR_OFFSET/4]); |
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222 | else { |
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1179 | serge | 223 | if (rdev->family >= CHIP_R600) |
224 | rdev->cp.rptr = RREG32(R600_CP_RB_RPTR); |
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225 | else |
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1117 | serge | 226 | rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR); |
1963 | serge | 227 | } |
1117 | serge | 228 | /* This works because ring_size is a power of 2 */ |
229 | rdev->cp.ring_free_dw = (rdev->cp.rptr + (rdev->cp.ring_size / 4)); |
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230 | rdev->cp.ring_free_dw -= rdev->cp.wptr; |
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231 | rdev->cp.ring_free_dw &= rdev->cp.ptr_mask; |
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232 | if (!rdev->cp.ring_free_dw) { |
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233 | rdev->cp.ring_free_dw = rdev->cp.ring_size / 4; |
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234 | } |
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235 | } |
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236 | |||
1963 | serge | 237 | int radeon_ring_alloc(struct radeon_device *rdev, unsigned ndw) |
1117 | serge | 238 | { |
239 | int r; |
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240 | |||
241 | /* Align requested size with padding so unlock_commit can |
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242 | * pad safely */ |
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243 | ndw = (ndw + rdev->cp.align_mask) & ~rdev->cp.align_mask; |
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244 | while (ndw > (rdev->cp.ring_free_dw - 1)) { |
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245 | radeon_ring_free_size(rdev); |
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246 | if (ndw < rdev->cp.ring_free_dw) { |
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247 | break; |
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248 | } |
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249 | // r = radeon_fence_wait_next(rdev); |
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250 | // if (r) { |
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251 | // mutex_unlock(&rdev->cp.mutex); |
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252 | // return r; |
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253 | // } |
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254 | } |
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255 | rdev->cp.count_dw = ndw; |
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256 | rdev->cp.wptr_old = rdev->cp.wptr; |
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257 | return 0; |
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258 | } |
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259 | |||
1963 | serge | 260 | int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw) |
1117 | serge | 261 | { |
1963 | serge | 262 | int r; |
263 | |||
264 | mutex_lock(&rdev->cp.mutex); |
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265 | r = radeon_ring_alloc(rdev, ndw); |
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266 | if (r) { |
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267 | mutex_unlock(&rdev->cp.mutex); |
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268 | return r; |
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269 | } |
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270 | return 0; |
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271 | } |
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272 | |||
273 | void radeon_ring_commit(struct radeon_device *rdev) |
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274 | { |
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1117 | serge | 275 | unsigned count_dw_pad; |
276 | unsigned i; |
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277 | |||
278 | /* We pad to match fetch size */ |
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279 | count_dw_pad = (rdev->cp.align_mask + 1) - |
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280 | (rdev->cp.wptr & rdev->cp.align_mask); |
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281 | for (i = 0; i < count_dw_pad; i++) { |
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1179 | serge | 282 | radeon_ring_write(rdev, 2 << 30); |
1117 | serge | 283 | } |
284 | DRM_MEMORYBARRIER(); |
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1179 | serge | 285 | radeon_cp_commit(rdev); |
1963 | serge | 286 | } |
287 | |||
288 | void radeon_ring_unlock_commit(struct radeon_device *rdev) |
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289 | { |
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290 | radeon_ring_commit(rdev); |
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1179 | serge | 291 | mutex_unlock(&rdev->cp.mutex); |
1117 | serge | 292 | } |
293 | |||
294 | void radeon_ring_unlock_undo(struct radeon_device *rdev) |
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295 | { |
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296 | rdev->cp.wptr = rdev->cp.wptr_old; |
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1179 | serge | 297 | mutex_unlock(&rdev->cp.mutex); |
1117 | serge | 298 | } |
299 | |||
300 | int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size) |
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301 | { |
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302 | int r; |
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303 | |||
304 | rdev->cp.ring_size = ring_size; |
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1120 | serge | 305 | /* Allocate ring buffer */ |
1117 | serge | 306 | if (rdev->cp.ring_obj == NULL) { |
1963 | serge | 307 | r = radeon_bo_create(rdev, rdev->cp.ring_size, PAGE_SIZE, true, |
1117 | serge | 308 | RADEON_GEM_DOMAIN_GTT, |
309 | &rdev->cp.ring_obj); |
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310 | if (r) { |
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1404 | serge | 311 | dev_err(rdev->dev, "(%d) ring create failed\n", r); |
1117 | serge | 312 | return r; |
313 | } |
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1404 | serge | 314 | r = radeon_bo_reserve(rdev->cp.ring_obj, false); |
315 | if (unlikely(r != 0)) |
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316 | return r; |
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317 | r = radeon_bo_pin(rdev->cp.ring_obj, RADEON_GEM_DOMAIN_GTT, |
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1117 | serge | 318 | &rdev->cp.gpu_addr); |
319 | if (r) { |
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1404 | serge | 320 | radeon_bo_unreserve(rdev->cp.ring_obj); |
321 | dev_err(rdev->dev, "(%d) ring pin failed\n", r); |
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1117 | serge | 322 | return r; |
323 | } |
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1404 | serge | 324 | r = radeon_bo_kmap(rdev->cp.ring_obj, |
1117 | serge | 325 | (void **)&rdev->cp.ring); |
1404 | serge | 326 | radeon_bo_unreserve(rdev->cp.ring_obj); |
1117 | serge | 327 | if (r) { |
1404 | serge | 328 | dev_err(rdev->dev, "(%d) ring map failed\n", r); |
1117 | serge | 329 | return r; |
330 | } |
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331 | } |
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332 | rdev->cp.ptr_mask = (rdev->cp.ring_size / 4) - 1; |
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333 | rdev->cp.ring_free_dw = rdev->cp.ring_size / 4; |
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334 | return 0; |
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335 | } |
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336 | |||
337 | void radeon_ring_fini(struct radeon_device *rdev) |
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338 | { |
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1404 | serge | 339 | int r; |
1963 | serge | 340 | struct radeon_bo *ring_obj; |
1404 | serge | 341 | |
1179 | serge | 342 | mutex_lock(&rdev->cp.mutex); |
1963 | serge | 343 | ring_obj = rdev->cp.ring_obj; |
344 | rdev->cp.ring = NULL; |
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345 | rdev->cp.ring_obj = NULL; |
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346 | mutex_unlock(&rdev->cp.mutex); |
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347 | |||
348 | if (ring_obj) { |
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349 | r = radeon_bo_reserve(ring_obj, false); |
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1404 | serge | 350 | if (likely(r == 0)) { |
1963 | serge | 351 | radeon_bo_kunmap(ring_obj); |
352 | radeon_bo_unpin(ring_obj); |
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353 | radeon_bo_unreserve(ring_obj); |
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1404 | serge | 354 | } |
1963 | serge | 355 | radeon_bo_unref(&ring_obj); |
1117 | serge | 356 | } |
357 | } |
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358 | |||
359 | |||
360 | /* |
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361 | * Debugfs info |
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362 | */ |
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363 | #if defined(CONFIG_DEBUG_FS) |
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364 | static int radeon_debugfs_ib_info(struct seq_file *m, void *data) |
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365 | { |
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366 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
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367 | struct radeon_ib *ib = node->info_ent->data; |
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368 | unsigned i; |
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369 | |||
370 | if (ib == NULL) { |
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371 | return 0; |
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372 | } |
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1428 | serge | 373 | seq_printf(m, "IB %04u\n", ib->idx); |
1117 | serge | 374 | seq_printf(m, "IB fence %p\n", ib->fence); |
375 | seq_printf(m, "IB size %05u dwords\n", ib->length_dw); |
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376 | for (i = 0; i < ib->length_dw; i++) { |
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377 | seq_printf(m, "[%05u]=0x%08X\n", i, ib->ptr[i]); |
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378 | } |
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379 | return 0; |
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380 | } |
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381 | |||
1963 | serge | 382 | static int radeon_debugfs_ib_bogus_info(struct seq_file *m, void *data) |
383 | { |
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384 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
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385 | struct radeon_device *rdev = node->info_ent->data; |
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386 | struct radeon_ib *ib; |
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387 | unsigned i; |
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388 | |||
389 | mutex_lock(&rdev->ib_pool.mutex); |
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390 | if (list_empty(&rdev->ib_pool.bogus_ib)) { |
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391 | mutex_unlock(&rdev->ib_pool.mutex); |
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392 | seq_printf(m, "no bogus IB recorded\n"); |
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393 | return 0; |
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394 | } |
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395 | ib = list_first_entry(&rdev->ib_pool.bogus_ib, struct radeon_ib, list); |
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396 | list_del_init(&ib->list); |
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397 | mutex_unlock(&rdev->ib_pool.mutex); |
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398 | seq_printf(m, "IB size %05u dwords\n", ib->length_dw); |
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399 | for (i = 0; i < ib->length_dw; i++) { |
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400 | seq_printf(m, "[%05u]=0x%08X\n", i, ib->ptr[i]); |
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401 | } |
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402 | vfree(ib->ptr); |
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403 | kfree(ib); |
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404 | return 0; |
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405 | } |
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406 | |||
1117 | serge | 407 | static struct drm_info_list radeon_debugfs_ib_list[RADEON_IB_POOL_SIZE]; |
408 | static char radeon_debugfs_ib_names[RADEON_IB_POOL_SIZE][32]; |
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1963 | serge | 409 | |
410 | static struct drm_info_list radeon_debugfs_ib_bogus_info_list[] = { |
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411 | {"radeon_ib_bogus", radeon_debugfs_ib_bogus_info, 0, NULL}, |
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412 | }; |
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1117 | serge | 413 | #endif |
414 | |||
415 | int radeon_debugfs_ib_init(struct radeon_device *rdev) |
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416 | { |
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417 | #if defined(CONFIG_DEBUG_FS) |
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418 | unsigned i; |
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1430 | serge | 419 | int r; |
1117 | serge | 420 | |
1430 | serge | 421 | radeon_debugfs_ib_bogus_info_list[0].data = rdev; |
422 | r = radeon_debugfs_add_files(rdev, radeon_debugfs_ib_bogus_info_list, 1); |
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423 | if (r) |
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424 | return r; |
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1117 | serge | 425 | for (i = 0; i < RADEON_IB_POOL_SIZE; i++) { |
426 | sprintf(radeon_debugfs_ib_names[i], "radeon_ib_%04u", i); |
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427 | radeon_debugfs_ib_list[i].name = radeon_debugfs_ib_names[i]; |
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428 | radeon_debugfs_ib_list[i].show = &radeon_debugfs_ib_info; |
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429 | radeon_debugfs_ib_list[i].driver_features = 0; |
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430 | radeon_debugfs_ib_list[i].data = &rdev->ib_pool.ibs[i]; |
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431 | } |
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432 | return radeon_debugfs_add_files(rdev, radeon_debugfs_ib_list, |
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433 | RADEON_IB_POOL_SIZE); |
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434 | #else |
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435 | return 0; |
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436 | #endif |
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437 | }>>>><>>>>> |