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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 1268 | serge | 1 | /* |
| 2 | * Permission is hereby granted, free of charge, to any person obtaining a |
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| 3 | * copy of this software and associated documentation files (the "Software"), |
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| 4 | * to deal in the Software without restriction, including without limitation |
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| 5 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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| 6 | * and/or sell copies of the Software, and to permit persons to whom the |
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| 7 | * Software is furnished to do so, subject to the following conditions: |
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| 8 | * |
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| 9 | * The above copyright notice and this permission notice shall be included in |
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| 10 | * all copies or substantial portions of the Software. |
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| 11 | * |
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| 12 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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| 13 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| 14 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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| 15 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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| 16 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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| 17 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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| 18 | * OTHER DEALINGS IN THE SOFTWARE. |
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| 19 | * |
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| 20 | * Authors: Rafał Miłecki |
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| 1430 | serge | 21 | * Alex Deucher |
| 1268 | serge | 22 | */ |
| 23 | #include "drmP.h" |
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| 24 | #include "radeon.h" |
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| 1430 | serge | 25 | #include "avivod.h" |
| 1268 | serge | 26 | |
| 1430 | serge | 27 | #define RADEON_IDLE_LOOP_MS 100 |
| 28 | #define RADEON_RECLOCK_DELAY_MS 200 |
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| 29 | #define RADEON_WAIT_VBLANK_TIMEOUT 200 |
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| 1268 | serge | 30 | |
| 1430 | serge | 31 | static void radeon_pm_set_clocks_locked(struct radeon_device *rdev); |
| 32 | static void radeon_pm_set_clocks(struct radeon_device *rdev); |
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| 33 | static void radeon_pm_idle_work_handler(struct work_struct *work); |
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| 34 | static int radeon_debugfs_pm_init(struct radeon_device *rdev); |
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| 35 | |||
| 36 | static const char *pm_state_names[4] = { |
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| 37 | "PM_STATE_DISABLED", |
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| 38 | "PM_STATE_MINIMUM", |
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| 39 | "PM_STATE_PAUSED", |
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| 40 | "PM_STATE_ACTIVE" |
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| 41 | }; |
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| 42 | |||
| 43 | static const char *pm_state_types[5] = { |
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| 44 | "Default", |
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| 45 | "Powersave", |
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| 46 | "Battery", |
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| 47 | "Balanced", |
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| 48 | "Performance", |
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| 49 | }; |
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| 50 | |||
| 51 | static void radeon_print_power_mode_info(struct radeon_device *rdev) |
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| 52 | { |
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| 53 | int i, j; |
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| 54 | bool is_default; |
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| 55 | |||
| 56 | DRM_INFO("%d Power State(s)\n", rdev->pm.num_power_states); |
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| 57 | for (i = 0; i < rdev->pm.num_power_states; i++) { |
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| 58 | if (rdev->pm.default_power_state == &rdev->pm.power_state[i]) |
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| 59 | is_default = true; |
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| 60 | else |
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| 61 | is_default = false; |
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| 62 | DRM_INFO("State %d %s %s\n", i, |
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| 63 | pm_state_types[rdev->pm.power_state[i].type], |
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| 64 | is_default ? "(default)" : ""); |
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| 65 | if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP)) |
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| 66 | DRM_INFO("\t%d PCIE Lanes\n", rdev->pm.power_state[i].non_clock_info.pcie_lanes); |
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| 67 | DRM_INFO("\t%d Clock Mode(s)\n", rdev->pm.power_state[i].num_clock_modes); |
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| 68 | for (j = 0; j < rdev->pm.power_state[i].num_clock_modes; j++) { |
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| 69 | if (rdev->flags & RADEON_IS_IGP) |
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| 70 | DRM_INFO("\t\t%d engine: %d\n", |
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| 71 | j, |
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| 72 | rdev->pm.power_state[i].clock_info[j].sclk * 10); |
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| 73 | else |
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| 74 | DRM_INFO("\t\t%d engine/memory: %d/%d\n", |
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| 75 | j, |
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| 76 | rdev->pm.power_state[i].clock_info[j].sclk * 10, |
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| 77 | rdev->pm.power_state[i].clock_info[j].mclk * 10); |
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| 78 | } |
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| 79 | } |
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| 80 | } |
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| 81 | |||
| 82 | static struct radeon_power_state * radeon_pick_power_state(struct radeon_device *rdev, |
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| 83 | enum radeon_pm_state_type type) |
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| 84 | { |
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| 85 | int i, j; |
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| 86 | enum radeon_pm_state_type wanted_types[2]; |
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| 87 | int wanted_count; |
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| 88 | |||
| 89 | switch (type) { |
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| 90 | case POWER_STATE_TYPE_DEFAULT: |
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| 91 | default: |
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| 92 | return rdev->pm.default_power_state; |
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| 93 | case POWER_STATE_TYPE_POWERSAVE: |
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| 94 | if (rdev->flags & RADEON_IS_MOBILITY) { |
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| 95 | wanted_types[0] = POWER_STATE_TYPE_POWERSAVE; |
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| 96 | wanted_types[1] = POWER_STATE_TYPE_BATTERY; |
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| 97 | wanted_count = 2; |
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| 98 | } else { |
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| 99 | wanted_types[0] = POWER_STATE_TYPE_PERFORMANCE; |
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| 100 | wanted_count = 1; |
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| 101 | } |
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| 102 | break; |
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| 103 | case POWER_STATE_TYPE_BATTERY: |
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| 104 | if (rdev->flags & RADEON_IS_MOBILITY) { |
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| 105 | wanted_types[0] = POWER_STATE_TYPE_BATTERY; |
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| 106 | wanted_types[1] = POWER_STATE_TYPE_POWERSAVE; |
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| 107 | wanted_count = 2; |
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| 108 | } else { |
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| 109 | wanted_types[0] = POWER_STATE_TYPE_PERFORMANCE; |
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| 110 | wanted_count = 1; |
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| 111 | } |
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| 112 | break; |
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| 113 | case POWER_STATE_TYPE_BALANCED: |
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| 114 | case POWER_STATE_TYPE_PERFORMANCE: |
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| 115 | wanted_types[0] = type; |
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| 116 | wanted_count = 1; |
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| 117 | break; |
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| 118 | } |
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| 119 | |||
| 120 | for (i = 0; i < wanted_count; i++) { |
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| 121 | for (j = 0; j < rdev->pm.num_power_states; j++) { |
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| 122 | if (rdev->pm.power_state[j].type == wanted_types[i]) |
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| 123 | return &rdev->pm.power_state[j]; |
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| 124 | } |
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| 125 | } |
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| 126 | |||
| 127 | return rdev->pm.default_power_state; |
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| 128 | } |
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| 129 | |||
| 130 | static struct radeon_pm_clock_info * radeon_pick_clock_mode(struct radeon_device *rdev, |
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| 131 | struct radeon_power_state *power_state, |
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| 132 | enum radeon_pm_clock_mode_type type) |
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| 133 | { |
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| 134 | switch (type) { |
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| 135 | case POWER_MODE_TYPE_DEFAULT: |
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| 136 | default: |
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| 137 | return power_state->default_clock_mode; |
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| 138 | case POWER_MODE_TYPE_LOW: |
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| 139 | return &power_state->clock_info[0]; |
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| 140 | case POWER_MODE_TYPE_MID: |
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| 141 | if (power_state->num_clock_modes > 2) |
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| 142 | return &power_state->clock_info[1]; |
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| 143 | else |
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| 144 | return &power_state->clock_info[0]; |
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| 145 | break; |
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| 146 | case POWER_MODE_TYPE_HIGH: |
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| 147 | return &power_state->clock_info[power_state->num_clock_modes - 1]; |
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| 148 | } |
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| 149 | |||
| 150 | } |
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| 151 | |||
| 152 | static void radeon_get_power_state(struct radeon_device *rdev, |
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| 153 | enum radeon_pm_action action) |
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| 154 | { |
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| 155 | switch (action) { |
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| 156 | case PM_ACTION_MINIMUM: |
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| 157 | rdev->pm.requested_power_state = radeon_pick_power_state(rdev, POWER_STATE_TYPE_BATTERY); |
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| 158 | rdev->pm.requested_clock_mode = |
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| 159 | radeon_pick_clock_mode(rdev, rdev->pm.requested_power_state, POWER_MODE_TYPE_LOW); |
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| 160 | break; |
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| 161 | case PM_ACTION_DOWNCLOCK: |
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| 162 | rdev->pm.requested_power_state = radeon_pick_power_state(rdev, POWER_STATE_TYPE_POWERSAVE); |
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| 163 | rdev->pm.requested_clock_mode = |
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| 164 | radeon_pick_clock_mode(rdev, rdev->pm.requested_power_state, POWER_MODE_TYPE_MID); |
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| 165 | break; |
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| 166 | case PM_ACTION_UPCLOCK: |
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| 167 | rdev->pm.requested_power_state = radeon_pick_power_state(rdev, POWER_STATE_TYPE_DEFAULT); |
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| 168 | rdev->pm.requested_clock_mode = |
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| 169 | radeon_pick_clock_mode(rdev, rdev->pm.requested_power_state, POWER_MODE_TYPE_HIGH); |
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| 170 | break; |
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| 171 | case PM_ACTION_NONE: |
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| 172 | default: |
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| 173 | DRM_ERROR("Requested mode for not defined action\n"); |
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| 174 | return; |
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| 175 | } |
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| 176 | DRM_INFO("Requested: e: %d m: %d p: %d\n", |
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| 177 | rdev->pm.requested_clock_mode->sclk, |
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| 178 | rdev->pm.requested_clock_mode->mclk, |
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| 179 | rdev->pm.requested_power_state->non_clock_info.pcie_lanes); |
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| 180 | } |
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| 181 | |||
| 182 | static void radeon_set_power_state(struct radeon_device *rdev) |
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| 183 | { |
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| 184 | /* if *_clock_mode are the same, *_power_state are as well */ |
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| 185 | if (rdev->pm.requested_clock_mode == rdev->pm.current_clock_mode) |
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| 186 | return; |
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| 187 | |||
| 188 | DRM_INFO("Setting: e: %d m: %d p: %d\n", |
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| 189 | rdev->pm.requested_clock_mode->sclk, |
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| 190 | rdev->pm.requested_clock_mode->mclk, |
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| 191 | rdev->pm.requested_power_state->non_clock_info.pcie_lanes); |
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| 192 | /* set pcie lanes */ |
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| 193 | /* set voltage */ |
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| 194 | /* set engine clock */ |
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| 195 | radeon_set_engine_clock(rdev, rdev->pm.requested_clock_mode->sclk); |
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| 196 | /* set memory clock */ |
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| 197 | |||
| 198 | rdev->pm.current_power_state = rdev->pm.requested_power_state; |
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| 199 | rdev->pm.current_clock_mode = rdev->pm.requested_clock_mode; |
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| 200 | } |
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| 201 | |||
| 1268 | serge | 202 | int radeon_pm_init(struct radeon_device *rdev) |
| 203 | { |
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| 1430 | serge | 204 | rdev->pm.state = PM_STATE_DISABLED; |
| 205 | rdev->pm.planned_action = PM_ACTION_NONE; |
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| 206 | rdev->pm.downclocked = false; |
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| 207 | |||
| 208 | if (rdev->bios) { |
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| 209 | if (rdev->is_atom_bios) |
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| 210 | radeon_atombios_get_power_modes(rdev); |
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| 211 | else |
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| 212 | radeon_combios_get_power_modes(rdev); |
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| 213 | radeon_print_power_mode_info(rdev); |
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| 214 | } |
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| 215 | |||
| 1268 | serge | 216 | if (radeon_debugfs_pm_init(rdev)) { |
| 1321 | serge | 217 | DRM_ERROR("Failed to register debugfs file for PM!\n"); |
| 1268 | serge | 218 | } |
| 219 | |||
| 1430 | serge | 220 | // INIT_DELAYED_WORK(&rdev->pm.idle_work, radeon_pm_idle_work_handler); |
| 221 | |||
| 222 | if (radeon_dynpm != -1 && radeon_dynpm) { |
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| 223 | rdev->pm.state = PM_STATE_PAUSED; |
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| 224 | DRM_INFO("radeon: dynamic power management enabled\n"); |
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| 225 | } |
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| 226 | |||
| 227 | DRM_INFO("radeon: power management initialized\n"); |
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| 228 | |||
| 1268 | serge | 229 | return 0; |
| 230 | } |
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| 231 | |||
| 1430 | serge | 232 | void radeon_pm_compute_clocks(struct radeon_device *rdev) |
| 233 | { |
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| 234 | struct drm_device *ddev = rdev->ddev; |
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| 235 | struct drm_connector *connector; |
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| 236 | struct radeon_crtc *radeon_crtc; |
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| 237 | int count = 0; |
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| 238 | |||
| 239 | if (rdev->pm.state == PM_STATE_DISABLED) |
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| 240 | return; |
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| 241 | |||
| 242 | mutex_lock(&rdev->pm.mutex); |
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| 243 | |||
| 244 | rdev->pm.active_crtcs = 0; |
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| 245 | list_for_each_entry(connector, |
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| 246 | &ddev->mode_config.connector_list, head) { |
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| 247 | if (connector->encoder && |
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| 248 | connector->dpms != DRM_MODE_DPMS_OFF) { |
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| 249 | radeon_crtc = to_radeon_crtc(connector->encoder->crtc); |
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| 250 | rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id); |
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| 251 | ++count; |
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| 252 | } |
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| 253 | } |
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| 254 | |||
| 255 | if (count > 1) { |
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| 256 | if (rdev->pm.state == PM_STATE_ACTIVE) { |
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| 257 | |||
| 258 | rdev->pm.state = PM_STATE_PAUSED; |
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| 259 | rdev->pm.planned_action = PM_ACTION_UPCLOCK; |
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| 260 | if (rdev->pm.downclocked) |
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| 261 | radeon_pm_set_clocks(rdev); |
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| 262 | |||
| 263 | DRM_DEBUG("radeon: dynamic power management deactivated\n"); |
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| 264 | } |
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| 265 | } else if (count == 1) { |
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| 266 | /* TODO: Increase clocks if needed for current mode */ |
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| 267 | |||
| 268 | if (rdev->pm.state == PM_STATE_MINIMUM) { |
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| 269 | rdev->pm.state = PM_STATE_ACTIVE; |
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| 270 | rdev->pm.planned_action = PM_ACTION_UPCLOCK; |
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| 271 | radeon_pm_set_clocks(rdev); |
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| 272 | } |
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| 273 | else if (rdev->pm.state == PM_STATE_PAUSED) { |
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| 274 | rdev->pm.state = PM_STATE_ACTIVE; |
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| 275 | DRM_DEBUG("radeon: dynamic power management activated\n"); |
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| 276 | } |
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| 277 | } |
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| 278 | else { /* count == 0 */ |
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| 279 | if (rdev->pm.state != PM_STATE_MINIMUM) { |
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| 280 | rdev->pm.state = PM_STATE_MINIMUM; |
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| 281 | rdev->pm.planned_action = PM_ACTION_MINIMUM; |
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| 282 | radeon_pm_set_clocks(rdev); |
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| 283 | } |
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| 284 | } |
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| 285 | |||
| 286 | mutex_unlock(&rdev->pm.mutex); |
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| 287 | } |
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| 288 | |||
| 289 | static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish) |
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| 290 | { |
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| 291 | u32 stat_crtc1 = 0, stat_crtc2 = 0; |
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| 292 | bool in_vbl = true; |
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| 293 | |||
| 294 | if (ASIC_IS_AVIVO(rdev)) { |
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| 295 | if (rdev->pm.active_crtcs & (1 << 0)) { |
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| 296 | stat_crtc1 = RREG32(D1CRTC_STATUS); |
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| 297 | if (!(stat_crtc1 & 1)) |
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| 298 | in_vbl = false; |
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| 299 | } |
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| 300 | if (rdev->pm.active_crtcs & (1 << 1)) { |
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| 301 | stat_crtc2 = RREG32(D2CRTC_STATUS); |
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| 302 | if (!(stat_crtc2 & 1)) |
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| 303 | in_vbl = false; |
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| 304 | } |
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| 305 | } |
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| 306 | if (in_vbl == false) |
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| 307 | DRM_INFO("not in vbl for pm change %08x %08x at %s\n", stat_crtc1, |
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| 308 | stat_crtc2, finish ? "exit" : "entry"); |
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| 309 | return in_vbl; |
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| 310 | } |
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| 311 | static void radeon_pm_set_clocks_locked(struct radeon_device *rdev) |
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| 312 | { |
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| 313 | /*radeon_fence_wait_last(rdev);*/ |
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| 314 | switch (rdev->pm.planned_action) { |
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| 315 | case PM_ACTION_UPCLOCK: |
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| 316 | rdev->pm.downclocked = false; |
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| 317 | break; |
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| 318 | case PM_ACTION_DOWNCLOCK: |
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| 319 | rdev->pm.downclocked = true; |
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| 320 | break; |
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| 321 | case PM_ACTION_MINIMUM: |
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| 322 | break; |
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| 323 | case PM_ACTION_NONE: |
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| 324 | DRM_ERROR("%s: PM_ACTION_NONE\n", __func__); |
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| 325 | break; |
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| 326 | } |
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| 327 | |||
| 328 | /* check if we are in vblank */ |
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| 329 | radeon_pm_debug_check_in_vbl(rdev, false); |
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| 330 | radeon_set_power_state(rdev); |
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| 331 | radeon_pm_debug_check_in_vbl(rdev, true); |
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| 332 | rdev->pm.planned_action = PM_ACTION_NONE; |
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| 333 | } |
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| 334 | |||
| 335 | static void radeon_pm_set_clocks(struct radeon_device *rdev) |
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| 336 | { |
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| 337 | radeon_get_power_state(rdev, rdev->pm.planned_action); |
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| 338 | mutex_lock(&rdev->cp.mutex); |
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| 339 | |||
| 340 | if (rdev->pm.active_crtcs & (1 << 0)) { |
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| 341 | rdev->pm.req_vblank |= (1 << 0); |
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| 342 | // drm_vblank_get(rdev->ddev, 0); |
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| 343 | } |
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| 344 | if (rdev->pm.active_crtcs & (1 << 1)) { |
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| 345 | rdev->pm.req_vblank |= (1 << 1); |
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| 346 | // drm_vblank_get(rdev->ddev, 1); |
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| 347 | } |
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| 348 | if (rdev->pm.active_crtcs) |
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| 349 | // wait_event_interruptible_timeout( |
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| 350 | // rdev->irq.vblank_queue, 0, |
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| 351 | // msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT)); |
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| 352 | if (rdev->pm.req_vblank & (1 << 0)) { |
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| 353 | rdev->pm.req_vblank &= ~(1 << 0); |
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| 354 | // drm_vblank_put(rdev->ddev, 0); |
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| 355 | } |
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| 356 | if (rdev->pm.req_vblank & (1 << 1)) { |
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| 357 | rdev->pm.req_vblank &= ~(1 << 1); |
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| 358 | // drm_vblank_put(rdev->ddev, 1); |
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| 359 | } |
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| 360 | |||
| 361 | radeon_pm_set_clocks_locked(rdev); |
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| 362 | mutex_unlock(&rdev->cp.mutex); |
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| 363 | } |
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| 364 | |||
| 365 | #if 0 |
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| 366 | static void radeon_pm_idle_work_handler(struct work_struct *work) |
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| 367 | { |
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| 368 | struct radeon_device *rdev; |
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| 369 | rdev = container_of(work, struct radeon_device, |
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| 370 | pm.idle_work.work); |
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| 371 | |||
| 372 | mutex_lock(&rdev->pm.mutex); |
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| 373 | if (rdev->pm.state == PM_STATE_ACTIVE) { |
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| 374 | unsigned long irq_flags; |
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| 375 | int not_processed = 0; |
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| 376 | |||
| 377 | read_lock_irqsave(&rdev->fence_drv.lock, irq_flags); |
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| 378 | if (!list_empty(&rdev->fence_drv.emited)) { |
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| 379 | struct list_head *ptr; |
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| 380 | list_for_each(ptr, &rdev->fence_drv.emited) { |
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| 381 | /* count up to 3, that's enought info */ |
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| 382 | if (++not_processed >= 3) |
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| 383 | break; |
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| 384 | } |
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| 385 | } |
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| 386 | read_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags); |
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| 387 | |||
| 388 | if (not_processed >= 3) { /* should upclock */ |
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| 389 | if (rdev->pm.planned_action == PM_ACTION_DOWNCLOCK) { |
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| 390 | rdev->pm.planned_action = PM_ACTION_NONE; |
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| 391 | } else if (rdev->pm.planned_action == PM_ACTION_NONE && |
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| 392 | rdev->pm.downclocked) { |
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| 393 | rdev->pm.planned_action = |
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| 394 | PM_ACTION_UPCLOCK; |
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| 395 | rdev->pm.action_timeout = jiffies + |
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| 396 | msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS); |
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| 397 | } |
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| 398 | } else if (not_processed == 0) { /* should downclock */ |
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| 399 | if (rdev->pm.planned_action == PM_ACTION_UPCLOCK) { |
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| 400 | rdev->pm.planned_action = PM_ACTION_NONE; |
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| 401 | } else if (rdev->pm.planned_action == PM_ACTION_NONE && |
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| 402 | !rdev->pm.downclocked) { |
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| 403 | rdev->pm.planned_action = |
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| 404 | PM_ACTION_DOWNCLOCK; |
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| 405 | rdev->pm.action_timeout = jiffies + |
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| 406 | msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS); |
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| 407 | } |
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| 408 | } |
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| 409 | |||
| 410 | if (rdev->pm.planned_action != PM_ACTION_NONE && |
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| 411 | jiffies > rdev->pm.action_timeout) { |
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| 412 | radeon_pm_set_clocks(rdev); |
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| 413 | } |
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| 414 | } |
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| 415 | mutex_unlock(&rdev->pm.mutex); |
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| 416 | |||
| 417 | queue_delayed_work(rdev->wq, &rdev->pm.idle_work, |
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| 418 | msecs_to_jiffies(RADEON_IDLE_LOOP_MS)); |
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| 419 | } |
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| 420 | #endif |
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| 421 | |||
| 1268 | serge | 422 | /* |
| 423 | * Debugfs info |
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| 424 | */ |
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| 425 | #if defined(CONFIG_DEBUG_FS) |
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| 426 | |||
| 427 | static int radeon_debugfs_pm_info(struct seq_file *m, void *data) |
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| 428 | { |
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| 429 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
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| 430 | struct drm_device *dev = node->minor->dev; |
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| 431 | struct radeon_device *rdev = dev->dev_private; |
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| 432 | |||
| 1430 | serge | 433 | seq_printf(m, "state: %s\n", pm_state_names[rdev->pm.state]); |
| 1404 | serge | 434 | seq_printf(m, "default engine clock: %u0 kHz\n", rdev->clock.default_sclk); |
| 435 | seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev)); |
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| 436 | seq_printf(m, "default memory clock: %u0 kHz\n", rdev->clock.default_mclk); |
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| 437 | if (rdev->asic->get_memory_clock) |
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| 438 | seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev)); |
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| 1430 | serge | 439 | if (rdev->asic->get_pcie_lanes) |
| 440 | seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev)); |
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| 1268 | serge | 441 | |
| 442 | return 0; |
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| 443 | } |
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| 444 | |||
| 445 | static struct drm_info_list radeon_pm_info_list[] = { |
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| 446 | {"radeon_pm_info", radeon_debugfs_pm_info, 0, NULL}, |
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| 447 | }; |
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| 448 | #endif |
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| 449 | |||
| 1430 | serge | 450 | static int radeon_debugfs_pm_init(struct radeon_device *rdev) |
| 1268 | serge | 451 | { |
| 452 | #if defined(CONFIG_DEBUG_FS) |
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| 453 | return radeon_debugfs_add_files(rdev, radeon_pm_info_list, ARRAY_SIZE(radeon_pm_info_list)); |
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| 454 | #else |
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| 455 | return 0; |
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| 456 | #endif |
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| 457 | } |