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Rev | Author | Line No. | Line |
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1404 | serge | 1 | |
2 | #include |
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3 | #include "radeon_drm.h" |
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4 | #include "radeon.h" |
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5 | |||
6 | |||
7 | |||
8 | static struct drm_mm mm_vram; |
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9 | |||
10 | |||
11 | struct drm_mm_node **node) |
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12 | { |
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13 | struct drm_mm_node *vm_node; |
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14 | int r; |
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15 | |||
16 | |||
17 | |||
18 | |||
19 | |||
20 | |||
21 | return r; |
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22 | |||
23 | |||
24 | |||
25 | |||
26 | r = -ENOMEM; |
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27 | return r; |
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28 | } |
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29 | |||
30 | |||
31 | |||
32 | |||
33 | goto retry_pre_get; |
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34 | } |
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35 | |||
36 | |||
37 | }; |
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38 | |||
39 | |||
40 | |||
41 | { |
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42 | u32 c = 0; |
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43 | |||
44 | |||
45 | rbo->placement.lpfn = 0; |
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46 | rbo->placement.placement = rbo->placements; |
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47 | rbo->placement.busy_placement = rbo->placements; |
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48 | if (domain & RADEON_GEM_DOMAIN_VRAM) |
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49 | rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED | |
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50 | TTM_PL_FLAG_VRAM; |
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51 | if (domain & RADEON_GEM_DOMAIN_GTT) |
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52 | rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT; |
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53 | if (domain & RADEON_GEM_DOMAIN_CPU) |
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54 | rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM; |
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55 | if (!c) |
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56 | rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM; |
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57 | rbo->placement.num_placement = c; |
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58 | rbo->placement.num_busy_placement = c; |
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59 | } |
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60 | |||
61 | |||
62 | |||
63 | { |
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64 | int r; |
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65 | |||
66 | |||
67 | rdev->mc.mc_vram_size >> 20, |
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68 | (unsigned long long)rdev->mc.aper_size >> 20); |
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69 | DRM_INFO("RAM width %dbits %cDR\n", |
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70 | rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S'); |
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71 | |||
72 | |||
73 | ((rdev->mc.real_vram_size - 0xC00000) >> PAGE_SHIFT)); |
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74 | if (r) { |
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75 | DRM_ERROR("Failed initializing VRAM heap.\n"); |
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76 | return r; |
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77 | }; |
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78 | |||
79 | |||
80 | if (r) { |
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81 | DRM_ERROR("Failed initializing GTT heap.\n"); |
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82 | return r; |
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83 | } |
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84 | |||
85 | |||
86 | } |
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87 | |||
88 | |||
89 | |||
90 | { |
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91 | int r; |
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92 | |||
93 | |||
94 | |||
95 | |||
96 | } |
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97 | |||
98 | |||
99 | { |
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100 | bo->reserved.counter = 1; |
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101 | } |
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102 | |||
103 | |||
104 | unsigned long size, bool kernel, u32 domain, |
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105 | struct radeon_bo **bo_ptr) |
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106 | { |
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107 | enum ttm_bo_type type; |
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108 | |||
109 | |||
110 | size_t num_pages; |
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111 | struct drm_mm *mman; |
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112 | u32 bo_domain; |
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113 | int r; |
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114 | |||
115 | |||
116 | |||
117 | |||
118 | dbgprintf("Illegal buffer object size.\n"); |
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119 | return -EINVAL; |
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120 | } |
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121 | |||
122 | |||
123 | { |
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124 | mman = &mm_vram; |
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125 | bo_domain = RADEON_GEM_DOMAIN_VRAM; |
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126 | } |
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127 | else if(domain & RADEON_GEM_DOMAIN_GTT) |
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128 | { |
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129 | mman = &mm_gtt; |
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130 | bo_domain = RADEON_GEM_DOMAIN_GTT; |
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131 | } |
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132 | else return -EINVAL; |
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133 | |||
134 | |||
135 | type = ttm_bo_type_kernel; |
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136 | } else { |
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137 | type = ttm_bo_type_device; |
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138 | } |
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139 | *bo_ptr = NULL; |
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140 | bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL); |
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141 | if (bo == NULL) |
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142 | return -ENOMEM; |
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143 | |||
144 | |||
145 | bo->gobj = gobj; |
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146 | bo->surface_reg = -1; |
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147 | bo->tbo.num_pages = num_pages; |
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148 | bo->domain = domain; |
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149 | |||
150 | |||
151 | |||
152 | |||
153 | /* Kernel allocation are uninterruptible */ |
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154 | |||
155 | |||
156 | if (unlikely(r != 0)) |
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157 | return r; |
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158 | |||
159 | |||
160 | |||
161 | |||
162 | } |
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163 | |||
164 | |||
165 | |||
166 | |||
167 | { |
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168 | int r=0, i; |
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169 | |||
170 | |||
171 | bo->pin_count++; |
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172 | if (gpu_addr) |
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173 | *gpu_addr = radeon_bo_gpu_offset(bo); |
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174 | return 0; |
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175 | } |
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176 | |||
177 | |||
178 | |||
179 | |||
180 | { |
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181 | bo->tbo.offset += (u64)bo->rdev->mc.vram_start; |
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1430 | serge | 182 | } |
1404 | serge | 183 | else if (bo->domain & RADEON_GEM_DOMAIN_GTT) |
184 | { |
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185 | u32_t *pagelist; |
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186 | bo->kptr = KernelAlloc( bo->tbo.num_pages << PAGE_SHIFT ); |
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187 | dbgprintf("kernel alloc %x\n", bo->kptr ); |
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188 | |||
189 | |||
190 | dbgprintf("pagelist %x\n", pagelist); |
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191 | radeon_gart_bind(bo->rdev, bo->tbo.offset, |
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192 | bo->tbo.vm_node->size, pagelist); |
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193 | bo->tbo.offset += (u64)bo->rdev->mc.gtt_start; |
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1430 | serge | 194 | } |
1404 | serge | 195 | else |
196 | { |
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197 | DRM_ERROR("Unknown placement %x\n", bo->domain); |
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198 | bo->tbo.offset = -1; |
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199 | r = -1; |
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200 | }; |
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201 | |||
202 | |||
203 | DRM_ERROR("radeon: failed to pin object.\n"); |
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204 | } |
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205 | |||
206 | |||
207 | bo->pin_count = 1; |
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208 | if (gpu_addr != NULL) |
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209 | *gpu_addr = radeon_bo_gpu_offset(bo); |
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210 | } |
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211 | |||
212 | |||
213 | dev_err(bo->rdev->dev, "%p pin failed\n", bo); |
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214 | return r; |
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215 | }; |
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216 | |||
217 | |||
218 | { |
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219 | int r = 0; |
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220 | |||
221 | |||
222 | dev_warn(bo->rdev->dev, "%p unpin not necessary\n", bo); |
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223 | return 0; |
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224 | } |
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225 | bo->pin_count--; |
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226 | if (bo->pin_count) |
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227 | return 0; |
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228 | |||
229 | |||
230 | { |
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231 | drm_mm_put_block(bo->tbo.vm_node); |
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232 | bo->tbo.vm_node = NULL; |
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233 | }; |
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234 | |||
235 | |||
236 | } |
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237 | |||
238 | |||
239 | { |
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240 | bool is_iomem; |
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241 | |||
242 | |||
243 | if (ptr) { |
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244 | *ptr = bo->kptr; |
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245 | } |
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246 | return 0; |
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247 | } |
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248 | |||
249 | |||
250 | { |
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251 | bo->cpu_addr = bo->rdev->mc.aper_base + |
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252 | (bo->tbo.vm_node->start << PAGE_SHIFT); |
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253 | bo->kptr = (void*)MapIoMem(bo->cpu_addr, |
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254 | bo->tbo.vm_node->size << 12, PG_SW); |
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255 | } |
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256 | else |
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257 | { |
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258 | return -1; |
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259 | } |
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260 | |||
261 | |||
262 | *ptr = bo->kptr; |
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263 | } |
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264 | |||
265 | |||
266 | } |
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267 | |||
268 | |||
269 | { |
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270 | if (bo->kptr == NULL) |
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271 | return; |
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272 | |||
273 | |||
274 | { |
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275 | FreeKernelSpace(bo->kptr); |
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276 | } |
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277 | |||
278 | |||
279 | |||
280 | |||
281 | |||
282 | |||
283 | { |
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284 | struct ttm_buffer_object *tbo; |
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285 | |||
286 | |||
287 | return; |
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288 | |||
289 | |||
290 | } |
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291 | |||
292 | |||
293 | |||
294 | uint32_t *tiling_flags, |
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295 | uint32_t *pitch) |
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296 | { |
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297 | // BUG_ON(!atomic_read(&bo->tbo.reserved)); |
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298 | if (tiling_flags) |
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299 | *tiling_flags = bo->tiling_flags; |
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300 | if (pitch) |
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301 | *pitch = bo->pitch; |
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302 | } |
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303 | |||
304 | |||
305 | |||
306 | * Allocate a GEM object of the specified size with shmfs backing store |
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307 | */ |
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308 | struct drm_gem_object * |
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309 | drm_gem_object_alloc(struct drm_device *dev, size_t size) |
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310 | { |
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311 | struct drm_gem_object *obj; |
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312 | |||
313 | |||
314 | |||
315 | |||
316 | |||
317 | |||
318 | obj->size = size; |
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319 | return obj; |
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320 | } |
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321 | |||
322 | |||
323 | |||
324 | unsigned long size, bool kernel, u32 domain, |
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325 | struct radeon_bo **bo_ptr) |
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326 | { |
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327 | enum ttm_bo_type type; |
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328 | |||
329 | |||
330 | struct drm_mm *mman; |
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331 | struct drm_mm_node *vm_node; |
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332 | |||
333 | |||
334 | u32 bo_domain; |
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335 | int r; |
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336 | |||
337 | |||
338 | |||
339 | |||
340 | dbgprintf("Illegal buffer object size.\n"); |
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341 | return -EINVAL; |
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342 | } |
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343 | |||
344 | |||
345 | RADEON_GEM_DOMAIN_VRAM ) |
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346 | { |
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347 | return -EINVAL; |
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348 | }; |
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349 | |||
350 | |||
351 | type = ttm_bo_type_kernel; |
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352 | } else { |
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353 | type = ttm_bo_type_device; |
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354 | } |
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355 | *bo_ptr = NULL; |
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356 | bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL); |
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357 | if (bo == NULL) |
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358 | return -ENOMEM; |
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359 | |||
360 | |||
361 | bo->gobj = gobj; |
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362 | bo->surface_reg = -1; |
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363 | bo->tbo.num_pages = num_pages; |
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364 | bo->domain = domain; |
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365 | |||
366 | |||
367 | |||
368 | |||
369 | /* Kernel allocation are uninterruptible */ |
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370 | |||
371 | |||
372 | |||
373 | |||
374 | vm_node->size = 0xC00000 >> 12; |
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375 | vm_node->start = 0; |
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376 | vm_node->mm = NULL; |
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377 | |||
378 | |||
379 | bo->tbo.offset = bo->tbo.vm_node->start << PAGE_SHIFT; |
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380 | bo->tbo.offset += (u64)bo->rdev->mc.vram_start; |
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1430 | serge | 381 | bo->kptr = (void*)0xFE000000; |
1404 | serge | 382 | bo->pin_count = 1; |
383 | |||
384 | |||
385 | |||
386 | |||
387 | }><>><>><>><>><> |
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388 |