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5078 | serge | 1 | /* |
2 | * Copyright 2009 Jerome Glisse. |
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3 | * All Rights Reserved. |
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4 | * |
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5 | * Permission is hereby granted, free of charge, to any person obtaining a |
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6 | * copy of this software and associated documentation files (the |
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7 | * "Software"), to deal in the Software without restriction, including |
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8 | * without limitation the rights to use, copy, modify, merge, publish, |
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9 | * distribute, sub license, and/or sell copies of the Software, and to |
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10 | * permit persons to whom the Software is furnished to do so, subject to |
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11 | * the following conditions: |
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12 | * |
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13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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14 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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15 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL |
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16 | * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, |
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17 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR |
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18 | * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE |
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19 | * USE OR OTHER DEALINGS IN THE SOFTWARE. |
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20 | * |
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21 | * The above copyright notice and this permission notice (including the |
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22 | * next paragraph) shall be included in all copies or substantial portions |
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23 | * of the Software. |
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24 | * |
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25 | */ |
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26 | /* |
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27 | * Authors: |
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28 | * Jerome Glisse |
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29 | * Thomas Hellstrom |
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30 | * Dave Airlie |
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31 | */ |
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32 | #include |
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33 | #include |
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34 | #include |
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35 | #include |
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36 | #include "radeon.h" |
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37 | #include "radeon_trace.h" |
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38 | |||
39 | |||
40 | int radeon_ttm_init(struct radeon_device *rdev); |
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41 | void radeon_ttm_fini(struct radeon_device *rdev); |
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42 | static void radeon_bo_clear_surface_reg(struct radeon_bo *bo); |
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43 | |||
44 | /* |
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45 | * To exclude mutual BO access we rely on bo_reserve exclusion, as all |
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46 | * function are calling it. |
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47 | */ |
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48 | |||
49 | static void radeon_update_memory_usage(struct radeon_bo *bo, |
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50 | unsigned mem_type, int sign) |
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51 | { |
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52 | struct radeon_device *rdev = bo->rdev; |
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53 | u64 size = (u64)bo->tbo.num_pages << PAGE_SHIFT; |
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54 | |||
55 | switch (mem_type) { |
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56 | case TTM_PL_TT: |
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57 | if (sign > 0) |
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58 | __atomic_add_fetch(&rdev->gtt_usage.counter, size,__ATOMIC_RELAXED); |
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59 | else |
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60 | __atomic_sub_fetch(&rdev->gtt_usage.counter, size,__ATOMIC_RELAXED); |
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61 | break; |
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62 | case TTM_PL_VRAM: |
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63 | if (sign > 0) |
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64 | __atomic_add_fetch(&rdev->vram_usage.counter, size,__ATOMIC_RELAXED); |
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65 | else |
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66 | __atomic_sub_fetch(&rdev->vram_usage.counter, size,__ATOMIC_RELAXED ); |
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67 | break; |
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68 | } |
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69 | } |
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70 | |||
71 | static void radeon_ttm_bo_destroy(struct ttm_buffer_object *tbo) |
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72 | { |
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73 | struct radeon_bo *bo; |
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74 | |||
75 | bo = container_of(tbo, struct radeon_bo, tbo); |
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76 | |||
77 | radeon_update_memory_usage(bo, bo->tbo.mem.mem_type, -1); |
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78 | |||
79 | mutex_lock(&bo->rdev->gem.mutex); |
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80 | list_del_init(&bo->list); |
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81 | mutex_unlock(&bo->rdev->gem.mutex); |
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82 | radeon_bo_clear_surface_reg(bo); |
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83 | WARN_ON(!list_empty(&bo->va)); |
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84 | drm_gem_object_release(&bo->gem_base); |
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85 | kfree(bo); |
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86 | } |
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87 | |||
88 | bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo) |
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89 | { |
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90 | if (bo->destroy == &radeon_ttm_bo_destroy) |
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91 | return true; |
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92 | return false; |
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93 | } |
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94 | |||
95 | void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain) |
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96 | { |
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6104 | serge | 97 | u32 c = 0, i; |
5078 | serge | 98 | |
6104 | serge | 99 | rbo->placement.placement = rbo->placements; |
100 | rbo->placement.busy_placement = rbo->placements; |
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5271 | serge | 101 | if (domain & RADEON_GEM_DOMAIN_VRAM) { |
102 | /* Try placing BOs which don't need CPU access outside of the |
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103 | * CPU accessible part of VRAM |
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104 | */ |
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105 | if ((rbo->flags & RADEON_GEM_NO_CPU_ACCESS) && |
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106 | rbo->rdev->mc.visible_vram_size < rbo->rdev->mc.real_vram_size) { |
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107 | rbo->placements[c].fpfn = |
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108 | rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT; |
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109 | rbo->placements[c++].flags = TTM_PL_FLAG_WC | |
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110 | TTM_PL_FLAG_UNCACHED | |
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6104 | serge | 111 | TTM_PL_FLAG_VRAM; |
5271 | serge | 112 | } |
113 | |||
114 | rbo->placements[c].fpfn = 0; |
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115 | rbo->placements[c++].flags = TTM_PL_FLAG_WC | |
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116 | TTM_PL_FLAG_UNCACHED | |
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117 | TTM_PL_FLAG_VRAM; |
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118 | } |
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119 | |||
6104 | serge | 120 | if (domain & RADEON_GEM_DOMAIN_GTT) { |
5078 | serge | 121 | if (rbo->flags & RADEON_GEM_GTT_UC) { |
5271 | serge | 122 | rbo->placements[c].fpfn = 0; |
123 | rbo->placements[c++].flags = TTM_PL_FLAG_UNCACHED | |
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124 | TTM_PL_FLAG_TT; |
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125 | |||
5078 | serge | 126 | } else if ((rbo->flags & RADEON_GEM_GTT_WC) || |
127 | (rbo->rdev->flags & RADEON_IS_AGP)) { |
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5271 | serge | 128 | rbo->placements[c].fpfn = 0; |
129 | rbo->placements[c++].flags = TTM_PL_FLAG_WC | |
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130 | TTM_PL_FLAG_UNCACHED | |
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5078 | serge | 131 | TTM_PL_FLAG_TT; |
6104 | serge | 132 | } else { |
5271 | serge | 133 | rbo->placements[c].fpfn = 0; |
134 | rbo->placements[c++].flags = TTM_PL_FLAG_CACHED | |
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135 | TTM_PL_FLAG_TT; |
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6104 | serge | 136 | } |
137 | } |
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5271 | serge | 138 | |
6104 | serge | 139 | if (domain & RADEON_GEM_DOMAIN_CPU) { |
5078 | serge | 140 | if (rbo->flags & RADEON_GEM_GTT_UC) { |
5271 | serge | 141 | rbo->placements[c].fpfn = 0; |
142 | rbo->placements[c++].flags = TTM_PL_FLAG_UNCACHED | |
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143 | TTM_PL_FLAG_SYSTEM; |
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144 | |||
5078 | serge | 145 | } else if ((rbo->flags & RADEON_GEM_GTT_WC) || |
146 | rbo->rdev->flags & RADEON_IS_AGP) { |
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5271 | serge | 147 | rbo->placements[c].fpfn = 0; |
148 | rbo->placements[c++].flags = TTM_PL_FLAG_WC | |
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149 | TTM_PL_FLAG_UNCACHED | |
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5078 | serge | 150 | TTM_PL_FLAG_SYSTEM; |
6104 | serge | 151 | } else { |
5271 | serge | 152 | rbo->placements[c].fpfn = 0; |
153 | rbo->placements[c++].flags = TTM_PL_FLAG_CACHED | |
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154 | TTM_PL_FLAG_SYSTEM; |
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6104 | serge | 155 | } |
156 | } |
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5271 | serge | 157 | if (!c) { |
158 | rbo->placements[c].fpfn = 0; |
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159 | rbo->placements[c++].flags = TTM_PL_MASK_CACHING | |
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160 | TTM_PL_FLAG_SYSTEM; |
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161 | } |
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162 | |||
6104 | serge | 163 | rbo->placement.num_placement = c; |
164 | rbo->placement.num_busy_placement = c; |
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5078 | serge | 165 | |
5271 | serge | 166 | for (i = 0; i < c; ++i) { |
167 | if ((rbo->flags & RADEON_GEM_CPU_ACCESS) && |
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168 | (rbo->placements[i].flags & TTM_PL_FLAG_VRAM) && |
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169 | !rbo->placements[i].fpfn) |
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170 | rbo->placements[i].lpfn = |
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171 | rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT; |
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172 | else |
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173 | rbo->placements[i].lpfn = 0; |
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174 | } |
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5078 | serge | 175 | } |
176 | |||
177 | int radeon_bo_create(struct radeon_device *rdev, |
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5271 | serge | 178 | unsigned long size, int byte_align, bool kernel, |
179 | u32 domain, u32 flags, struct sg_table *sg, |
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180 | struct reservation_object *resv, |
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181 | struct radeon_bo **bo_ptr) |
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5078 | serge | 182 | { |
6104 | serge | 183 | struct radeon_bo *bo; |
5078 | serge | 184 | enum ttm_bo_type type; |
6104 | serge | 185 | unsigned long page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT; |
186 | size_t acc_size; |
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187 | int r; |
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5078 | serge | 188 | |
189 | size = ALIGN(size, PAGE_SIZE); |
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190 | |||
191 | if (kernel) { |
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192 | type = ttm_bo_type_kernel; |
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193 | } else if (sg) { |
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194 | type = ttm_bo_type_sg; |
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195 | } else { |
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196 | type = ttm_bo_type_device; |
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197 | } |
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198 | *bo_ptr = NULL; |
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199 | |||
200 | acc_size = ttm_bo_dma_acc_size(&rdev->mman.bdev, size, |
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201 | sizeof(struct radeon_bo)); |
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202 | |||
6104 | serge | 203 | bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL); |
204 | if (bo == NULL) |
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205 | return -ENOMEM; |
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206 | r = drm_gem_object_init(rdev->ddev, &bo->gem_base, size); |
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207 | if (unlikely(r)) { |
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208 | kfree(bo); |
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209 | return r; |
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210 | } |
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211 | bo->rdev = rdev; |
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212 | bo->surface_reg = -1; |
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213 | INIT_LIST_HEAD(&bo->list); |
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214 | INIT_LIST_HEAD(&bo->va); |
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215 | bo->initial_domain = domain & (RADEON_GEM_DOMAIN_VRAM | |
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216 | RADEON_GEM_DOMAIN_GTT | |
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217 | RADEON_GEM_DOMAIN_CPU); |
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5078 | serge | 218 | |
219 | bo->flags = flags; |
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220 | /* PCI GART is always snooped */ |
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221 | if (!(rdev->flags & RADEON_IS_PCIE)) |
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222 | bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC); |
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223 | |||
6104 | serge | 224 | /* Write-combined CPU mappings of GTT cause GPU hangs with RV6xx |
225 | * See https://bugs.freedesktop.org/show_bug.cgi?id=91268 |
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226 | */ |
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227 | if (rdev->family >= CHIP_RV610 && rdev->family <= CHIP_RV635) |
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228 | bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC); |
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229 | |||
5271 | serge | 230 | #ifdef CONFIG_X86_32 |
231 | /* XXX: Write-combined CPU mappings of GTT seem broken on 32-bit |
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232 | * See https://bugs.freedesktop.org/show_bug.cgi?id=84627 |
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233 | */ |
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6104 | serge | 234 | bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC); |
235 | #elif defined(CONFIG_X86) && !defined(CONFIG_X86_PAT) |
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236 | /* Don't try to enable write-combining when it can't work, or things |
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237 | * may be slow |
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238 | * See https://bugs.freedesktop.org/show_bug.cgi?id=88758 |
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239 | */ |
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240 | |||
241 | #warning Please enable CONFIG_MTRR and CONFIG_X86_PAT for better performance \ |
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242 | thanks to write-combining |
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243 | |||
244 | if (bo->flags & RADEON_GEM_GTT_WC) |
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245 | DRM_INFO_ONCE("Please enable CONFIG_MTRR and CONFIG_X86_PAT for " |
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246 | "better performance thanks to write-combining\n"); |
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247 | bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC); |
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5271 | serge | 248 | #endif |
5078 | serge | 249 | |
6104 | serge | 250 | radeon_ttm_placement_from_domain(bo, domain); |
5078 | serge | 251 | /* Kernel allocation are uninterruptible */ |
5346 | serge | 252 | down_read(&rdev->pm.mclk_lock); |
5078 | serge | 253 | r = ttm_bo_init(&rdev->mman.bdev, &bo->tbo, size, type, |
254 | &bo->placement, page_align, !kernel, NULL, |
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5271 | serge | 255 | acc_size, sg, resv, &radeon_ttm_bo_destroy); |
5346 | serge | 256 | up_read(&rdev->pm.mclk_lock); |
5078 | serge | 257 | if (unlikely(r != 0)) { |
258 | return r; |
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259 | } |
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260 | *bo_ptr = bo; |
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261 | |||
262 | trace_radeon_bo_create(bo); |
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263 | |||
264 | return 0; |
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265 | } |
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266 | |||
267 | int radeon_bo_kmap(struct radeon_bo *bo, void **ptr) |
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268 | { |
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269 | bool is_iomem; |
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270 | int r; |
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271 | |||
272 | if (bo->kptr) { |
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273 | if (ptr) { |
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274 | *ptr = bo->kptr; |
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275 | } |
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276 | return 0; |
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277 | } |
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278 | r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap); |
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279 | if (r) { |
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280 | return r; |
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281 | } |
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282 | bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem); |
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283 | if (ptr) { |
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284 | *ptr = bo->kptr; |
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285 | } |
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286 | radeon_bo_check_tiling(bo, 0, 0); |
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287 | return 0; |
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288 | } |
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289 | |||
290 | void radeon_bo_kunmap(struct radeon_bo *bo) |
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291 | { |
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292 | if (bo->kptr == NULL) |
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293 | return; |
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294 | bo->kptr = NULL; |
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295 | radeon_bo_check_tiling(bo, 0, 0); |
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296 | ttm_bo_kunmap(&bo->kmap); |
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297 | } |
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298 | |||
299 | struct radeon_bo *radeon_bo_ref(struct radeon_bo *bo) |
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300 | { |
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301 | if (bo == NULL) |
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302 | return NULL; |
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303 | |||
304 | ttm_bo_reference(&bo->tbo); |
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305 | return bo; |
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306 | } |
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307 | |||
308 | void radeon_bo_unref(struct radeon_bo **bo) |
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309 | { |
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310 | struct ttm_buffer_object *tbo; |
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311 | struct radeon_device *rdev; |
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312 | |||
313 | if ((*bo) == NULL) |
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314 | return; |
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315 | rdev = (*bo)->rdev; |
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316 | tbo = &((*bo)->tbo); |
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317 | ttm_bo_unref(&tbo); |
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318 | if (tbo == NULL) |
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319 | *bo = NULL; |
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320 | } |
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321 | |||
322 | int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain, u64 max_offset, |
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6104 | serge | 323 | u64 *gpu_addr) |
5078 | serge | 324 | { |
6104 | serge | 325 | int r, i; |
5078 | serge | 326 | |
6104 | serge | 327 | if (bo->pin_count) { |
328 | bo->pin_count++; |
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329 | if (gpu_addr) |
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330 | *gpu_addr = radeon_bo_gpu_offset(bo); |
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5078 | serge | 331 | |
6104 | serge | 332 | if (max_offset != 0) { |
333 | u64 domain_start; |
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5078 | serge | 334 | |
6104 | serge | 335 | if (domain == RADEON_GEM_DOMAIN_VRAM) |
336 | domain_start = bo->rdev->mc.vram_start; |
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337 | else |
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338 | domain_start = bo->rdev->mc.gtt_start; |
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339 | WARN_ON_ONCE(max_offset < |
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340 | (radeon_bo_gpu_offset(bo) - domain_start)); |
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341 | } |
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5078 | serge | 342 | |
6104 | serge | 343 | return 0; |
344 | } |
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345 | radeon_ttm_placement_from_domain(bo, domain); |
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5271 | serge | 346 | for (i = 0; i < bo->placement.num_placement; i++) { |
6104 | serge | 347 | /* force to pin into visible video ram */ |
5271 | serge | 348 | if ((bo->placements[i].flags & TTM_PL_FLAG_VRAM) && |
349 | !(bo->flags & RADEON_GEM_NO_CPU_ACCESS) && |
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350 | (!max_offset || max_offset > bo->rdev->mc.visible_vram_size)) |
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351 | bo->placements[i].lpfn = |
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352 | bo->rdev->mc.visible_vram_size >> PAGE_SHIFT; |
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353 | else |
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354 | bo->placements[i].lpfn = max_offset >> PAGE_SHIFT; |
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355 | |||
356 | bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT; |
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6104 | serge | 357 | } |
5078 | serge | 358 | |
359 | r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false); |
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6104 | serge | 360 | if (likely(r == 0)) { |
361 | bo->pin_count = 1; |
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362 | if (gpu_addr != NULL) |
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363 | *gpu_addr = radeon_bo_gpu_offset(bo); |
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5078 | serge | 364 | if (domain == RADEON_GEM_DOMAIN_VRAM) |
365 | bo->rdev->vram_pin_size += radeon_bo_size(bo); |
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366 | else |
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367 | bo->rdev->gart_pin_size += radeon_bo_size(bo); |
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368 | } else { |
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369 | dev_err(bo->rdev->dev, "%p pin failed\n", bo); |
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6104 | serge | 370 | } |
371 | return r; |
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5078 | serge | 372 | } |
373 | |||
374 | int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr) |
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375 | { |
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6104 | serge | 376 | return radeon_bo_pin_restricted(bo, domain, 0, gpu_addr); |
5078 | serge | 377 | } |
378 | |||
379 | int radeon_bo_unpin(struct radeon_bo *bo) |
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380 | { |
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6104 | serge | 381 | int r, i; |
5078 | serge | 382 | |
6104 | serge | 383 | if (!bo->pin_count) { |
384 | dev_warn(bo->rdev->dev, "%p unpin not necessary\n", bo); |
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385 | return 0; |
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386 | } |
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387 | bo->pin_count--; |
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388 | if (bo->pin_count) |
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389 | return 0; |
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5271 | serge | 390 | for (i = 0; i < bo->placement.num_placement; i++) { |
391 | bo->placements[i].lpfn = 0; |
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392 | bo->placements[i].flags &= ~TTM_PL_FLAG_NO_EVICT; |
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393 | } |
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5078 | serge | 394 | r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false); |
395 | if (likely(r == 0)) { |
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396 | if (bo->tbo.mem.mem_type == TTM_PL_VRAM) |
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397 | bo->rdev->vram_pin_size -= radeon_bo_size(bo); |
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398 | else |
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399 | bo->rdev->gart_pin_size -= radeon_bo_size(bo); |
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400 | } else { |
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401 | dev_err(bo->rdev->dev, "%p validate failed for unpin\n", bo); |
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402 | } |
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403 | return r; |
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404 | } |
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405 | |||
406 | int radeon_bo_init(struct radeon_device *rdev) |
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407 | { |
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408 | /* Add an MTRR for the VRAM */ |
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409 | DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n", |
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410 | rdev->mc.mc_vram_size >> 20, |
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411 | (unsigned long long)rdev->mc.aper_size >> 20); |
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412 | DRM_INFO("RAM width %dbits %cDR\n", |
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413 | rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S'); |
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414 | return radeon_ttm_init(rdev); |
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415 | } |
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416 | |||
417 | void radeon_bo_fini(struct radeon_device *rdev) |
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418 | { |
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419 | // radeon_ttm_fini(rdev); |
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420 | // arch_phys_wc_del(rdev->mc.vram_mtrr); |
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421 | } |
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422 | |||
423 | /* Returns how many bytes TTM can move per IB. |
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424 | */ |
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425 | static u64 radeon_bo_get_threshold_for_moves(struct radeon_device *rdev) |
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426 | { |
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427 | u64 real_vram_size = rdev->mc.real_vram_size; |
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428 | u64 vram_usage = atomic64_read(&rdev->vram_usage); |
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429 | |||
430 | /* This function is based on the current VRAM usage. |
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431 | * |
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432 | * - If all of VRAM is free, allow relocating the number of bytes that |
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433 | * is equal to 1/4 of the size of VRAM for this IB. |
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434 | |||
435 | * - If more than one half of VRAM is occupied, only allow relocating |
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436 | * 1 MB of data for this IB. |
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437 | * |
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438 | * - From 0 to one half of used VRAM, the threshold decreases |
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439 | * linearly. |
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440 | * __________________ |
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441 | * 1/4 of -|\ | |
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442 | * VRAM | \ | |
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443 | * | \ | |
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444 | * | \ | |
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445 | * | \ | |
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446 | * | \ | |
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447 | * | \ | |
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448 | * | \________|1 MB |
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449 | * |----------------| |
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450 | * VRAM 0 % 100 % |
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451 | * used used |
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452 | * |
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453 | * Note: It's a threshold, not a limit. The threshold must be crossed |
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454 | * for buffer relocations to stop, so any buffer of an arbitrary size |
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455 | * can be moved as long as the threshold isn't crossed before |
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456 | * the relocation takes place. We don't want to disable buffer |
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457 | * relocations completely. |
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458 | * |
||
459 | * The idea is that buffers should be placed in VRAM at creation time |
||
460 | * and TTM should only do a minimum number of relocations during |
||
461 | * command submission. In practice, you need to submit at least |
||
462 | * a dozen IBs to move all buffers to VRAM if they are in GTT. |
||
463 | * |
||
464 | * Also, things can get pretty crazy under memory pressure and actual |
||
465 | * VRAM usage can change a lot, so playing safe even at 50% does |
||
466 | * consistently increase performance. |
||
467 | */ |
||
468 | |||
469 | u64 half_vram = real_vram_size >> 1; |
||
470 | u64 half_free_vram = vram_usage >= half_vram ? 0 : half_vram - vram_usage; |
||
471 | u64 bytes_moved_threshold = half_free_vram >> 1; |
||
472 | return max(bytes_moved_threshold, 1024*1024ull); |
||
473 | } |
||
474 | |||
475 | int radeon_bo_list_validate(struct radeon_device *rdev, |
||
476 | struct ww_acquire_ctx *ticket, |
||
477 | struct list_head *head, int ring) |
||
478 | { |
||
5271 | serge | 479 | struct radeon_bo_list *lobj; |
480 | struct list_head duplicates; |
||
5078 | serge | 481 | int r; |
482 | u64 bytes_moved = 0, initial_bytes_moved; |
||
483 | u64 bytes_moved_threshold = radeon_bo_get_threshold_for_moves(rdev); |
||
484 | |||
5271 | serge | 485 | INIT_LIST_HEAD(&duplicates); |
486 | r = ttm_eu_reserve_buffers(ticket, head, true, &duplicates); |
||
5078 | serge | 487 | if (unlikely(r != 0)) { |
488 | return r; |
||
489 | } |
||
490 | |||
491 | list_for_each_entry(lobj, head, tv.head) { |
||
5271 | serge | 492 | struct radeon_bo *bo = lobj->robj; |
5078 | serge | 493 | if (!bo->pin_count) { |
494 | u32 domain = lobj->prefered_domains; |
||
5271 | serge | 495 | u32 allowed = lobj->allowed_domains; |
5078 | serge | 496 | u32 current_domain = |
497 | radeon_mem_type_to_domain(bo->tbo.mem.mem_type); |
||
498 | |||
499 | /* Check if this buffer will be moved and don't move it |
||
500 | * if we have moved too many buffers for this IB already. |
||
501 | * |
||
502 | * Note that this allows moving at least one buffer of |
||
503 | * any size, because it doesn't take the current "bo" |
||
504 | * into account. We don't want to disallow buffer moves |
||
505 | * completely. |
||
506 | */ |
||
5271 | serge | 507 | if ((allowed & current_domain) != 0 && |
5078 | serge | 508 | (domain & current_domain) == 0 && /* will be moved */ |
509 | bytes_moved > bytes_moved_threshold) { |
||
510 | /* don't move it */ |
||
511 | domain = current_domain; |
||
512 | } |
||
513 | |||
514 | retry: |
||
515 | radeon_ttm_placement_from_domain(bo, domain); |
||
516 | if (ring == R600_RING_TYPE_UVD_INDEX) |
||
5271 | serge | 517 | radeon_uvd_force_into_uvd_segment(bo, allowed); |
5078 | serge | 518 | |
519 | initial_bytes_moved = atomic64_read(&rdev->num_bytes_moved); |
||
520 | r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false); |
||
521 | bytes_moved += atomic64_read(&rdev->num_bytes_moved) - |
||
522 | initial_bytes_moved; |
||
523 | |||
524 | if (unlikely(r)) { |
||
525 | if (r != -ERESTARTSYS && |
||
526 | domain != lobj->allowed_domains) { |
||
527 | domain = lobj->allowed_domains; |
||
528 | goto retry; |
||
529 | } |
||
530 | ttm_eu_backoff_reservation(ticket, head); |
||
531 | return r; |
||
532 | } |
||
533 | } |
||
534 | lobj->gpu_offset = radeon_bo_gpu_offset(bo); |
||
535 | lobj->tiling_flags = bo->tiling_flags; |
||
536 | } |
||
5271 | serge | 537 | |
538 | list_for_each_entry(lobj, &duplicates, tv.head) { |
||
539 | lobj->gpu_offset = radeon_bo_gpu_offset(lobj->robj); |
||
540 | lobj->tiling_flags = lobj->robj->tiling_flags; |
||
541 | } |
||
542 | |||
5078 | serge | 543 | return 0; |
544 | } |
||
545 | |||
546 | int radeon_bo_get_surface_reg(struct radeon_bo *bo) |
||
547 | { |
||
548 | struct radeon_device *rdev = bo->rdev; |
||
549 | struct radeon_surface_reg *reg; |
||
550 | struct radeon_bo *old_object; |
||
551 | int steal; |
||
552 | int i; |
||
553 | |||
554 | lockdep_assert_held(&bo->tbo.resv->lock.base); |
||
555 | |||
556 | if (!bo->tiling_flags) |
||
557 | return 0; |
||
558 | |||
559 | if (bo->surface_reg >= 0) { |
||
560 | reg = &rdev->surface_regs[bo->surface_reg]; |
||
561 | i = bo->surface_reg; |
||
562 | goto out; |
||
563 | } |
||
564 | |||
565 | steal = -1; |
||
566 | for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) { |
||
567 | |||
568 | reg = &rdev->surface_regs[i]; |
||
569 | if (!reg->bo) |
||
570 | break; |
||
571 | |||
572 | old_object = reg->bo; |
||
573 | if (old_object->pin_count == 0) |
||
574 | steal = i; |
||
575 | } |
||
576 | |||
577 | /* if we are all out */ |
||
578 | if (i == RADEON_GEM_MAX_SURFACES) { |
||
579 | if (steal == -1) |
||
580 | return -ENOMEM; |
||
581 | /* find someone with a surface reg and nuke their BO */ |
||
582 | reg = &rdev->surface_regs[steal]; |
||
583 | old_object = reg->bo; |
||
584 | /* blow away the mapping */ |
||
585 | DRM_DEBUG("stealing surface reg %d from %p\n", steal, old_object); |
||
586 | ttm_bo_unmap_virtual(&old_object->tbo); |
||
587 | old_object->surface_reg = -1; |
||
588 | i = steal; |
||
589 | } |
||
590 | |||
591 | bo->surface_reg = i; |
||
592 | reg->bo = bo; |
||
593 | |||
594 | out: |
||
595 | radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch, |
||
596 | bo->tbo.mem.start << PAGE_SHIFT, |
||
597 | bo->tbo.num_pages << PAGE_SHIFT); |
||
598 | return 0; |
||
599 | } |
||
600 | |||
601 | static void radeon_bo_clear_surface_reg(struct radeon_bo *bo) |
||
602 | { |
||
603 | struct radeon_device *rdev = bo->rdev; |
||
604 | struct radeon_surface_reg *reg; |
||
605 | |||
606 | if (bo->surface_reg == -1) |
||
607 | return; |
||
608 | |||
609 | reg = &rdev->surface_regs[bo->surface_reg]; |
||
610 | radeon_clear_surface_reg(rdev, bo->surface_reg); |
||
611 | |||
612 | reg->bo = NULL; |
||
613 | bo->surface_reg = -1; |
||
614 | } |
||
615 | |||
616 | int radeon_bo_set_tiling_flags(struct radeon_bo *bo, |
||
617 | uint32_t tiling_flags, uint32_t pitch) |
||
618 | { |
||
619 | struct radeon_device *rdev = bo->rdev; |
||
620 | int r; |
||
621 | |||
622 | if (rdev->family >= CHIP_CEDAR) { |
||
623 | unsigned bankw, bankh, mtaspect, tilesplit, stilesplit; |
||
624 | |||
625 | bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK; |
||
626 | bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK; |
||
627 | mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK; |
||
628 | tilesplit = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK; |
||
629 | stilesplit = (tiling_flags >> RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK; |
||
630 | switch (bankw) { |
||
631 | case 0: |
||
632 | case 1: |
||
633 | case 2: |
||
634 | case 4: |
||
635 | case 8: |
||
636 | break; |
||
637 | default: |
||
638 | return -EINVAL; |
||
639 | } |
||
640 | switch (bankh) { |
||
641 | case 0: |
||
642 | case 1: |
||
643 | case 2: |
||
644 | case 4: |
||
645 | case 8: |
||
646 | break; |
||
647 | default: |
||
648 | return -EINVAL; |
||
649 | } |
||
650 | switch (mtaspect) { |
||
651 | case 0: |
||
652 | case 1: |
||
653 | case 2: |
||
654 | case 4: |
||
655 | case 8: |
||
656 | break; |
||
657 | default: |
||
658 | return -EINVAL; |
||
659 | } |
||
660 | if (tilesplit > 6) { |
||
661 | return -EINVAL; |
||
662 | } |
||
663 | if (stilesplit > 6) { |
||
664 | return -EINVAL; |
||
665 | } |
||
666 | } |
||
667 | r = radeon_bo_reserve(bo, false); |
||
668 | if (unlikely(r != 0)) |
||
669 | return r; |
||
670 | bo->tiling_flags = tiling_flags; |
||
671 | bo->pitch = pitch; |
||
672 | radeon_bo_unreserve(bo); |
||
673 | return 0; |
||
674 | } |
||
675 | |||
676 | void radeon_bo_get_tiling_flags(struct radeon_bo *bo, |
||
677 | uint32_t *tiling_flags, |
||
678 | uint32_t *pitch) |
||
679 | { |
||
680 | lockdep_assert_held(&bo->tbo.resv->lock.base); |
||
681 | |||
682 | if (tiling_flags) |
||
683 | *tiling_flags = bo->tiling_flags; |
||
684 | if (pitch) |
||
685 | *pitch = bo->pitch; |
||
686 | } |
||
687 | |||
688 | int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved, |
||
689 | bool force_drop) |
||
690 | { |
||
691 | if (!force_drop) |
||
692 | lockdep_assert_held(&bo->tbo.resv->lock.base); |
||
693 | |||
694 | if (!(bo->tiling_flags & RADEON_TILING_SURFACE)) |
||
695 | return 0; |
||
696 | |||
697 | if (force_drop) { |
||
698 | radeon_bo_clear_surface_reg(bo); |
||
699 | return 0; |
||
700 | } |
||
701 | |||
702 | if (bo->tbo.mem.mem_type != TTM_PL_VRAM) { |
||
703 | if (!has_moved) |
||
704 | return 0; |
||
705 | |||
706 | if (bo->surface_reg >= 0) |
||
707 | radeon_bo_clear_surface_reg(bo); |
||
708 | return 0; |
||
709 | } |
||
710 | |||
711 | if ((bo->surface_reg >= 0) && !has_moved) |
||
712 | return 0; |
||
713 | |||
714 | return radeon_bo_get_surface_reg(bo); |
||
715 | } |
||
716 | |||
717 | void radeon_bo_move_notify(struct ttm_buffer_object *bo, |
||
718 | struct ttm_mem_reg *new_mem) |
||
719 | { |
||
720 | struct radeon_bo *rbo; |
||
721 | |||
722 | if (!radeon_ttm_bo_is_radeon_bo(bo)) |
||
723 | return; |
||
724 | |||
725 | rbo = container_of(bo, struct radeon_bo, tbo); |
||
726 | radeon_bo_check_tiling(rbo, 0, 1); |
||
727 | radeon_vm_bo_invalidate(rbo->rdev, rbo); |
||
728 | |||
729 | /* update statistics */ |
||
730 | if (!new_mem) |
||
731 | return; |
||
732 | |||
733 | radeon_update_memory_usage(rbo, bo->mem.mem_type, -1); |
||
734 | radeon_update_memory_usage(rbo, new_mem->mem_type, 1); |
||
735 | } |
||
736 | int radeon_bo_wait(struct radeon_bo *bo, u32 *mem_type, bool no_wait) |
||
737 | { |
||
738 | int r; |
||
739 | |||
740 | r = ttm_bo_reserve(&bo->tbo, true, no_wait, false, NULL); |
||
741 | if (unlikely(r != 0)) |
||
742 | return r; |
||
743 | if (mem_type) |
||
744 | *mem_type = bo->tbo.mem.mem_type; |
||
5271 | serge | 745 | |
6104 | serge | 746 | r = ttm_bo_wait(&bo->tbo, true, true, no_wait); |
5078 | serge | 747 | ttm_bo_unreserve(&bo->tbo); |
748 | return r; |
||
749 | } |
||
5271 | serge | 750 | |
751 | /** |
||
752 | * radeon_bo_fence - add fence to buffer object |
||
753 | * |
||
754 | * @bo: buffer object in question |
||
755 | * @fence: fence to add |
||
756 | * @shared: true if fence should be added shared |
||
757 | * |
||
758 | */ |
||
759 | void radeon_bo_fence(struct radeon_bo *bo, struct radeon_fence *fence, |
||
760 | bool shared) |
||
761 | { |
||
762 | struct reservation_object *resv = bo->tbo.resv; |
||
763 | |||
764 | if (shared) |
||
765 | reservation_object_add_shared_fence(resv, &fence->base); |
||
766 | else |
||
767 | reservation_object_add_excl_fence(resv, &fence->base); |
||
768 | }><>><>>>> |