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| Rev | Author | Line No. | Line |
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| 5078 | serge | 1 | /* |
| 2 | * Copyright 2009 Jerome Glisse. |
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| 3 | * All Rights Reserved. |
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| 4 | * |
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| 5 | * Permission is hereby granted, free of charge, to any person obtaining a |
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| 6 | * copy of this software and associated documentation files (the |
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| 7 | * "Software"), to deal in the Software without restriction, including |
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| 8 | * without limitation the rights to use, copy, modify, merge, publish, |
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| 9 | * distribute, sub license, and/or sell copies of the Software, and to |
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| 10 | * permit persons to whom the Software is furnished to do so, subject to |
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| 11 | * the following conditions: |
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| 12 | * |
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| 13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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| 14 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| 15 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL |
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| 16 | * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, |
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| 17 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR |
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| 18 | * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE |
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| 19 | * USE OR OTHER DEALINGS IN THE SOFTWARE. |
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| 20 | * |
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| 21 | * The above copyright notice and this permission notice (including the |
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| 22 | * next paragraph) shall be included in all copies or substantial portions |
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| 23 | * of the Software. |
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| 24 | * |
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| 25 | */ |
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| 26 | /* |
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| 27 | * Authors: |
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| 28 | * Jerome Glisse |
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| 29 | * Thomas Hellstrom |
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| 30 | * Dave Airlie |
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| 31 | */ |
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| 32 | #include |
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| 33 | #include |
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| 34 | #include |
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| 35 | #include |
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| 36 | #include "radeon.h" |
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| 37 | #include "radeon_trace.h" |
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| 38 | |||
| 39 | |||
| 40 | int radeon_ttm_init(struct radeon_device *rdev); |
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| 41 | void radeon_ttm_fini(struct radeon_device *rdev); |
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| 42 | static void radeon_bo_clear_surface_reg(struct radeon_bo *bo); |
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| 43 | |||
| 44 | /* |
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| 45 | * To exclude mutual BO access we rely on bo_reserve exclusion, as all |
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| 46 | * function are calling it. |
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| 47 | */ |
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| 48 | |||
| 49 | static void radeon_update_memory_usage(struct radeon_bo *bo, |
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| 50 | unsigned mem_type, int sign) |
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| 51 | { |
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| 52 | struct radeon_device *rdev = bo->rdev; |
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| 53 | u64 size = (u64)bo->tbo.num_pages << PAGE_SHIFT; |
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| 54 | |||
| 55 | switch (mem_type) { |
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| 56 | case TTM_PL_TT: |
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| 57 | if (sign > 0) |
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| 58 | __atomic_add_fetch(&rdev->gtt_usage.counter, size,__ATOMIC_RELAXED); |
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| 59 | else |
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| 60 | __atomic_sub_fetch(&rdev->gtt_usage.counter, size,__ATOMIC_RELAXED); |
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| 61 | break; |
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| 62 | case TTM_PL_VRAM: |
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| 63 | if (sign > 0) |
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| 64 | __atomic_add_fetch(&rdev->vram_usage.counter, size,__ATOMIC_RELAXED); |
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| 65 | else |
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| 66 | __atomic_sub_fetch(&rdev->vram_usage.counter, size,__ATOMIC_RELAXED ); |
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| 67 | break; |
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| 68 | } |
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| 69 | } |
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| 70 | |||
| 71 | static void radeon_ttm_bo_destroy(struct ttm_buffer_object *tbo) |
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| 72 | { |
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| 73 | struct radeon_bo *bo; |
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| 74 | |||
| 75 | bo = container_of(tbo, struct radeon_bo, tbo); |
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| 76 | |||
| 77 | radeon_update_memory_usage(bo, bo->tbo.mem.mem_type, -1); |
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| 78 | |||
| 79 | mutex_lock(&bo->rdev->gem.mutex); |
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| 80 | list_del_init(&bo->list); |
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| 81 | mutex_unlock(&bo->rdev->gem.mutex); |
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| 82 | radeon_bo_clear_surface_reg(bo); |
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| 83 | WARN_ON(!list_empty(&bo->va)); |
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| 84 | drm_gem_object_release(&bo->gem_base); |
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| 85 | kfree(bo); |
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| 86 | } |
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| 87 | |||
| 88 | bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo) |
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| 89 | { |
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| 90 | if (bo->destroy == &radeon_ttm_bo_destroy) |
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| 91 | return true; |
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| 92 | return false; |
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| 93 | } |
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| 94 | |||
| 95 | void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain) |
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| 96 | { |
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| 97 | u32 c = 0, i; |
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| 98 | |||
| 99 | rbo->placement.fpfn = 0; |
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| 100 | rbo->placement.lpfn = 0; |
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| 101 | rbo->placement.placement = rbo->placements; |
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| 102 | rbo->placement.busy_placement = rbo->placements; |
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| 103 | if (domain & RADEON_GEM_DOMAIN_VRAM) |
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| 104 | rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED | |
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| 105 | TTM_PL_FLAG_VRAM; |
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| 106 | if (domain & RADEON_GEM_DOMAIN_GTT) { |
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| 107 | if (rbo->flags & RADEON_GEM_GTT_UC) { |
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| 108 | rbo->placements[c++] = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_TT; |
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| 109 | } else if ((rbo->flags & RADEON_GEM_GTT_WC) || |
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| 110 | (rbo->rdev->flags & RADEON_IS_AGP)) { |
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| 111 | rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED | |
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| 112 | TTM_PL_FLAG_TT; |
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| 113 | } else { |
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| 114 | rbo->placements[c++] = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_TT; |
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| 115 | } |
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| 116 | } |
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| 117 | if (domain & RADEON_GEM_DOMAIN_CPU) { |
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| 118 | if (rbo->flags & RADEON_GEM_GTT_UC) { |
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| 119 | rbo->placements[c++] = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_SYSTEM; |
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| 120 | } else if ((rbo->flags & RADEON_GEM_GTT_WC) || |
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| 121 | rbo->rdev->flags & RADEON_IS_AGP) { |
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| 122 | rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED | |
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| 123 | TTM_PL_FLAG_SYSTEM; |
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| 124 | } else { |
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| 125 | rbo->placements[c++] = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_SYSTEM; |
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| 126 | } |
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| 127 | } |
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| 128 | if (!c) |
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| 129 | rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM; |
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| 130 | rbo->placement.num_placement = c; |
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| 131 | rbo->placement.num_busy_placement = c; |
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| 132 | |||
| 133 | /* |
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| 134 | * Use two-ended allocation depending on the buffer size to |
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| 135 | * improve fragmentation quality. |
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| 136 | * 512kb was measured as the most optimal number. |
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| 137 | */ |
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| 138 | if (rbo->tbo.mem.size > 512 * 1024) { |
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| 139 | for (i = 0; i < c; i++) { |
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| 140 | rbo->placements[i] |= TTM_PL_FLAG_TOPDOWN; |
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| 141 | } |
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| 142 | } |
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| 143 | } |
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| 144 | |||
| 145 | int radeon_bo_create(struct radeon_device *rdev, |
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| 146 | unsigned long size, int byte_align, bool kernel, u32 domain, |
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| 147 | u32 flags, struct sg_table *sg, struct radeon_bo **bo_ptr) |
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| 148 | { |
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| 149 | struct radeon_bo *bo; |
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| 150 | enum ttm_bo_type type; |
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| 151 | unsigned long page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT; |
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| 152 | size_t acc_size; |
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| 153 | int r; |
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| 154 | |||
| 155 | size = ALIGN(size, PAGE_SIZE); |
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| 156 | |||
| 157 | if (kernel) { |
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| 158 | type = ttm_bo_type_kernel; |
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| 159 | } else if (sg) { |
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| 160 | type = ttm_bo_type_sg; |
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| 161 | } else { |
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| 162 | type = ttm_bo_type_device; |
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| 163 | } |
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| 164 | *bo_ptr = NULL; |
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| 165 | |||
| 166 | acc_size = ttm_bo_dma_acc_size(&rdev->mman.bdev, size, |
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| 167 | sizeof(struct radeon_bo)); |
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| 168 | |||
| 169 | bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL); |
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| 170 | if (bo == NULL) |
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| 171 | return -ENOMEM; |
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| 172 | r = drm_gem_object_init(rdev->ddev, &bo->gem_base, size); |
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| 173 | if (unlikely(r)) { |
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| 174 | kfree(bo); |
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| 175 | return r; |
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| 176 | } |
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| 177 | bo->rdev = rdev; |
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| 178 | bo->surface_reg = -1; |
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| 179 | INIT_LIST_HEAD(&bo->list); |
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| 180 | INIT_LIST_HEAD(&bo->va); |
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| 181 | bo->initial_domain = domain & (RADEON_GEM_DOMAIN_VRAM | |
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| 182 | RADEON_GEM_DOMAIN_GTT | |
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| 183 | RADEON_GEM_DOMAIN_CPU); |
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| 184 | |||
| 185 | bo->flags = flags; |
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| 186 | /* PCI GART is always snooped */ |
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| 187 | if (!(rdev->flags & RADEON_IS_PCIE)) |
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| 188 | bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC); |
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| 189 | |||
| 190 | // printf("%s rdev->flags %x bo->flags %x\n", |
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| 191 | // __FUNCTION__, bo->flags); |
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| 192 | |||
| 193 | if(flags & RADEON_GEM_GTT_WC) |
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| 194 | bo->flags&= ~RADEON_GEM_GTT_WC; |
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| 195 | |||
| 196 | radeon_ttm_placement_from_domain(bo, domain); |
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| 197 | /* Kernel allocation are uninterruptible */ |
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| 198 | // down_read(&rdev->pm.mclk_lock); |
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| 199 | r = ttm_bo_init(&rdev->mman.bdev, &bo->tbo, size, type, |
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| 200 | &bo->placement, page_align, !kernel, NULL, |
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| 201 | acc_size, sg, &radeon_ttm_bo_destroy); |
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| 202 | // up_read(&rdev->pm.mclk_lock); |
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| 203 | if (unlikely(r != 0)) { |
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| 204 | return r; |
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| 205 | } |
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| 206 | *bo_ptr = bo; |
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| 207 | |||
| 208 | trace_radeon_bo_create(bo); |
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| 209 | |||
| 210 | return 0; |
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| 211 | } |
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| 212 | |||
| 213 | int radeon_bo_kmap(struct radeon_bo *bo, void **ptr) |
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| 214 | { |
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| 215 | bool is_iomem; |
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| 216 | int r; |
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| 217 | |||
| 218 | if (bo->kptr) { |
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| 219 | if (ptr) { |
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| 220 | *ptr = bo->kptr; |
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| 221 | } |
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| 222 | return 0; |
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| 223 | } |
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| 224 | r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap); |
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| 225 | if (r) { |
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| 226 | return r; |
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| 227 | } |
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| 228 | bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem); |
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| 229 | if (ptr) { |
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| 230 | *ptr = bo->kptr; |
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| 231 | } |
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| 232 | radeon_bo_check_tiling(bo, 0, 0); |
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| 233 | return 0; |
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| 234 | } |
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| 235 | |||
| 236 | void radeon_bo_kunmap(struct radeon_bo *bo) |
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| 237 | { |
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| 238 | if (bo->kptr == NULL) |
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| 239 | return; |
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| 240 | bo->kptr = NULL; |
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| 241 | radeon_bo_check_tiling(bo, 0, 0); |
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| 242 | ttm_bo_kunmap(&bo->kmap); |
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| 243 | } |
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| 244 | |||
| 245 | struct radeon_bo *radeon_bo_ref(struct radeon_bo *bo) |
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| 246 | { |
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| 247 | if (bo == NULL) |
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| 248 | return NULL; |
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| 249 | |||
| 250 | ttm_bo_reference(&bo->tbo); |
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| 251 | return bo; |
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| 252 | } |
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| 253 | |||
| 254 | void radeon_bo_unref(struct radeon_bo **bo) |
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| 255 | { |
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| 256 | struct ttm_buffer_object *tbo; |
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| 257 | struct radeon_device *rdev; |
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| 258 | |||
| 259 | if ((*bo) == NULL) |
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| 260 | return; |
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| 261 | rdev = (*bo)->rdev; |
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| 262 | tbo = &((*bo)->tbo); |
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| 263 | ttm_bo_unref(&tbo); |
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| 264 | if (tbo == NULL) |
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| 265 | *bo = NULL; |
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| 266 | } |
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| 267 | |||
| 268 | int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain, u64 max_offset, |
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| 269 | u64 *gpu_addr) |
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| 270 | { |
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| 271 | int r, i; |
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| 272 | |||
| 273 | if (bo->pin_count) { |
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| 274 | bo->pin_count++; |
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| 275 | if (gpu_addr) |
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| 276 | *gpu_addr = radeon_bo_gpu_offset(bo); |
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| 277 | |||
| 278 | if (max_offset != 0) { |
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| 279 | u64 domain_start; |
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| 280 | |||
| 281 | if (domain == RADEON_GEM_DOMAIN_VRAM) |
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| 282 | domain_start = bo->rdev->mc.vram_start; |
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| 283 | else |
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| 284 | domain_start = bo->rdev->mc.gtt_start; |
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| 285 | WARN_ON_ONCE(max_offset < |
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| 286 | (radeon_bo_gpu_offset(bo) - domain_start)); |
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| 287 | } |
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| 288 | |||
| 289 | return 0; |
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| 290 | } |
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| 291 | radeon_ttm_placement_from_domain(bo, domain); |
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| 292 | if (domain == RADEON_GEM_DOMAIN_VRAM) { |
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| 293 | /* force to pin into visible video ram */ |
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| 294 | bo->placement.lpfn = bo->rdev->mc.visible_vram_size >> PAGE_SHIFT; |
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| 295 | } |
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| 296 | if (max_offset) { |
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| 297 | u64 lpfn = max_offset >> PAGE_SHIFT; |
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| 298 | |||
| 299 | if (!bo->placement.lpfn) |
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| 300 | bo->placement.lpfn = bo->rdev->mc.gtt_size >> PAGE_SHIFT; |
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| 301 | |||
| 302 | if (lpfn < bo->placement.lpfn) |
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| 303 | bo->placement.lpfn = lpfn; |
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| 304 | } |
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| 305 | for (i = 0; i < bo->placement.num_placement; i++) |
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| 306 | bo->placements[i] |= TTM_PL_FLAG_NO_EVICT; |
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| 307 | r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false); |
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| 308 | if (likely(r == 0)) { |
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| 309 | bo->pin_count = 1; |
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| 310 | if (gpu_addr != NULL) |
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| 311 | *gpu_addr = radeon_bo_gpu_offset(bo); |
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| 312 | if (domain == RADEON_GEM_DOMAIN_VRAM) |
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| 313 | bo->rdev->vram_pin_size += radeon_bo_size(bo); |
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| 314 | else |
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| 315 | bo->rdev->gart_pin_size += radeon_bo_size(bo); |
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| 316 | } else { |
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| 317 | dev_err(bo->rdev->dev, "%p pin failed\n", bo); |
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| 318 | } |
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| 319 | return r; |
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| 320 | } |
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| 321 | |||
| 322 | int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr) |
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| 323 | { |
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| 324 | return radeon_bo_pin_restricted(bo, domain, 0, gpu_addr); |
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| 325 | } |
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| 326 | |||
| 327 | int radeon_bo_unpin(struct radeon_bo *bo) |
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| 328 | { |
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| 329 | int r, i; |
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| 330 | |||
| 331 | if (!bo->pin_count) { |
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| 332 | dev_warn(bo->rdev->dev, "%p unpin not necessary\n", bo); |
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| 333 | return 0; |
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| 334 | } |
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| 335 | bo->pin_count--; |
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| 336 | if (bo->pin_count) |
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| 337 | return 0; |
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| 338 | for (i = 0; i < bo->placement.num_placement; i++) |
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| 339 | bo->placements[i] &= ~TTM_PL_FLAG_NO_EVICT; |
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| 340 | r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false); |
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| 341 | if (likely(r == 0)) { |
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| 342 | if (bo->tbo.mem.mem_type == TTM_PL_VRAM) |
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| 343 | bo->rdev->vram_pin_size -= radeon_bo_size(bo); |
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| 344 | else |
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| 345 | bo->rdev->gart_pin_size -= radeon_bo_size(bo); |
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| 346 | } else { |
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| 347 | dev_err(bo->rdev->dev, "%p validate failed for unpin\n", bo); |
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| 348 | } |
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| 349 | return r; |
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| 350 | } |
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| 351 | |||
| 352 | int radeon_bo_init(struct radeon_device *rdev) |
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| 353 | { |
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| 354 | /* Add an MTRR for the VRAM */ |
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| 355 | DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n", |
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| 356 | rdev->mc.mc_vram_size >> 20, |
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| 357 | (unsigned long long)rdev->mc.aper_size >> 20); |
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| 358 | DRM_INFO("RAM width %dbits %cDR\n", |
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| 359 | rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S'); |
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| 360 | return radeon_ttm_init(rdev); |
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| 361 | } |
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| 362 | |||
| 363 | void radeon_bo_fini(struct radeon_device *rdev) |
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| 364 | { |
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| 365 | // radeon_ttm_fini(rdev); |
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| 366 | // arch_phys_wc_del(rdev->mc.vram_mtrr); |
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| 367 | } |
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| 368 | |||
| 369 | /* Returns how many bytes TTM can move per IB. |
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| 370 | */ |
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| 371 | static u64 radeon_bo_get_threshold_for_moves(struct radeon_device *rdev) |
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| 372 | { |
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| 373 | u64 real_vram_size = rdev->mc.real_vram_size; |
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| 374 | u64 vram_usage = atomic64_read(&rdev->vram_usage); |
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| 375 | |||
| 376 | /* This function is based on the current VRAM usage. |
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| 377 | * |
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| 378 | * - If all of VRAM is free, allow relocating the number of bytes that |
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| 379 | * is equal to 1/4 of the size of VRAM for this IB. |
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| 380 | |||
| 381 | * - If more than one half of VRAM is occupied, only allow relocating |
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| 382 | * 1 MB of data for this IB. |
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| 383 | * |
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| 384 | * - From 0 to one half of used VRAM, the threshold decreases |
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| 385 | * linearly. |
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| 386 | * __________________ |
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| 387 | * 1/4 of -|\ | |
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| 388 | * VRAM | \ | |
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| 389 | * | \ | |
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| 390 | * | \ | |
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| 391 | * | \ | |
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| 392 | * | \ | |
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| 393 | * | \ | |
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| 394 | * | \________|1 MB |
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| 395 | * |----------------| |
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| 396 | * VRAM 0 % 100 % |
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| 397 | * used used |
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| 398 | * |
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| 399 | * Note: It's a threshold, not a limit. The threshold must be crossed |
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| 400 | * for buffer relocations to stop, so any buffer of an arbitrary size |
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| 401 | * can be moved as long as the threshold isn't crossed before |
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| 402 | * the relocation takes place. We don't want to disable buffer |
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| 403 | * relocations completely. |
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| 404 | * |
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| 405 | * The idea is that buffers should be placed in VRAM at creation time |
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| 406 | * and TTM should only do a minimum number of relocations during |
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| 407 | * command submission. In practice, you need to submit at least |
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| 408 | * a dozen IBs to move all buffers to VRAM if they are in GTT. |
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| 409 | * |
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| 410 | * Also, things can get pretty crazy under memory pressure and actual |
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| 411 | * VRAM usage can change a lot, so playing safe even at 50% does |
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| 412 | * consistently increase performance. |
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| 413 | */ |
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| 414 | |||
| 415 | u64 half_vram = real_vram_size >> 1; |
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| 416 | u64 half_free_vram = vram_usage >= half_vram ? 0 : half_vram - vram_usage; |
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| 417 | u64 bytes_moved_threshold = half_free_vram >> 1; |
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| 418 | return max(bytes_moved_threshold, 1024*1024ull); |
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| 419 | } |
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| 420 | |||
| 421 | int radeon_bo_list_validate(struct radeon_device *rdev, |
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| 422 | struct ww_acquire_ctx *ticket, |
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| 423 | struct list_head *head, int ring) |
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| 424 | { |
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| 425 | struct radeon_cs_reloc *lobj; |
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| 426 | struct radeon_bo *bo; |
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| 427 | int r; |
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| 428 | u64 bytes_moved = 0, initial_bytes_moved; |
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| 429 | u64 bytes_moved_threshold = radeon_bo_get_threshold_for_moves(rdev); |
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| 430 | |||
| 431 | r = ttm_eu_reserve_buffers(ticket, head); |
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| 432 | if (unlikely(r != 0)) { |
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| 433 | return r; |
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| 434 | } |
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| 435 | |||
| 436 | list_for_each_entry(lobj, head, tv.head) { |
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| 437 | bo = lobj->robj; |
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| 438 | if (!bo->pin_count) { |
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| 439 | u32 domain = lobj->prefered_domains; |
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| 440 | u32 current_domain = |
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| 441 | radeon_mem_type_to_domain(bo->tbo.mem.mem_type); |
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| 442 | |||
| 443 | /* Check if this buffer will be moved and don't move it |
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| 444 | * if we have moved too many buffers for this IB already. |
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| 445 | * |
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| 446 | * Note that this allows moving at least one buffer of |
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| 447 | * any size, because it doesn't take the current "bo" |
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| 448 | * into account. We don't want to disallow buffer moves |
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| 449 | * completely. |
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| 450 | */ |
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| 451 | if ((lobj->allowed_domains & current_domain) != 0 && |
||
| 452 | (domain & current_domain) == 0 && /* will be moved */ |
||
| 453 | bytes_moved > bytes_moved_threshold) { |
||
| 454 | /* don't move it */ |
||
| 455 | domain = current_domain; |
||
| 456 | } |
||
| 457 | |||
| 458 | retry: |
||
| 459 | radeon_ttm_placement_from_domain(bo, domain); |
||
| 460 | if (ring == R600_RING_TYPE_UVD_INDEX) |
||
| 461 | radeon_uvd_force_into_uvd_segment(bo); |
||
| 462 | |||
| 463 | initial_bytes_moved = atomic64_read(&rdev->num_bytes_moved); |
||
| 464 | r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false); |
||
| 465 | bytes_moved += atomic64_read(&rdev->num_bytes_moved) - |
||
| 466 | initial_bytes_moved; |
||
| 467 | |||
| 468 | if (unlikely(r)) { |
||
| 469 | if (r != -ERESTARTSYS && |
||
| 470 | domain != lobj->allowed_domains) { |
||
| 471 | domain = lobj->allowed_domains; |
||
| 472 | goto retry; |
||
| 473 | } |
||
| 474 | ttm_eu_backoff_reservation(ticket, head); |
||
| 475 | return r; |
||
| 476 | } |
||
| 477 | } |
||
| 478 | lobj->gpu_offset = radeon_bo_gpu_offset(bo); |
||
| 479 | lobj->tiling_flags = bo->tiling_flags; |
||
| 480 | } |
||
| 481 | return 0; |
||
| 482 | } |
||
| 483 | |||
| 484 | int radeon_bo_get_surface_reg(struct radeon_bo *bo) |
||
| 485 | { |
||
| 486 | struct radeon_device *rdev = bo->rdev; |
||
| 487 | struct radeon_surface_reg *reg; |
||
| 488 | struct radeon_bo *old_object; |
||
| 489 | int steal; |
||
| 490 | int i; |
||
| 491 | |||
| 492 | lockdep_assert_held(&bo->tbo.resv->lock.base); |
||
| 493 | |||
| 494 | if (!bo->tiling_flags) |
||
| 495 | return 0; |
||
| 496 | |||
| 497 | if (bo->surface_reg >= 0) { |
||
| 498 | reg = &rdev->surface_regs[bo->surface_reg]; |
||
| 499 | i = bo->surface_reg; |
||
| 500 | goto out; |
||
| 501 | } |
||
| 502 | |||
| 503 | steal = -1; |
||
| 504 | for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) { |
||
| 505 | |||
| 506 | reg = &rdev->surface_regs[i]; |
||
| 507 | if (!reg->bo) |
||
| 508 | break; |
||
| 509 | |||
| 510 | old_object = reg->bo; |
||
| 511 | if (old_object->pin_count == 0) |
||
| 512 | steal = i; |
||
| 513 | } |
||
| 514 | |||
| 515 | /* if we are all out */ |
||
| 516 | if (i == RADEON_GEM_MAX_SURFACES) { |
||
| 517 | if (steal == -1) |
||
| 518 | return -ENOMEM; |
||
| 519 | /* find someone with a surface reg and nuke their BO */ |
||
| 520 | reg = &rdev->surface_regs[steal]; |
||
| 521 | old_object = reg->bo; |
||
| 522 | /* blow away the mapping */ |
||
| 523 | DRM_DEBUG("stealing surface reg %d from %p\n", steal, old_object); |
||
| 524 | ttm_bo_unmap_virtual(&old_object->tbo); |
||
| 525 | old_object->surface_reg = -1; |
||
| 526 | i = steal; |
||
| 527 | } |
||
| 528 | |||
| 529 | bo->surface_reg = i; |
||
| 530 | reg->bo = bo; |
||
| 531 | |||
| 532 | out: |
||
| 533 | radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch, |
||
| 534 | bo->tbo.mem.start << PAGE_SHIFT, |
||
| 535 | bo->tbo.num_pages << PAGE_SHIFT); |
||
| 536 | return 0; |
||
| 537 | } |
||
| 538 | |||
| 539 | static void radeon_bo_clear_surface_reg(struct radeon_bo *bo) |
||
| 540 | { |
||
| 541 | struct radeon_device *rdev = bo->rdev; |
||
| 542 | struct radeon_surface_reg *reg; |
||
| 543 | |||
| 544 | if (bo->surface_reg == -1) |
||
| 545 | return; |
||
| 546 | |||
| 547 | reg = &rdev->surface_regs[bo->surface_reg]; |
||
| 548 | radeon_clear_surface_reg(rdev, bo->surface_reg); |
||
| 549 | |||
| 550 | reg->bo = NULL; |
||
| 551 | bo->surface_reg = -1; |
||
| 552 | } |
||
| 553 | |||
| 554 | int radeon_bo_set_tiling_flags(struct radeon_bo *bo, |
||
| 555 | uint32_t tiling_flags, uint32_t pitch) |
||
| 556 | { |
||
| 557 | struct radeon_device *rdev = bo->rdev; |
||
| 558 | int r; |
||
| 559 | |||
| 560 | if (rdev->family >= CHIP_CEDAR) { |
||
| 561 | unsigned bankw, bankh, mtaspect, tilesplit, stilesplit; |
||
| 562 | |||
| 563 | bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK; |
||
| 564 | bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK; |
||
| 565 | mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK; |
||
| 566 | tilesplit = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK; |
||
| 567 | stilesplit = (tiling_flags >> RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK; |
||
| 568 | switch (bankw) { |
||
| 569 | case 0: |
||
| 570 | case 1: |
||
| 571 | case 2: |
||
| 572 | case 4: |
||
| 573 | case 8: |
||
| 574 | break; |
||
| 575 | default: |
||
| 576 | return -EINVAL; |
||
| 577 | } |
||
| 578 | switch (bankh) { |
||
| 579 | case 0: |
||
| 580 | case 1: |
||
| 581 | case 2: |
||
| 582 | case 4: |
||
| 583 | case 8: |
||
| 584 | break; |
||
| 585 | default: |
||
| 586 | return -EINVAL; |
||
| 587 | } |
||
| 588 | switch (mtaspect) { |
||
| 589 | case 0: |
||
| 590 | case 1: |
||
| 591 | case 2: |
||
| 592 | case 4: |
||
| 593 | case 8: |
||
| 594 | break; |
||
| 595 | default: |
||
| 596 | return -EINVAL; |
||
| 597 | } |
||
| 598 | if (tilesplit > 6) { |
||
| 599 | return -EINVAL; |
||
| 600 | } |
||
| 601 | if (stilesplit > 6) { |
||
| 602 | return -EINVAL; |
||
| 603 | } |
||
| 604 | } |
||
| 605 | r = radeon_bo_reserve(bo, false); |
||
| 606 | if (unlikely(r != 0)) |
||
| 607 | return r; |
||
| 608 | bo->tiling_flags = tiling_flags; |
||
| 609 | bo->pitch = pitch; |
||
| 610 | radeon_bo_unreserve(bo); |
||
| 611 | return 0; |
||
| 612 | } |
||
| 613 | |||
| 614 | void radeon_bo_get_tiling_flags(struct radeon_bo *bo, |
||
| 615 | uint32_t *tiling_flags, |
||
| 616 | uint32_t *pitch) |
||
| 617 | { |
||
| 618 | lockdep_assert_held(&bo->tbo.resv->lock.base); |
||
| 619 | |||
| 620 | if (tiling_flags) |
||
| 621 | *tiling_flags = bo->tiling_flags; |
||
| 622 | if (pitch) |
||
| 623 | *pitch = bo->pitch; |
||
| 624 | } |
||
| 625 | |||
| 626 | int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved, |
||
| 627 | bool force_drop) |
||
| 628 | { |
||
| 629 | if (!force_drop) |
||
| 630 | lockdep_assert_held(&bo->tbo.resv->lock.base); |
||
| 631 | |||
| 632 | if (!(bo->tiling_flags & RADEON_TILING_SURFACE)) |
||
| 633 | return 0; |
||
| 634 | |||
| 635 | if (force_drop) { |
||
| 636 | radeon_bo_clear_surface_reg(bo); |
||
| 637 | return 0; |
||
| 638 | } |
||
| 639 | |||
| 640 | if (bo->tbo.mem.mem_type != TTM_PL_VRAM) { |
||
| 641 | if (!has_moved) |
||
| 642 | return 0; |
||
| 643 | |||
| 644 | if (bo->surface_reg >= 0) |
||
| 645 | radeon_bo_clear_surface_reg(bo); |
||
| 646 | return 0; |
||
| 647 | } |
||
| 648 | |||
| 649 | if ((bo->surface_reg >= 0) && !has_moved) |
||
| 650 | return 0; |
||
| 651 | |||
| 652 | return radeon_bo_get_surface_reg(bo); |
||
| 653 | } |
||
| 654 | |||
| 655 | void radeon_bo_move_notify(struct ttm_buffer_object *bo, |
||
| 656 | struct ttm_mem_reg *new_mem) |
||
| 657 | { |
||
| 658 | struct radeon_bo *rbo; |
||
| 659 | |||
| 660 | if (!radeon_ttm_bo_is_radeon_bo(bo)) |
||
| 661 | return; |
||
| 662 | |||
| 663 | rbo = container_of(bo, struct radeon_bo, tbo); |
||
| 664 | radeon_bo_check_tiling(rbo, 0, 1); |
||
| 665 | radeon_vm_bo_invalidate(rbo->rdev, rbo); |
||
| 666 | |||
| 667 | /* update statistics */ |
||
| 668 | if (!new_mem) |
||
| 669 | return; |
||
| 670 | |||
| 671 | radeon_update_memory_usage(rbo, bo->mem.mem_type, -1); |
||
| 672 | radeon_update_memory_usage(rbo, new_mem->mem_type, 1); |
||
| 673 | } |
||
| 674 | int radeon_bo_wait(struct radeon_bo *bo, u32 *mem_type, bool no_wait) |
||
| 675 | { |
||
| 676 | int r; |
||
| 677 | |||
| 678 | r = ttm_bo_reserve(&bo->tbo, true, no_wait, false, NULL); |
||
| 679 | if (unlikely(r != 0)) |
||
| 680 | return r; |
||
| 681 | spin_lock(&bo->tbo.bdev->fence_lock); |
||
| 682 | if (mem_type) |
||
| 683 | *mem_type = bo->tbo.mem.mem_type; |
||
| 684 | if (bo->tbo.sync_obj) |
||
| 685 | r = ttm_bo_wait(&bo->tbo, true, true, no_wait); |
||
| 686 | spin_unlock(&bo->tbo.bdev->fence_lock); |
||
| 687 | ttm_bo_unreserve(&bo->tbo); |
||
| 688 | return r; |
||
| 689 | } |