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| Rev | Author | Line No. | Line |
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| 1120 | serge | 1 | /* |
| 2 | * Copyright 2009 Jerome Glisse. |
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| 3 | * All Rights Reserved. |
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| 4 | * |
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| 5 | * Permission is hereby granted, free of charge, to any person obtaining a |
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| 6 | * copy of this software and associated documentation files (the |
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| 7 | * "Software"), to deal in the Software without restriction, including |
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| 8 | * without limitation the rights to use, copy, modify, merge, publish, |
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| 9 | * distribute, sub license, and/or sell copies of the Software, and to |
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| 10 | * permit persons to whom the Software is furnished to do so, subject to |
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| 11 | * the following conditions: |
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| 12 | * |
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| 13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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| 14 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| 15 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL |
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| 16 | * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, |
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| 17 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR |
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| 18 | * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE |
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| 19 | * USE OR OTHER DEALINGS IN THE SOFTWARE. |
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| 20 | * |
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| 21 | * The above copyright notice and this permission notice (including the |
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| 22 | * next paragraph) shall be included in all copies or substantial portions |
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| 23 | * of the Software. |
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| 24 | * |
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| 25 | */ |
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| 26 | /* |
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| 27 | * Authors: |
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| 28 | * Jerome Glisse |
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| 29 | * Thomas Hellstrom |
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| 30 | * Dave Airlie |
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| 31 | */ |
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| 1179 | serge | 32 | #include |
| 1963 | serge | 33 | #include |
| 1179 | serge | 34 | #include |
| 1120 | serge | 35 | #include "radeon_drm.h" |
| 36 | #include "radeon.h" |
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| 37 | #include |
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| 1126 | serge | 38 | #include "radeon_object.h" |
| 1120 | serge | 39 | |
| 40 | int radeon_gart_bind(struct radeon_device *rdev, unsigned offset, |
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| 41 | int pages, u32_t *pagelist); |
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| 42 | |||
| 43 | |||
| 44 | |||
| 45 | |||
| 46 | static struct drm_mm mm_gtt; |
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| 47 | static struct drm_mm mm_vram; |
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| 48 | |||
| 49 | |||
| 50 | int radeon_object_init(struct radeon_device *rdev) |
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| 51 | { |
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| 52 | int r = 0; |
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| 53 | |||
| 1182 | serge | 54 | ENTER(); |
| 1125 | serge | 55 | |
| 1313 | serge | 56 | r = drm_mm_init(&mm_vram, 0xC00000 >> PAGE_SHIFT, |
| 57 | ((rdev->mc.real_vram_size - 0xC00000) >> PAGE_SHIFT)); |
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| 1120 | serge | 58 | if (r) { |
| 59 | DRM_ERROR("Failed initializing VRAM heap.\n"); |
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| 60 | return r; |
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| 61 | }; |
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| 62 | |||
| 63 | r = drm_mm_init(&mm_gtt, 0, ((rdev->mc.gtt_size) >> PAGE_SHIFT)); |
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| 64 | if (r) { |
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| 65 | DRM_ERROR("Failed initializing GTT heap.\n"); |
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| 66 | return r; |
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| 67 | } |
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| 68 | |||
| 69 | return r; |
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| 70 | // return radeon_ttm_init(rdev); |
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| 71 | } |
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| 72 | |||
| 73 | static inline uint32_t radeon_object_flags_from_domain(uint32_t domain) |
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| 74 | { |
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| 75 | uint32_t flags = 0; |
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| 76 | if (domain & RADEON_GEM_DOMAIN_VRAM) { |
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| 77 | flags |= TTM_PL_FLAG_VRAM; |
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| 78 | } |
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| 79 | if (domain & RADEON_GEM_DOMAIN_GTT) { |
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| 80 | flags |= TTM_PL_FLAG_TT; |
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| 81 | } |
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| 82 | if (domain & RADEON_GEM_DOMAIN_CPU) { |
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| 83 | flags |= TTM_PL_FLAG_SYSTEM; |
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| 84 | } |
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| 85 | if (!flags) { |
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| 86 | flags |= TTM_PL_FLAG_SYSTEM; |
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| 87 | } |
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| 88 | return flags; |
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| 89 | } |
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| 90 | |||
| 91 | |||
| 1963 | serge | 92 | int radeon_bo_create(struct radeon_device *rdev, |
| 93 | unsigned long size, int byte_align, bool kernel, u32 domain, |
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| 94 | struct radeon_bo **bo_ptr) |
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| 1120 | serge | 95 | { |
| 1963 | serge | 96 | struct radeon_bo *bo; |
| 1120 | serge | 97 | enum ttm_bo_type type; |
| 98 | uint32_t flags; |
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| 99 | int r; |
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| 100 | |||
| 101 | if (kernel) { |
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| 102 | type = ttm_bo_type_kernel; |
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| 103 | } else { |
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| 104 | type = ttm_bo_type_device; |
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| 105 | } |
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| 1963 | serge | 106 | *bo_ptr = NULL; |
| 107 | bo = kzalloc(sizeof(struct radeon_object), GFP_KERNEL); |
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| 108 | if (bo == NULL) { |
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| 1120 | serge | 109 | return -ENOMEM; |
| 110 | } |
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| 1963 | serge | 111 | bo->rdev = rdev; |
| 112 | INIT_LIST_HEAD(&bo->list); |
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| 1120 | serge | 113 | |
| 114 | flags = radeon_object_flags_from_domain(domain); |
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| 115 | |||
| 1963 | serge | 116 | bo->flags = flags; |
| 1120 | serge | 117 | |
| 118 | if( flags & TTM_PL_FLAG_VRAM) |
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| 119 | { |
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| 120 | size_t num_pages; |
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| 121 | |||
| 122 | struct drm_mm_node *vm_node; |
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| 123 | |||
| 124 | num_pages = (size + PAGE_SIZE - 1) >> PAGE_SHIFT; |
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| 125 | |||
| 126 | if (num_pages == 0) { |
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| 1182 | serge | 127 | dbgprintf("Illegal buffer object size.\n"); |
| 1120 | serge | 128 | return -EINVAL; |
| 129 | } |
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| 130 | retry_pre_get: |
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| 131 | r = drm_mm_pre_get(&mm_vram); |
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| 132 | |||
| 133 | if (unlikely(r != 0)) |
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| 134 | return r; |
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| 135 | |||
| 136 | vm_node = drm_mm_search_free(&mm_vram, num_pages, 0, 0); |
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| 137 | |||
| 138 | if (unlikely(vm_node == NULL)) { |
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| 139 | r = -ENOMEM; |
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| 140 | return r; |
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| 141 | } |
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| 142 | |||
| 1963 | serge | 143 | bo->mm_node = drm_mm_get_block_atomic(vm_node, num_pages, 0); |
| 1120 | serge | 144 | |
| 1963 | serge | 145 | if (unlikely(bo->mm_node == NULL)) { |
| 1120 | serge | 146 | goto retry_pre_get; |
| 147 | } |
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| 148 | |||
| 1963 | serge | 149 | bo->vm_addr = ((uint32_t)bo->mm_node->start); |
| 1120 | serge | 150 | |
| 1268 | serge | 151 | // dbgprintf("alloc vram: base %x size %x\n", |
| 152 | // robj->vm_addr << PAGE_SHIFT, num_pages << PAGE_SHIFT); |
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| 1120 | serge | 153 | |
| 154 | }; |
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| 155 | |||
| 156 | if( flags & TTM_PL_FLAG_TT) |
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| 157 | { |
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| 158 | size_t num_pages; |
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| 159 | |||
| 160 | struct drm_mm_node *vm_node; |
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| 161 | |||
| 162 | num_pages = (size + PAGE_SIZE - 1) >> PAGE_SHIFT; |
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| 163 | |||
| 164 | if (num_pages == 0) { |
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| 1182 | serge | 165 | dbgprintf("Illegal buffer object size.\n"); |
| 1120 | serge | 166 | return -EINVAL; |
| 167 | } |
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| 168 | retry_pre_get1: |
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| 169 | r = drm_mm_pre_get(&mm_gtt); |
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| 170 | |||
| 171 | if (unlikely(r != 0)) |
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| 172 | return r; |
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| 173 | |||
| 174 | vm_node = drm_mm_search_free(&mm_gtt, num_pages, 0, 0); |
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| 175 | |||
| 176 | if (unlikely(vm_node == NULL)) { |
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| 177 | r = -ENOMEM; |
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| 178 | return r; |
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| 179 | } |
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| 180 | |||
| 181 | robj->mm_node = drm_mm_get_block_atomic(vm_node, num_pages, 0); |
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| 182 | |||
| 183 | if (unlikely(robj->mm_node == NULL)) { |
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| 184 | goto retry_pre_get1; |
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| 185 | } |
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| 186 | |||
| 1963 | serge | 187 | bo->vm_addr = ((uint32_t)bo->mm_node->start) ; |
| 1120 | serge | 188 | |
| 1268 | serge | 189 | // dbgprintf("alloc gtt: base %x size %x\n", |
| 190 | // robj->vm_addr << PAGE_SHIFT, num_pages << PAGE_SHIFT); |
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| 1120 | serge | 191 | }; |
| 192 | |||
| 193 | // r = ttm_buffer_object_init(&rdev->mman.bdev, &robj->tobj, size, type, flags, |
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| 194 | // 0, 0, false, NULL, size, |
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| 195 | // &radeon_ttm_object_object_destroy); |
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| 196 | if (unlikely(r != 0)) { |
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| 197 | /* ttm call radeon_ttm_object_object_destroy if error happen */ |
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| 198 | DRM_ERROR("Failed to allocate TTM object (%ld, 0x%08X, %u)\n", |
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| 199 | size, flags, 0); |
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| 200 | return r; |
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| 201 | } |
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| 202 | *robj_ptr = robj; |
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| 203 | // if (gobj) { |
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| 204 | // list_add_tail(&robj->list, &rdev->gem.objects); |
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| 205 | // } |
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| 206 | return 0; |
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| 207 | } |
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| 208 | |||
| 209 | #define page_tabs 0xFDC00000 |
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| 210 | |||
| 211 | int radeon_object_pin(struct radeon_object *robj, uint32_t domain, |
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| 212 | uint64_t *gpu_addr) |
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| 213 | { |
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| 214 | uint32_t flags; |
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| 215 | uint32_t tmp; |
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| 216 | int r = 0; |
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| 217 | |||
| 218 | // flags = radeon_object_flags_from_domain(domain); |
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| 219 | // spin_lock(&robj->tobj.lock); |
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| 220 | if (robj->pin_count) { |
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| 221 | robj->pin_count++; |
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| 222 | if (gpu_addr != NULL) { |
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| 223 | *gpu_addr = robj->gpu_addr; |
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| 224 | } |
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| 225 | // spin_unlock(&robj->tobj.lock); |
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| 226 | return 0; |
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| 227 | } |
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| 228 | // spin_unlock(&robj->tobj.lock); |
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| 229 | // r = radeon_object_reserve(robj, false); |
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| 230 | // if (unlikely(r != 0)) { |
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| 231 | // DRM_ERROR("radeon: failed to reserve object for pinning it.\n"); |
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| 232 | // return r; |
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| 233 | // } |
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| 234 | // tmp = robj->tobj.mem.placement; |
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| 235 | // ttm_flag_masked(&tmp, flags, TTM_PL_MASK_MEM); |
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| 236 | // robj->tobj.proposed_placement = tmp | TTM_PL_FLAG_NO_EVICT | TTM_PL_MASK_CACHING; |
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| 237 | // r = ttm_buffer_object_validate(&robj->tobj, |
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| 238 | // robj->tobj.proposed_placement, |
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| 239 | // false, false); |
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| 240 | |||
| 241 | robj->gpu_addr = ((u64)robj->vm_addr) << PAGE_SHIFT; |
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| 242 | |||
| 243 | if(robj->flags & TTM_PL_FLAG_VRAM) |
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| 244 | robj->gpu_addr += (u64)robj->rdev->mc.vram_location; |
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| 245 | else if (robj->flags & TTM_PL_FLAG_TT) |
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| 246 | { |
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| 247 | u32_t *pagelist; |
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| 248 | robj->kptr = KernelAlloc( robj->mm_node->size << PAGE_SHIFT ); |
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| 249 | dbgprintf("kernel alloc %x\n", robj->kptr ); |
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| 250 | |||
| 251 | pagelist = &((u32_t*)page_tabs)[(u32_t)robj->kptr >> 12]; |
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| 252 | dbgprintf("pagelist %x\n", pagelist); |
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| 253 | radeon_gart_bind(robj->rdev, robj->gpu_addr, |
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| 254 | robj->mm_node->size, pagelist); |
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| 255 | robj->gpu_addr += (u64)robj->rdev->mc.gtt_location; |
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| 256 | } |
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| 257 | else |
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| 258 | { |
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| 259 | DRM_ERROR("Unknown placement %d\n", robj->flags); |
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| 260 | robj->gpu_addr = 0xFFFFFFFFFFFFFFFFULL; |
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| 261 | r = -1; |
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| 262 | }; |
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| 263 | |||
| 264 | // flags & TTM_PL_FLAG_VRAM |
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| 265 | if (gpu_addr != NULL) { |
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| 266 | *gpu_addr = robj->gpu_addr; |
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| 267 | } |
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| 268 | robj->pin_count = 1; |
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| 269 | if (unlikely(r != 0)) { |
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| 270 | DRM_ERROR("radeon: failed to pin object.\n"); |
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| 271 | } |
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| 272 | |||
| 273 | return r; |
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| 274 | } |
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| 275 | |||
| 276 | int radeon_object_kmap(struct radeon_object *robj, void **ptr) |
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| 277 | { |
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| 278 | int r = 0; |
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| 279 | |||
| 280 | // spin_lock(&robj->tobj.lock); |
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| 281 | if (robj->kptr) { |
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| 282 | if (ptr) { |
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| 283 | *ptr = robj->kptr; |
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| 284 | } |
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| 285 | // spin_unlock(&robj->tobj.lock); |
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| 286 | return 0; |
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| 287 | } |
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| 288 | // spin_unlock(&robj->tobj.lock); |
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| 289 | |||
| 290 | if(robj->flags & TTM_PL_FLAG_VRAM) |
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| 291 | { |
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| 292 | robj->cpu_addr = robj->rdev->mc.aper_base + |
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| 293 | (robj->vm_addr << PAGE_SHIFT); |
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| 294 | robj->kptr = (void*)MapIoMem(robj->cpu_addr, |
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| 295 | robj->mm_node->size << 12, PG_SW); |
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| 296 | } |
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| 297 | else |
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| 298 | { |
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| 299 | return -1; |
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| 300 | } |
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| 301 | |||
| 302 | if (ptr) { |
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| 303 | *ptr = robj->kptr; |
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| 304 | } |
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| 305 | |||
| 306 | return 0; |
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| 307 | } |
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| 308 | |||
| 1182 | serge | 309 | void radeon_object_kunmap(struct radeon_object *robj) |
| 310 | { |
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| 311 | // spin_lock(&robj->tobj.lock); |
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| 312 | if (robj->kptr == NULL) { |
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| 313 | // spin_unlock(&robj->tobj.lock); |
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| 314 | return; |
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| 315 | } |
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| 1120 | serge | 316 | |
| 1182 | serge | 317 | if (robj->flags & TTM_PL_FLAG_VRAM) |
| 318 | { |
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| 319 | FreeKernelSpace(robj->kptr); |
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| 320 | robj->kptr = NULL; |
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| 321 | } |
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| 322 | // spin_unlock(&robj->tobj.lock); |
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| 323 | } |
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| 324 | |||
| 1120 | serge | 325 | |
| 326 | void radeon_object_unpin(struct radeon_object *robj) |
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| 327 | { |
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| 328 | uint32_t flags; |
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| 329 | int r; |
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| 330 | |||
| 331 | // spin_lock(&robj->tobj.lock); |
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| 332 | if (!robj->pin_count) { |
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| 333 | // spin_unlock(&robj->tobj.lock); |
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| 334 | printk(KERN_WARNING "Unpin not necessary for %p !\n", robj); |
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| 335 | return; |
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| 336 | } |
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| 337 | robj->pin_count--; |
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| 338 | if (robj->pin_count) { |
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| 339 | // spin_unlock(&robj->tobj.lock); |
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| 340 | return; |
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| 341 | } |
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| 342 | // spin_unlock(&robj->tobj.lock); |
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| 1313 | serge | 343 | |
| 344 | drm_mm_put_block(robj->mm_node); |
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| 345 | |||
| 346 | kfree(robj); |
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| 1120 | serge | 347 | } |
| 348 | |||
| 349 | |||
| 1313 | serge | 350 | #if 0 |
| 1120 | serge | 351 | |
| 352 | |||
| 353 | /* |
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| 354 | * To exclude mutual BO access we rely on bo_reserve exclusion, as all |
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| 355 | * function are calling it. |
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| 356 | */ |
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| 357 | |||
| 358 | static int radeon_object_reserve(struct radeon_object *robj, bool interruptible) |
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| 359 | { |
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| 360 | return ttm_bo_reserve(&robj->tobj, interruptible, false, false, 0); |
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| 361 | } |
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| 362 | |||
| 363 | static void radeon_object_unreserve(struct radeon_object *robj) |
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| 364 | { |
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| 365 | ttm_bo_unreserve(&robj->tobj); |
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| 366 | } |
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| 367 | |||
| 368 | static void radeon_ttm_object_object_destroy(struct ttm_buffer_object *tobj) |
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| 369 | { |
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| 370 | struct radeon_object *robj; |
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| 371 | |||
| 372 | robj = container_of(tobj, struct radeon_object, tobj); |
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| 373 | // list_del_init(&robj->list); |
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| 374 | kfree(robj); |
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| 375 | } |
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| 376 | |||
| 377 | static inline void radeon_object_gpu_addr(struct radeon_object *robj) |
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| 378 | { |
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| 379 | /* Default gpu address */ |
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| 380 | robj->gpu_addr = 0xFFFFFFFFFFFFFFFFULL; |
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| 381 | if (robj->tobj.mem.mm_node == NULL) { |
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| 382 | return; |
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| 383 | } |
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| 384 | robj->gpu_addr = ((u64)robj->tobj.mem.mm_node->start) << PAGE_SHIFT; |
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| 385 | switch (robj->tobj.mem.mem_type) { |
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| 386 | case TTM_PL_VRAM: |
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| 387 | robj->gpu_addr += (u64)robj->rdev->mc.vram_location; |
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| 388 | break; |
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| 389 | case TTM_PL_TT: |
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| 390 | robj->gpu_addr += (u64)robj->rdev->mc.gtt_location; |
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| 391 | break; |
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| 392 | default: |
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| 393 | DRM_ERROR("Unknown placement %d\n", robj->tobj.mem.mem_type); |
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| 394 | robj->gpu_addr = 0xFFFFFFFFFFFFFFFFULL; |
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| 395 | return; |
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| 396 | } |
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| 397 | } |
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| 398 | |||
| 399 | |||
| 400 | int radeon_object_create(struct radeon_device *rdev, |
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| 401 | struct drm_gem_object *gobj, |
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| 402 | unsigned long size, |
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| 403 | bool kernel, |
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| 404 | uint32_t domain, |
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| 405 | bool interruptible, |
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| 406 | struct radeon_object **robj_ptr) |
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| 407 | { |
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| 408 | struct radeon_object *robj; |
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| 409 | enum ttm_bo_type type; |
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| 410 | uint32_t flags; |
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| 411 | int r; |
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| 412 | |||
| 413 | // if (unlikely(rdev->mman.bdev.dev_mapping == NULL)) { |
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| 414 | // rdev->mman.bdev.dev_mapping = rdev->ddev->dev_mapping; |
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| 415 | // } |
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| 416 | if (kernel) { |
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| 417 | type = ttm_bo_type_kernel; |
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| 418 | } else { |
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| 419 | type = ttm_bo_type_device; |
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| 420 | } |
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| 421 | *robj_ptr = NULL; |
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| 422 | robj = kzalloc(sizeof(struct radeon_object), GFP_KERNEL); |
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| 423 | if (robj == NULL) { |
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| 424 | return -ENOMEM; |
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| 425 | } |
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| 426 | robj->rdev = rdev; |
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| 427 | robj->gobj = gobj; |
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| 428 | // INIT_LIST_HEAD(&robj->list); |
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| 429 | |||
| 430 | flags = radeon_object_flags_from_domain(domain); |
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| 431 | // r = ttm_buffer_object_init(&rdev->mman.bdev, &robj->tobj, size, type, flags, |
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| 432 | // 0, 0, false, NULL, size, |
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| 433 | // &radeon_ttm_object_object_destroy); |
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| 434 | if (unlikely(r != 0)) { |
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| 435 | /* ttm call radeon_ttm_object_object_destroy if error happen */ |
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| 436 | DRM_ERROR("Failed to allocate TTM object (%ld, 0x%08X, %u)\n", |
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| 437 | size, flags, 0); |
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| 438 | return r; |
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| 439 | } |
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| 440 | *robj_ptr = robj; |
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| 441 | // if (gobj) { |
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| 442 | // list_add_tail(&robj->list, &rdev->gem.objects); |
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| 443 | // } |
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| 444 | return 0; |
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| 445 | } |
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| 446 | |||
| 447 | int radeon_object_kmap(struct radeon_object *robj, void **ptr) |
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| 448 | { |
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| 449 | int r; |
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| 450 | |||
| 451 | // spin_lock(&robj->tobj.lock); |
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| 452 | if (robj->kptr) { |
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| 453 | if (ptr) { |
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| 454 | *ptr = robj->kptr; |
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| 455 | } |
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| 456 | // spin_unlock(&robj->tobj.lock); |
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| 457 | return 0; |
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| 458 | } |
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| 459 | // spin_unlock(&robj->tobj.lock); |
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| 460 | r = ttm_bo_kmap(&robj->tobj, 0, robj->tobj.num_pages, &robj->kmap); |
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| 461 | if (r) { |
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| 462 | return r; |
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| 463 | } |
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| 464 | // spin_lock(&robj->tobj.lock); |
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| 465 | robj->kptr = ttm_kmap_obj_virtual(&robj->kmap, &robj->is_iomem); |
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| 466 | // spin_unlock(&robj->tobj.lock); |
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| 467 | if (ptr) { |
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| 468 | *ptr = robj->kptr; |
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| 469 | } |
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| 470 | return 0; |
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| 471 | } |
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| 472 | |||
| 473 | void radeon_object_kunmap(struct radeon_object *robj) |
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| 474 | { |
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| 475 | // spin_lock(&robj->tobj.lock); |
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| 476 | if (robj->kptr == NULL) { |
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| 477 | // spin_unlock(&robj->tobj.lock); |
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| 478 | return; |
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| 479 | } |
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| 480 | robj->kptr = NULL; |
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| 481 | // spin_unlock(&robj->tobj.lock); |
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| 482 | ttm_bo_kunmap(&robj->kmap); |
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| 483 | } |
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| 484 | |||
| 485 | void radeon_object_unref(struct radeon_object **robj) |
||
| 486 | { |
||
| 487 | struct ttm_buffer_object *tobj; |
||
| 488 | |||
| 489 | if ((*robj) == NULL) { |
||
| 490 | return; |
||
| 491 | } |
||
| 492 | tobj = &((*robj)->tobj); |
||
| 493 | ttm_bo_unref(&tobj); |
||
| 494 | if (tobj == NULL) { |
||
| 495 | *robj = NULL; |
||
| 496 | } |
||
| 497 | } |
||
| 498 | |||
| 499 | int radeon_object_mmap(struct radeon_object *robj, uint64_t *offset) |
||
| 500 | { |
||
| 501 | *offset = robj->tobj.addr_space_offset; |
||
| 502 | return 0; |
||
| 503 | } |
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| 504 | |||
| 505 | int radeon_object_pin(struct radeon_object *robj, uint32_t domain, |
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| 506 | uint64_t *gpu_addr) |
||
| 507 | { |
||
| 508 | uint32_t flags; |
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| 509 | uint32_t tmp; |
||
| 510 | int r; |
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| 511 | |||
| 512 | flags = radeon_object_flags_from_domain(domain); |
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| 513 | // spin_lock(&robj->tobj.lock); |
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| 514 | if (robj->pin_count) { |
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| 515 | robj->pin_count++; |
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| 516 | if (gpu_addr != NULL) { |
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| 517 | *gpu_addr = robj->gpu_addr; |
||
| 518 | } |
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| 519 | // spin_unlock(&robj->tobj.lock); |
||
| 520 | return 0; |
||
| 521 | } |
||
| 522 | // spin_unlock(&robj->tobj.lock); |
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| 523 | r = radeon_object_reserve(robj, false); |
||
| 524 | if (unlikely(r != 0)) { |
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| 525 | DRM_ERROR("radeon: failed to reserve object for pinning it.\n"); |
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| 526 | return r; |
||
| 527 | } |
||
| 528 | tmp = robj->tobj.mem.placement; |
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| 529 | ttm_flag_masked(&tmp, flags, TTM_PL_MASK_MEM); |
||
| 530 | robj->tobj.proposed_placement = tmp | TTM_PL_FLAG_NO_EVICT | TTM_PL_MASK_CACHING; |
||
| 531 | r = ttm_buffer_object_validate(&robj->tobj, |
||
| 532 | robj->tobj.proposed_placement, |
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| 533 | false, false); |
||
| 534 | radeon_object_gpu_addr(robj); |
||
| 535 | if (gpu_addr != NULL) { |
||
| 536 | *gpu_addr = robj->gpu_addr; |
||
| 537 | } |
||
| 538 | robj->pin_count = 1; |
||
| 539 | if (unlikely(r != 0)) { |
||
| 540 | DRM_ERROR("radeon: failed to pin object.\n"); |
||
| 541 | } |
||
| 542 | radeon_object_unreserve(robj); |
||
| 543 | return r; |
||
| 544 | } |
||
| 545 | |||
| 546 | void radeon_object_unpin(struct radeon_object *robj) |
||
| 547 | { |
||
| 548 | uint32_t flags; |
||
| 549 | int r; |
||
| 550 | |||
| 551 | // spin_lock(&robj->tobj.lock); |
||
| 552 | if (!robj->pin_count) { |
||
| 553 | // spin_unlock(&robj->tobj.lock); |
||
| 554 | printk(KERN_WARNING "Unpin not necessary for %p !\n", robj); |
||
| 555 | return; |
||
| 556 | } |
||
| 557 | robj->pin_count--; |
||
| 558 | if (robj->pin_count) { |
||
| 559 | // spin_unlock(&robj->tobj.lock); |
||
| 560 | return; |
||
| 561 | } |
||
| 562 | // spin_unlock(&robj->tobj.lock); |
||
| 563 | r = radeon_object_reserve(robj, false); |
||
| 564 | if (unlikely(r != 0)) { |
||
| 565 | DRM_ERROR("radeon: failed to reserve object for unpinning it.\n"); |
||
| 566 | return; |
||
| 567 | } |
||
| 568 | flags = robj->tobj.mem.placement; |
||
| 569 | robj->tobj.proposed_placement = flags & ~TTM_PL_FLAG_NO_EVICT; |
||
| 570 | r = ttm_buffer_object_validate(&robj->tobj, |
||
| 571 | robj->tobj.proposed_placement, |
||
| 572 | false, false); |
||
| 573 | if (unlikely(r != 0)) { |
||
| 574 | DRM_ERROR("radeon: failed to unpin buffer.\n"); |
||
| 575 | } |
||
| 576 | radeon_object_unreserve(robj); |
||
| 577 | } |
||
| 578 | |||
| 579 | int radeon_object_wait(struct radeon_object *robj) |
||
| 580 | { |
||
| 581 | int r = 0; |
||
| 582 | |||
| 583 | /* FIXME: should use block reservation instead */ |
||
| 584 | r = radeon_object_reserve(robj, true); |
||
| 585 | if (unlikely(r != 0)) { |
||
| 586 | DRM_ERROR("radeon: failed to reserve object for waiting.\n"); |
||
| 587 | return r; |
||
| 588 | } |
||
| 589 | // spin_lock(&robj->tobj.lock); |
||
| 590 | if (robj->tobj.sync_obj) { |
||
| 591 | r = ttm_bo_wait(&robj->tobj, true, false, false); |
||
| 592 | } |
||
| 593 | // spin_unlock(&robj->tobj.lock); |
||
| 594 | radeon_object_unreserve(robj); |
||
| 595 | return r; |
||
| 596 | } |
||
| 597 | |||
| 598 | int radeon_object_evict_vram(struct radeon_device *rdev) |
||
| 599 | { |
||
| 600 | if (rdev->flags & RADEON_IS_IGP) { |
||
| 601 | /* Useless to evict on IGP chips */ |
||
| 602 | return 0; |
||
| 603 | } |
||
| 604 | return ttm_bo_evict_mm(&rdev->mman.bdev, TTM_PL_VRAM); |
||
| 605 | } |
||
| 606 | |||
| 607 | void radeon_object_force_delete(struct radeon_device *rdev) |
||
| 608 | { |
||
| 609 | struct radeon_object *robj, *n; |
||
| 610 | struct drm_gem_object *gobj; |
||
| 611 | |||
| 612 | if (list_empty(&rdev->gem.objects)) { |
||
| 613 | return; |
||
| 614 | } |
||
| 615 | DRM_ERROR("Userspace still has active objects !\n"); |
||
| 616 | list_for_each_entry_safe(robj, n, &rdev->gem.objects, list) { |
||
| 617 | mutex_lock(&rdev->ddev->struct_mutex); |
||
| 618 | gobj = robj->gobj; |
||
| 619 | DRM_ERROR("Force free for (%p,%p,%lu,%lu)\n", |
||
| 620 | gobj, robj, (unsigned long)gobj->size, |
||
| 621 | *((unsigned long *)&gobj->refcount)); |
||
| 622 | list_del_init(&robj->list); |
||
| 623 | radeon_object_unref(&robj); |
||
| 624 | gobj->driver_private = NULL; |
||
| 625 | drm_gem_object_unreference(gobj); |
||
| 626 | mutex_unlock(&rdev->ddev->struct_mutex); |
||
| 627 | } |
||
| 628 | } |
||
| 629 | |||
| 630 | void radeon_object_fini(struct radeon_device *rdev) |
||
| 631 | { |
||
| 632 | radeon_ttm_fini(rdev); |
||
| 633 | } |
||
| 634 | |||
| 635 | void radeon_object_list_add_object(struct radeon_object_list *lobj, |
||
| 636 | struct list_head *head) |
||
| 637 | { |
||
| 638 | if (lobj->wdomain) { |
||
| 639 | list_add(&lobj->list, head); |
||
| 640 | } else { |
||
| 641 | list_add_tail(&lobj->list, head); |
||
| 642 | } |
||
| 643 | } |
||
| 644 | |||
| 645 | int radeon_object_list_reserve(struct list_head *head) |
||
| 646 | { |
||
| 647 | struct radeon_object_list *lobj; |
||
| 648 | struct list_head *i; |
||
| 649 | int r; |
||
| 650 | |||
| 651 | list_for_each(i, head) { |
||
| 652 | lobj = list_entry(i, struct radeon_object_list, list); |
||
| 653 | if (!lobj->robj->pin_count) { |
||
| 654 | r = radeon_object_reserve(lobj->robj, true); |
||
| 655 | if (unlikely(r != 0)) { |
||
| 656 | DRM_ERROR("radeon: failed to reserve object.\n"); |
||
| 657 | return r; |
||
| 658 | } |
||
| 659 | } else { |
||
| 660 | } |
||
| 661 | } |
||
| 662 | return 0; |
||
| 663 | } |
||
| 664 | |||
| 665 | void radeon_object_list_unreserve(struct list_head *head) |
||
| 666 | { |
||
| 667 | struct radeon_object_list *lobj; |
||
| 668 | struct list_head *i; |
||
| 669 | |||
| 670 | list_for_each(i, head) { |
||
| 671 | lobj = list_entry(i, struct radeon_object_list, list); |
||
| 672 | if (!lobj->robj->pin_count) { |
||
| 673 | radeon_object_unreserve(lobj->robj); |
||
| 674 | } else { |
||
| 675 | } |
||
| 676 | } |
||
| 677 | } |
||
| 678 | |||
| 679 | int radeon_object_list_validate(struct list_head *head, void *fence) |
||
| 680 | { |
||
| 681 | struct radeon_object_list *lobj; |
||
| 682 | struct radeon_object *robj; |
||
| 683 | struct radeon_fence *old_fence = NULL; |
||
| 684 | struct list_head *i; |
||
| 685 | uint32_t flags; |
||
| 686 | int r; |
||
| 687 | |||
| 688 | r = radeon_object_list_reserve(head); |
||
| 689 | if (unlikely(r != 0)) { |
||
| 690 | radeon_object_list_unreserve(head); |
||
| 691 | return r; |
||
| 692 | } |
||
| 693 | list_for_each(i, head) { |
||
| 694 | lobj = list_entry(i, struct radeon_object_list, list); |
||
| 695 | robj = lobj->robj; |
||
| 696 | if (lobj->wdomain) { |
||
| 697 | flags = radeon_object_flags_from_domain(lobj->wdomain); |
||
| 698 | flags |= TTM_PL_FLAG_TT; |
||
| 699 | } else { |
||
| 700 | flags = radeon_object_flags_from_domain(lobj->rdomain); |
||
| 701 | flags |= TTM_PL_FLAG_TT; |
||
| 702 | flags |= TTM_PL_FLAG_VRAM; |
||
| 703 | } |
||
| 704 | if (!robj->pin_count) { |
||
| 705 | robj->tobj.proposed_placement = flags | TTM_PL_MASK_CACHING; |
||
| 706 | r = ttm_buffer_object_validate(&robj->tobj, |
||
| 707 | robj->tobj.proposed_placement, |
||
| 708 | true, false); |
||
| 709 | if (unlikely(r)) { |
||
| 710 | radeon_object_list_unreserve(head); |
||
| 711 | DRM_ERROR("radeon: failed to validate.\n"); |
||
| 712 | return r; |
||
| 713 | } |
||
| 714 | radeon_object_gpu_addr(robj); |
||
| 715 | } |
||
| 716 | lobj->gpu_offset = robj->gpu_addr; |
||
| 717 | if (fence) { |
||
| 718 | old_fence = (struct radeon_fence *)robj->tobj.sync_obj; |
||
| 719 | robj->tobj.sync_obj = radeon_fence_ref(fence); |
||
| 720 | robj->tobj.sync_obj_arg = NULL; |
||
| 721 | } |
||
| 722 | if (old_fence) { |
||
| 723 | radeon_fence_unref(&old_fence); |
||
| 724 | } |
||
| 725 | } |
||
| 726 | return 0; |
||
| 727 | } |
||
| 728 | |||
| 729 | void radeon_object_list_unvalidate(struct list_head *head) |
||
| 730 | { |
||
| 731 | struct radeon_object_list *lobj; |
||
| 732 | struct radeon_fence *old_fence = NULL; |
||
| 733 | struct list_head *i; |
||
| 734 | |||
| 735 | list_for_each(i, head) { |
||
| 736 | lobj = list_entry(i, struct radeon_object_list, list); |
||
| 737 | old_fence = (struct radeon_fence *)lobj->robj->tobj.sync_obj; |
||
| 738 | lobj->robj->tobj.sync_obj = NULL; |
||
| 739 | if (old_fence) { |
||
| 740 | radeon_fence_unref(&old_fence); |
||
| 741 | } |
||
| 742 | } |
||
| 743 | radeon_object_list_unreserve(head); |
||
| 744 | } |
||
| 745 | |||
| 746 | void radeon_object_list_clean(struct list_head *head) |
||
| 747 | { |
||
| 748 | radeon_object_list_unreserve(head); |
||
| 749 | } |
||
| 750 | |||
| 751 | int radeon_object_fbdev_mmap(struct radeon_object *robj, |
||
| 752 | struct vm_area_struct *vma) |
||
| 753 | { |
||
| 754 | return ttm_fbdev_mmap(vma, &robj->tobj); |
||
| 755 | } |
||
| 756 | |||
| 1128 | serge | 757 | #endif |
| 758 | |||
| 1120 | serge | 759 | unsigned long radeon_object_size(struct radeon_object *robj) |
| 760 | { |
||
| 761 | return robj->tobj.num_pages << PAGE_SHIFT; |
||
| 762 | } |
||
| 763 |