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| Rev | Author | Line No. | Line |
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| 1120 | serge | 1 | /* |
| 2 | * Copyright 2009 Jerome Glisse. |
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| 3 | * All Rights Reserved. |
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| 4 | * |
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| 5 | * Permission is hereby granted, free of charge, to any person obtaining a |
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| 6 | * copy of this software and associated documentation files (the |
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| 7 | * "Software"), to deal in the Software without restriction, including |
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| 8 | * without limitation the rights to use, copy, modify, merge, publish, |
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| 9 | * distribute, sub license, and/or sell copies of the Software, and to |
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| 10 | * permit persons to whom the Software is furnished to do so, subject to |
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| 11 | * the following conditions: |
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| 12 | * |
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| 13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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| 14 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| 15 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL |
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| 16 | * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, |
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| 17 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR |
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| 18 | * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE |
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| 19 | * USE OR OTHER DEALINGS IN THE SOFTWARE. |
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| 20 | * |
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| 21 | * The above copyright notice and this permission notice (including the |
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| 22 | * next paragraph) shall be included in all copies or substantial portions |
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| 23 | * of the Software. |
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| 24 | * |
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| 25 | */ |
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| 26 | /* |
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| 27 | * Authors: |
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| 28 | * Jerome Glisse |
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| 29 | * Thomas Hellstrom |
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| 30 | * Dave Airlie |
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| 31 | */ |
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| 1179 | serge | 32 | #include |
| 33 | #include |
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| 1120 | serge | 34 | #include "radeon_drm.h" |
| 35 | #include "radeon.h" |
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| 36 | #include |
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| 1126 | serge | 37 | #include "radeon_object.h" |
| 1120 | serge | 38 | |
| 39 | int radeon_gart_bind(struct radeon_device *rdev, unsigned offset, |
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| 40 | int pages, u32_t *pagelist); |
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| 41 | |||
| 42 | |||
| 43 | |||
| 44 | |||
| 45 | static struct drm_mm mm_gtt; |
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| 46 | static struct drm_mm mm_vram; |
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| 47 | |||
| 48 | |||
| 49 | int radeon_object_init(struct radeon_device *rdev) |
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| 50 | { |
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| 51 | int r = 0; |
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| 52 | |||
| 1182 | serge | 53 | ENTER(); |
| 1125 | serge | 54 | |
| 1313 | serge | 55 | r = drm_mm_init(&mm_vram, 0xC00000 >> PAGE_SHIFT, |
| 56 | ((rdev->mc.real_vram_size - 0xC00000) >> PAGE_SHIFT)); |
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| 1120 | serge | 57 | if (r) { |
| 58 | DRM_ERROR("Failed initializing VRAM heap.\n"); |
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| 59 | return r; |
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| 60 | }; |
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| 61 | |||
| 62 | r = drm_mm_init(&mm_gtt, 0, ((rdev->mc.gtt_size) >> PAGE_SHIFT)); |
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| 63 | if (r) { |
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| 64 | DRM_ERROR("Failed initializing GTT heap.\n"); |
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| 65 | return r; |
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| 66 | } |
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| 67 | |||
| 68 | return r; |
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| 69 | // return radeon_ttm_init(rdev); |
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| 70 | } |
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| 71 | |||
| 72 | static inline uint32_t radeon_object_flags_from_domain(uint32_t domain) |
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| 73 | { |
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| 74 | uint32_t flags = 0; |
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| 75 | if (domain & RADEON_GEM_DOMAIN_VRAM) { |
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| 76 | flags |= TTM_PL_FLAG_VRAM; |
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| 77 | } |
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| 78 | if (domain & RADEON_GEM_DOMAIN_GTT) { |
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| 79 | flags |= TTM_PL_FLAG_TT; |
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| 80 | } |
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| 81 | if (domain & RADEON_GEM_DOMAIN_CPU) { |
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| 82 | flags |= TTM_PL_FLAG_SYSTEM; |
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| 83 | } |
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| 84 | if (!flags) { |
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| 85 | flags |= TTM_PL_FLAG_SYSTEM; |
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| 86 | } |
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| 87 | return flags; |
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| 88 | } |
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| 89 | |||
| 90 | |||
| 91 | int radeon_object_create(struct radeon_device *rdev, |
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| 92 | struct drm_gem_object *gobj, |
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| 93 | unsigned long size, |
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| 94 | bool kernel, |
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| 95 | uint32_t domain, |
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| 96 | bool interruptible, |
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| 97 | struct radeon_object **robj_ptr) |
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| 98 | { |
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| 99 | struct radeon_object *robj; |
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| 100 | enum ttm_bo_type type; |
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| 101 | uint32_t flags; |
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| 102 | int r; |
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| 103 | |||
| 104 | if (kernel) { |
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| 105 | type = ttm_bo_type_kernel; |
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| 106 | } else { |
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| 107 | type = ttm_bo_type_device; |
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| 108 | } |
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| 109 | *robj_ptr = NULL; |
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| 110 | robj = kzalloc(sizeof(struct radeon_object), GFP_KERNEL); |
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| 111 | if (robj == NULL) { |
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| 112 | return -ENOMEM; |
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| 113 | } |
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| 114 | robj->rdev = rdev; |
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| 115 | // robj->gobj = gobj; |
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| 116 | INIT_LIST_HEAD(&robj->list); |
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| 117 | |||
| 118 | flags = radeon_object_flags_from_domain(domain); |
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| 119 | |||
| 120 | robj->flags = flags; |
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| 121 | |||
| 122 | if( flags & TTM_PL_FLAG_VRAM) |
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| 123 | { |
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| 124 | size_t num_pages; |
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| 125 | |||
| 126 | struct drm_mm_node *vm_node; |
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| 127 | |||
| 128 | num_pages = (size + PAGE_SIZE - 1) >> PAGE_SHIFT; |
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| 129 | |||
| 130 | if (num_pages == 0) { |
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| 1182 | serge | 131 | dbgprintf("Illegal buffer object size.\n"); |
| 1120 | serge | 132 | return -EINVAL; |
| 133 | } |
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| 134 | retry_pre_get: |
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| 135 | r = drm_mm_pre_get(&mm_vram); |
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| 136 | |||
| 137 | if (unlikely(r != 0)) |
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| 138 | return r; |
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| 139 | |||
| 140 | vm_node = drm_mm_search_free(&mm_vram, num_pages, 0, 0); |
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| 141 | |||
| 142 | if (unlikely(vm_node == NULL)) { |
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| 143 | r = -ENOMEM; |
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| 144 | return r; |
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| 145 | } |
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| 146 | |||
| 147 | robj->mm_node = drm_mm_get_block_atomic(vm_node, num_pages, 0); |
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| 148 | |||
| 149 | if (unlikely(robj->mm_node == NULL)) { |
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| 150 | goto retry_pre_get; |
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| 151 | } |
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| 152 | |||
| 153 | robj->vm_addr = ((uint32_t)robj->mm_node->start); |
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| 154 | |||
| 1268 | serge | 155 | // dbgprintf("alloc vram: base %x size %x\n", |
| 156 | // robj->vm_addr << PAGE_SHIFT, num_pages << PAGE_SHIFT); |
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| 1120 | serge | 157 | |
| 158 | }; |
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| 159 | |||
| 160 | if( flags & TTM_PL_FLAG_TT) |
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| 161 | { |
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| 162 | size_t num_pages; |
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| 163 | |||
| 164 | struct drm_mm_node *vm_node; |
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| 165 | |||
| 166 | num_pages = (size + PAGE_SIZE - 1) >> PAGE_SHIFT; |
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| 167 | |||
| 168 | if (num_pages == 0) { |
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| 1182 | serge | 169 | dbgprintf("Illegal buffer object size.\n"); |
| 1120 | serge | 170 | return -EINVAL; |
| 171 | } |
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| 172 | retry_pre_get1: |
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| 173 | r = drm_mm_pre_get(&mm_gtt); |
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| 174 | |||
| 175 | if (unlikely(r != 0)) |
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| 176 | return r; |
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| 177 | |||
| 178 | vm_node = drm_mm_search_free(&mm_gtt, num_pages, 0, 0); |
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| 179 | |||
| 180 | if (unlikely(vm_node == NULL)) { |
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| 181 | r = -ENOMEM; |
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| 182 | return r; |
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| 183 | } |
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| 184 | |||
| 185 | robj->mm_node = drm_mm_get_block_atomic(vm_node, num_pages, 0); |
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| 186 | |||
| 187 | if (unlikely(robj->mm_node == NULL)) { |
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| 188 | goto retry_pre_get1; |
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| 189 | } |
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| 190 | |||
| 191 | robj->vm_addr = ((uint32_t)robj->mm_node->start) ; |
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| 192 | |||
| 1268 | serge | 193 | // dbgprintf("alloc gtt: base %x size %x\n", |
| 194 | // robj->vm_addr << PAGE_SHIFT, num_pages << PAGE_SHIFT); |
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| 1120 | serge | 195 | }; |
| 196 | |||
| 197 | // r = ttm_buffer_object_init(&rdev->mman.bdev, &robj->tobj, size, type, flags, |
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| 198 | // 0, 0, false, NULL, size, |
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| 199 | // &radeon_ttm_object_object_destroy); |
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| 200 | if (unlikely(r != 0)) { |
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| 201 | /* ttm call radeon_ttm_object_object_destroy if error happen */ |
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| 202 | DRM_ERROR("Failed to allocate TTM object (%ld, 0x%08X, %u)\n", |
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| 203 | size, flags, 0); |
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| 204 | return r; |
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| 205 | } |
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| 206 | *robj_ptr = robj; |
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| 207 | // if (gobj) { |
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| 208 | // list_add_tail(&robj->list, &rdev->gem.objects); |
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| 209 | // } |
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| 210 | return 0; |
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| 211 | } |
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| 212 | |||
| 213 | #define page_tabs 0xFDC00000 |
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| 214 | |||
| 215 | int radeon_object_pin(struct radeon_object *robj, uint32_t domain, |
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| 216 | uint64_t *gpu_addr) |
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| 217 | { |
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| 218 | uint32_t flags; |
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| 219 | uint32_t tmp; |
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| 220 | int r = 0; |
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| 221 | |||
| 222 | // flags = radeon_object_flags_from_domain(domain); |
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| 223 | // spin_lock(&robj->tobj.lock); |
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| 224 | if (robj->pin_count) { |
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| 225 | robj->pin_count++; |
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| 226 | if (gpu_addr != NULL) { |
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| 227 | *gpu_addr = robj->gpu_addr; |
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| 228 | } |
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| 229 | // spin_unlock(&robj->tobj.lock); |
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| 230 | return 0; |
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| 231 | } |
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| 232 | // spin_unlock(&robj->tobj.lock); |
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| 233 | // r = radeon_object_reserve(robj, false); |
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| 234 | // if (unlikely(r != 0)) { |
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| 235 | // DRM_ERROR("radeon: failed to reserve object for pinning it.\n"); |
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| 236 | // return r; |
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| 237 | // } |
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| 238 | // tmp = robj->tobj.mem.placement; |
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| 239 | // ttm_flag_masked(&tmp, flags, TTM_PL_MASK_MEM); |
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| 240 | // robj->tobj.proposed_placement = tmp | TTM_PL_FLAG_NO_EVICT | TTM_PL_MASK_CACHING; |
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| 241 | // r = ttm_buffer_object_validate(&robj->tobj, |
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| 242 | // robj->tobj.proposed_placement, |
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| 243 | // false, false); |
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| 244 | |||
| 245 | robj->gpu_addr = ((u64)robj->vm_addr) << PAGE_SHIFT; |
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| 246 | |||
| 247 | if(robj->flags & TTM_PL_FLAG_VRAM) |
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| 248 | robj->gpu_addr += (u64)robj->rdev->mc.vram_location; |
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| 249 | else if (robj->flags & TTM_PL_FLAG_TT) |
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| 250 | { |
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| 251 | u32_t *pagelist; |
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| 252 | robj->kptr = KernelAlloc( robj->mm_node->size << PAGE_SHIFT ); |
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| 253 | dbgprintf("kernel alloc %x\n", robj->kptr ); |
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| 254 | |||
| 255 | pagelist = &((u32_t*)page_tabs)[(u32_t)robj->kptr >> 12]; |
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| 256 | dbgprintf("pagelist %x\n", pagelist); |
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| 257 | radeon_gart_bind(robj->rdev, robj->gpu_addr, |
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| 258 | robj->mm_node->size, pagelist); |
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| 259 | robj->gpu_addr += (u64)robj->rdev->mc.gtt_location; |
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| 260 | } |
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| 261 | else |
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| 262 | { |
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| 263 | DRM_ERROR("Unknown placement %d\n", robj->flags); |
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| 264 | robj->gpu_addr = 0xFFFFFFFFFFFFFFFFULL; |
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| 265 | r = -1; |
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| 266 | }; |
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| 267 | |||
| 268 | // flags & TTM_PL_FLAG_VRAM |
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| 269 | if (gpu_addr != NULL) { |
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| 270 | *gpu_addr = robj->gpu_addr; |
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| 271 | } |
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| 272 | robj->pin_count = 1; |
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| 273 | if (unlikely(r != 0)) { |
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| 274 | DRM_ERROR("radeon: failed to pin object.\n"); |
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| 275 | } |
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| 276 | |||
| 277 | return r; |
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| 278 | } |
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| 279 | |||
| 280 | int radeon_object_kmap(struct radeon_object *robj, void **ptr) |
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| 281 | { |
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| 282 | int r = 0; |
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| 283 | |||
| 284 | // spin_lock(&robj->tobj.lock); |
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| 285 | if (robj->kptr) { |
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| 286 | if (ptr) { |
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| 287 | *ptr = robj->kptr; |
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| 288 | } |
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| 289 | // spin_unlock(&robj->tobj.lock); |
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| 290 | return 0; |
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| 291 | } |
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| 292 | // spin_unlock(&robj->tobj.lock); |
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| 293 | |||
| 294 | if(robj->flags & TTM_PL_FLAG_VRAM) |
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| 295 | { |
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| 296 | robj->cpu_addr = robj->rdev->mc.aper_base + |
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| 297 | (robj->vm_addr << PAGE_SHIFT); |
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| 298 | robj->kptr = (void*)MapIoMem(robj->cpu_addr, |
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| 299 | robj->mm_node->size << 12, PG_SW); |
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| 300 | } |
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| 301 | else |
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| 302 | { |
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| 303 | return -1; |
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| 304 | } |
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| 305 | |||
| 306 | if (ptr) { |
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| 307 | *ptr = robj->kptr; |
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| 308 | } |
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| 309 | |||
| 310 | return 0; |
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| 311 | } |
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| 312 | |||
| 1182 | serge | 313 | void radeon_object_kunmap(struct radeon_object *robj) |
| 314 | { |
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| 315 | // spin_lock(&robj->tobj.lock); |
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| 316 | if (robj->kptr == NULL) { |
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| 317 | // spin_unlock(&robj->tobj.lock); |
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| 318 | return; |
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| 319 | } |
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| 1120 | serge | 320 | |
| 1182 | serge | 321 | if (robj->flags & TTM_PL_FLAG_VRAM) |
| 322 | { |
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| 323 | FreeKernelSpace(robj->kptr); |
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| 324 | robj->kptr = NULL; |
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| 325 | } |
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| 326 | // spin_unlock(&robj->tobj.lock); |
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| 327 | } |
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| 328 | |||
| 1120 | serge | 329 | |
| 330 | void radeon_object_unpin(struct radeon_object *robj) |
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| 331 | { |
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| 332 | uint32_t flags; |
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| 333 | int r; |
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| 334 | |||
| 335 | // spin_lock(&robj->tobj.lock); |
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| 336 | if (!robj->pin_count) { |
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| 337 | // spin_unlock(&robj->tobj.lock); |
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| 338 | printk(KERN_WARNING "Unpin not necessary for %p !\n", robj); |
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| 339 | return; |
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| 340 | } |
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| 341 | robj->pin_count--; |
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| 342 | if (robj->pin_count) { |
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| 343 | // spin_unlock(&robj->tobj.lock); |
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| 344 | return; |
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| 345 | } |
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| 346 | // spin_unlock(&robj->tobj.lock); |
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| 1313 | serge | 347 | |
| 348 | drm_mm_put_block(robj->mm_node); |
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| 349 | |||
| 350 | kfree(robj); |
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| 1120 | serge | 351 | } |
| 352 | |||
| 353 | |||
| 1313 | serge | 354 | #if 0 |
| 1120 | serge | 355 | |
| 356 | |||
| 357 | /* |
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| 358 | * To exclude mutual BO access we rely on bo_reserve exclusion, as all |
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| 359 | * function are calling it. |
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| 360 | */ |
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| 361 | |||
| 362 | static int radeon_object_reserve(struct radeon_object *robj, bool interruptible) |
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| 363 | { |
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| 364 | return ttm_bo_reserve(&robj->tobj, interruptible, false, false, 0); |
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| 365 | } |
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| 366 | |||
| 367 | static void radeon_object_unreserve(struct radeon_object *robj) |
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| 368 | { |
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| 369 | ttm_bo_unreserve(&robj->tobj); |
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| 370 | } |
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| 371 | |||
| 372 | static void radeon_ttm_object_object_destroy(struct ttm_buffer_object *tobj) |
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| 373 | { |
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| 374 | struct radeon_object *robj; |
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| 375 | |||
| 376 | robj = container_of(tobj, struct radeon_object, tobj); |
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| 377 | // list_del_init(&robj->list); |
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| 378 | kfree(robj); |
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| 379 | } |
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| 380 | |||
| 381 | static inline void radeon_object_gpu_addr(struct radeon_object *robj) |
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| 382 | { |
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| 383 | /* Default gpu address */ |
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| 384 | robj->gpu_addr = 0xFFFFFFFFFFFFFFFFULL; |
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| 385 | if (robj->tobj.mem.mm_node == NULL) { |
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| 386 | return; |
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| 387 | } |
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| 388 | robj->gpu_addr = ((u64)robj->tobj.mem.mm_node->start) << PAGE_SHIFT; |
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| 389 | switch (robj->tobj.mem.mem_type) { |
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| 390 | case TTM_PL_VRAM: |
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| 391 | robj->gpu_addr += (u64)robj->rdev->mc.vram_location; |
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| 392 | break; |
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| 393 | case TTM_PL_TT: |
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| 394 | robj->gpu_addr += (u64)robj->rdev->mc.gtt_location; |
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| 395 | break; |
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| 396 | default: |
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| 397 | DRM_ERROR("Unknown placement %d\n", robj->tobj.mem.mem_type); |
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| 398 | robj->gpu_addr = 0xFFFFFFFFFFFFFFFFULL; |
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| 399 | return; |
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| 400 | } |
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| 401 | } |
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| 402 | |||
| 403 | |||
| 404 | int radeon_object_create(struct radeon_device *rdev, |
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| 405 | struct drm_gem_object *gobj, |
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| 406 | unsigned long size, |
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| 407 | bool kernel, |
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| 408 | uint32_t domain, |
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| 409 | bool interruptible, |
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| 410 | struct radeon_object **robj_ptr) |
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| 411 | { |
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| 412 | struct radeon_object *robj; |
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| 413 | enum ttm_bo_type type; |
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| 414 | uint32_t flags; |
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| 415 | int r; |
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| 416 | |||
| 417 | // if (unlikely(rdev->mman.bdev.dev_mapping == NULL)) { |
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| 418 | // rdev->mman.bdev.dev_mapping = rdev->ddev->dev_mapping; |
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| 419 | // } |
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| 420 | if (kernel) { |
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| 421 | type = ttm_bo_type_kernel; |
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| 422 | } else { |
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| 423 | type = ttm_bo_type_device; |
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| 424 | } |
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| 425 | *robj_ptr = NULL; |
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| 426 | robj = kzalloc(sizeof(struct radeon_object), GFP_KERNEL); |
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| 427 | if (robj == NULL) { |
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| 428 | return -ENOMEM; |
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| 429 | } |
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| 430 | robj->rdev = rdev; |
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| 431 | robj->gobj = gobj; |
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| 432 | // INIT_LIST_HEAD(&robj->list); |
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| 433 | |||
| 434 | flags = radeon_object_flags_from_domain(domain); |
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| 435 | // r = ttm_buffer_object_init(&rdev->mman.bdev, &robj->tobj, size, type, flags, |
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| 436 | // 0, 0, false, NULL, size, |
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| 437 | // &radeon_ttm_object_object_destroy); |
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| 438 | if (unlikely(r != 0)) { |
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| 439 | /* ttm call radeon_ttm_object_object_destroy if error happen */ |
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| 440 | DRM_ERROR("Failed to allocate TTM object (%ld, 0x%08X, %u)\n", |
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| 441 | size, flags, 0); |
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| 442 | return r; |
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| 443 | } |
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| 444 | *robj_ptr = robj; |
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| 445 | // if (gobj) { |
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| 446 | // list_add_tail(&robj->list, &rdev->gem.objects); |
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| 447 | // } |
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| 448 | return 0; |
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| 449 | } |
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| 450 | |||
| 451 | int radeon_object_kmap(struct radeon_object *robj, void **ptr) |
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| 452 | { |
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| 453 | int r; |
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| 454 | |||
| 455 | // spin_lock(&robj->tobj.lock); |
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| 456 | if (robj->kptr) { |
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| 457 | if (ptr) { |
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| 458 | *ptr = robj->kptr; |
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| 459 | } |
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| 460 | // spin_unlock(&robj->tobj.lock); |
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| 461 | return 0; |
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| 462 | } |
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| 463 | // spin_unlock(&robj->tobj.lock); |
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| 464 | r = ttm_bo_kmap(&robj->tobj, 0, robj->tobj.num_pages, &robj->kmap); |
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| 465 | if (r) { |
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| 466 | return r; |
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| 467 | } |
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| 468 | // spin_lock(&robj->tobj.lock); |
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| 469 | robj->kptr = ttm_kmap_obj_virtual(&robj->kmap, &robj->is_iomem); |
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| 470 | // spin_unlock(&robj->tobj.lock); |
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| 471 | if (ptr) { |
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| 472 | *ptr = robj->kptr; |
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| 473 | } |
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| 474 | return 0; |
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| 475 | } |
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| 476 | |||
| 477 | void radeon_object_kunmap(struct radeon_object *robj) |
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| 478 | { |
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| 479 | // spin_lock(&robj->tobj.lock); |
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| 480 | if (robj->kptr == NULL) { |
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| 481 | // spin_unlock(&robj->tobj.lock); |
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| 482 | return; |
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| 483 | } |
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| 484 | robj->kptr = NULL; |
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| 485 | // spin_unlock(&robj->tobj.lock); |
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| 486 | ttm_bo_kunmap(&robj->kmap); |
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| 487 | } |
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| 488 | |||
| 489 | void radeon_object_unref(struct radeon_object **robj) |
||
| 490 | { |
||
| 491 | struct ttm_buffer_object *tobj; |
||
| 492 | |||
| 493 | if ((*robj) == NULL) { |
||
| 494 | return; |
||
| 495 | } |
||
| 496 | tobj = &((*robj)->tobj); |
||
| 497 | ttm_bo_unref(&tobj); |
||
| 498 | if (tobj == NULL) { |
||
| 499 | *robj = NULL; |
||
| 500 | } |
||
| 501 | } |
||
| 502 | |||
| 503 | int radeon_object_mmap(struct radeon_object *robj, uint64_t *offset) |
||
| 504 | { |
||
| 505 | *offset = robj->tobj.addr_space_offset; |
||
| 506 | return 0; |
||
| 507 | } |
||
| 508 | |||
| 509 | int radeon_object_pin(struct radeon_object *robj, uint32_t domain, |
||
| 510 | uint64_t *gpu_addr) |
||
| 511 | { |
||
| 512 | uint32_t flags; |
||
| 513 | uint32_t tmp; |
||
| 514 | int r; |
||
| 515 | |||
| 516 | flags = radeon_object_flags_from_domain(domain); |
||
| 517 | // spin_lock(&robj->tobj.lock); |
||
| 518 | if (robj->pin_count) { |
||
| 519 | robj->pin_count++; |
||
| 520 | if (gpu_addr != NULL) { |
||
| 521 | *gpu_addr = robj->gpu_addr; |
||
| 522 | } |
||
| 523 | // spin_unlock(&robj->tobj.lock); |
||
| 524 | return 0; |
||
| 525 | } |
||
| 526 | // spin_unlock(&robj->tobj.lock); |
||
| 527 | r = radeon_object_reserve(robj, false); |
||
| 528 | if (unlikely(r != 0)) { |
||
| 529 | DRM_ERROR("radeon: failed to reserve object for pinning it.\n"); |
||
| 530 | return r; |
||
| 531 | } |
||
| 532 | tmp = robj->tobj.mem.placement; |
||
| 533 | ttm_flag_masked(&tmp, flags, TTM_PL_MASK_MEM); |
||
| 534 | robj->tobj.proposed_placement = tmp | TTM_PL_FLAG_NO_EVICT | TTM_PL_MASK_CACHING; |
||
| 535 | r = ttm_buffer_object_validate(&robj->tobj, |
||
| 536 | robj->tobj.proposed_placement, |
||
| 537 | false, false); |
||
| 538 | radeon_object_gpu_addr(robj); |
||
| 539 | if (gpu_addr != NULL) { |
||
| 540 | *gpu_addr = robj->gpu_addr; |
||
| 541 | } |
||
| 542 | robj->pin_count = 1; |
||
| 543 | if (unlikely(r != 0)) { |
||
| 544 | DRM_ERROR("radeon: failed to pin object.\n"); |
||
| 545 | } |
||
| 546 | radeon_object_unreserve(robj); |
||
| 547 | return r; |
||
| 548 | } |
||
| 549 | |||
| 550 | void radeon_object_unpin(struct radeon_object *robj) |
||
| 551 | { |
||
| 552 | uint32_t flags; |
||
| 553 | int r; |
||
| 554 | |||
| 555 | // spin_lock(&robj->tobj.lock); |
||
| 556 | if (!robj->pin_count) { |
||
| 557 | // spin_unlock(&robj->tobj.lock); |
||
| 558 | printk(KERN_WARNING "Unpin not necessary for %p !\n", robj); |
||
| 559 | return; |
||
| 560 | } |
||
| 561 | robj->pin_count--; |
||
| 562 | if (robj->pin_count) { |
||
| 563 | // spin_unlock(&robj->tobj.lock); |
||
| 564 | return; |
||
| 565 | } |
||
| 566 | // spin_unlock(&robj->tobj.lock); |
||
| 567 | r = radeon_object_reserve(robj, false); |
||
| 568 | if (unlikely(r != 0)) { |
||
| 569 | DRM_ERROR("radeon: failed to reserve object for unpinning it.\n"); |
||
| 570 | return; |
||
| 571 | } |
||
| 572 | flags = robj->tobj.mem.placement; |
||
| 573 | robj->tobj.proposed_placement = flags & ~TTM_PL_FLAG_NO_EVICT; |
||
| 574 | r = ttm_buffer_object_validate(&robj->tobj, |
||
| 575 | robj->tobj.proposed_placement, |
||
| 576 | false, false); |
||
| 577 | if (unlikely(r != 0)) { |
||
| 578 | DRM_ERROR("radeon: failed to unpin buffer.\n"); |
||
| 579 | } |
||
| 580 | radeon_object_unreserve(robj); |
||
| 581 | } |
||
| 582 | |||
| 583 | int radeon_object_wait(struct radeon_object *robj) |
||
| 584 | { |
||
| 585 | int r = 0; |
||
| 586 | |||
| 587 | /* FIXME: should use block reservation instead */ |
||
| 588 | r = radeon_object_reserve(robj, true); |
||
| 589 | if (unlikely(r != 0)) { |
||
| 590 | DRM_ERROR("radeon: failed to reserve object for waiting.\n"); |
||
| 591 | return r; |
||
| 592 | } |
||
| 593 | // spin_lock(&robj->tobj.lock); |
||
| 594 | if (robj->tobj.sync_obj) { |
||
| 595 | r = ttm_bo_wait(&robj->tobj, true, false, false); |
||
| 596 | } |
||
| 597 | // spin_unlock(&robj->tobj.lock); |
||
| 598 | radeon_object_unreserve(robj); |
||
| 599 | return r; |
||
| 600 | } |
||
| 601 | |||
| 602 | int radeon_object_evict_vram(struct radeon_device *rdev) |
||
| 603 | { |
||
| 604 | if (rdev->flags & RADEON_IS_IGP) { |
||
| 605 | /* Useless to evict on IGP chips */ |
||
| 606 | return 0; |
||
| 607 | } |
||
| 608 | return ttm_bo_evict_mm(&rdev->mman.bdev, TTM_PL_VRAM); |
||
| 609 | } |
||
| 610 | |||
| 611 | void radeon_object_force_delete(struct radeon_device *rdev) |
||
| 612 | { |
||
| 613 | struct radeon_object *robj, *n; |
||
| 614 | struct drm_gem_object *gobj; |
||
| 615 | |||
| 616 | if (list_empty(&rdev->gem.objects)) { |
||
| 617 | return; |
||
| 618 | } |
||
| 619 | DRM_ERROR("Userspace still has active objects !\n"); |
||
| 620 | list_for_each_entry_safe(robj, n, &rdev->gem.objects, list) { |
||
| 621 | mutex_lock(&rdev->ddev->struct_mutex); |
||
| 622 | gobj = robj->gobj; |
||
| 623 | DRM_ERROR("Force free for (%p,%p,%lu,%lu)\n", |
||
| 624 | gobj, robj, (unsigned long)gobj->size, |
||
| 625 | *((unsigned long *)&gobj->refcount)); |
||
| 626 | list_del_init(&robj->list); |
||
| 627 | radeon_object_unref(&robj); |
||
| 628 | gobj->driver_private = NULL; |
||
| 629 | drm_gem_object_unreference(gobj); |
||
| 630 | mutex_unlock(&rdev->ddev->struct_mutex); |
||
| 631 | } |
||
| 632 | } |
||
| 633 | |||
| 634 | void radeon_object_fini(struct radeon_device *rdev) |
||
| 635 | { |
||
| 636 | radeon_ttm_fini(rdev); |
||
| 637 | } |
||
| 638 | |||
| 639 | void radeon_object_list_add_object(struct radeon_object_list *lobj, |
||
| 640 | struct list_head *head) |
||
| 641 | { |
||
| 642 | if (lobj->wdomain) { |
||
| 643 | list_add(&lobj->list, head); |
||
| 644 | } else { |
||
| 645 | list_add_tail(&lobj->list, head); |
||
| 646 | } |
||
| 647 | } |
||
| 648 | |||
| 649 | int radeon_object_list_reserve(struct list_head *head) |
||
| 650 | { |
||
| 651 | struct radeon_object_list *lobj; |
||
| 652 | struct list_head *i; |
||
| 653 | int r; |
||
| 654 | |||
| 655 | list_for_each(i, head) { |
||
| 656 | lobj = list_entry(i, struct radeon_object_list, list); |
||
| 657 | if (!lobj->robj->pin_count) { |
||
| 658 | r = radeon_object_reserve(lobj->robj, true); |
||
| 659 | if (unlikely(r != 0)) { |
||
| 660 | DRM_ERROR("radeon: failed to reserve object.\n"); |
||
| 661 | return r; |
||
| 662 | } |
||
| 663 | } else { |
||
| 664 | } |
||
| 665 | } |
||
| 666 | return 0; |
||
| 667 | } |
||
| 668 | |||
| 669 | void radeon_object_list_unreserve(struct list_head *head) |
||
| 670 | { |
||
| 671 | struct radeon_object_list *lobj; |
||
| 672 | struct list_head *i; |
||
| 673 | |||
| 674 | list_for_each(i, head) { |
||
| 675 | lobj = list_entry(i, struct radeon_object_list, list); |
||
| 676 | if (!lobj->robj->pin_count) { |
||
| 677 | radeon_object_unreserve(lobj->robj); |
||
| 678 | } else { |
||
| 679 | } |
||
| 680 | } |
||
| 681 | } |
||
| 682 | |||
| 683 | int radeon_object_list_validate(struct list_head *head, void *fence) |
||
| 684 | { |
||
| 685 | struct radeon_object_list *lobj; |
||
| 686 | struct radeon_object *robj; |
||
| 687 | struct radeon_fence *old_fence = NULL; |
||
| 688 | struct list_head *i; |
||
| 689 | uint32_t flags; |
||
| 690 | int r; |
||
| 691 | |||
| 692 | r = radeon_object_list_reserve(head); |
||
| 693 | if (unlikely(r != 0)) { |
||
| 694 | radeon_object_list_unreserve(head); |
||
| 695 | return r; |
||
| 696 | } |
||
| 697 | list_for_each(i, head) { |
||
| 698 | lobj = list_entry(i, struct radeon_object_list, list); |
||
| 699 | robj = lobj->robj; |
||
| 700 | if (lobj->wdomain) { |
||
| 701 | flags = radeon_object_flags_from_domain(lobj->wdomain); |
||
| 702 | flags |= TTM_PL_FLAG_TT; |
||
| 703 | } else { |
||
| 704 | flags = radeon_object_flags_from_domain(lobj->rdomain); |
||
| 705 | flags |= TTM_PL_FLAG_TT; |
||
| 706 | flags |= TTM_PL_FLAG_VRAM; |
||
| 707 | } |
||
| 708 | if (!robj->pin_count) { |
||
| 709 | robj->tobj.proposed_placement = flags | TTM_PL_MASK_CACHING; |
||
| 710 | r = ttm_buffer_object_validate(&robj->tobj, |
||
| 711 | robj->tobj.proposed_placement, |
||
| 712 | true, false); |
||
| 713 | if (unlikely(r)) { |
||
| 714 | radeon_object_list_unreserve(head); |
||
| 715 | DRM_ERROR("radeon: failed to validate.\n"); |
||
| 716 | return r; |
||
| 717 | } |
||
| 718 | radeon_object_gpu_addr(robj); |
||
| 719 | } |
||
| 720 | lobj->gpu_offset = robj->gpu_addr; |
||
| 721 | if (fence) { |
||
| 722 | old_fence = (struct radeon_fence *)robj->tobj.sync_obj; |
||
| 723 | robj->tobj.sync_obj = radeon_fence_ref(fence); |
||
| 724 | robj->tobj.sync_obj_arg = NULL; |
||
| 725 | } |
||
| 726 | if (old_fence) { |
||
| 727 | radeon_fence_unref(&old_fence); |
||
| 728 | } |
||
| 729 | } |
||
| 730 | return 0; |
||
| 731 | } |
||
| 732 | |||
| 733 | void radeon_object_list_unvalidate(struct list_head *head) |
||
| 734 | { |
||
| 735 | struct radeon_object_list *lobj; |
||
| 736 | struct radeon_fence *old_fence = NULL; |
||
| 737 | struct list_head *i; |
||
| 738 | |||
| 739 | list_for_each(i, head) { |
||
| 740 | lobj = list_entry(i, struct radeon_object_list, list); |
||
| 741 | old_fence = (struct radeon_fence *)lobj->robj->tobj.sync_obj; |
||
| 742 | lobj->robj->tobj.sync_obj = NULL; |
||
| 743 | if (old_fence) { |
||
| 744 | radeon_fence_unref(&old_fence); |
||
| 745 | } |
||
| 746 | } |
||
| 747 | radeon_object_list_unreserve(head); |
||
| 748 | } |
||
| 749 | |||
| 750 | void radeon_object_list_clean(struct list_head *head) |
||
| 751 | { |
||
| 752 | radeon_object_list_unreserve(head); |
||
| 753 | } |
||
| 754 | |||
| 755 | int radeon_object_fbdev_mmap(struct radeon_object *robj, |
||
| 756 | struct vm_area_struct *vma) |
||
| 757 | { |
||
| 758 | return ttm_fbdev_mmap(vma, &robj->tobj); |
||
| 759 | } |
||
| 760 | |||
| 1128 | serge | 761 | #endif |
| 762 | |||
| 1120 | serge | 763 | unsigned long radeon_object_size(struct radeon_object *robj) |
| 764 | { |
||
| 765 | return robj->tobj.num_pages << PAGE_SHIFT; |
||
| 766 | } |
||
| 767 |