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1117 | serge | 1 | /* |
2 | * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and |
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3 | * VA Linux Systems Inc., Fremont, California. |
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4 | * Copyright 2008 Red Hat Inc. |
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5 | * |
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6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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7 | * copy of this software and associated documentation files (the "Software"), |
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8 | * to deal in the Software without restriction, including without limitation |
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9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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10 | * and/or sell copies of the Software, and to permit persons to whom the |
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11 | * Software is furnished to do so, subject to the following conditions: |
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12 | * |
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13 | * The above copyright notice and this permission notice shall be included in |
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14 | * all copies or substantial portions of the Software. |
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15 | * |
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16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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22 | * OTHER DEALINGS IN THE SOFTWARE. |
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23 | * |
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24 | * Original Authors: |
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25 | * Kevin E. Martin, Rickard E. Faith, Alan Hourihane |
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26 | * |
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27 | * Kernel port Author: Dave Airlie |
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28 | */ |
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29 | |||
30 | #ifndef RADEON_MODE_H |
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31 | #define RADEON_MODE_H |
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32 | |||
2997 | Serge | 33 | #include |
34 | #include |
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35 | #include |
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36 | #include |
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37 | #include |
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1125 | serge | 38 | #include |
39 | #include |
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1117 | serge | 40 | |
1963 | serge | 41 | struct radeon_bo; |
1179 | serge | 42 | struct radeon_device; |
43 | |||
1117 | serge | 44 | #define to_radeon_crtc(x) container_of(x, struct radeon_crtc, base) |
45 | #define to_radeon_connector(x) container_of(x, struct radeon_connector, base) |
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46 | #define to_radeon_encoder(x) container_of(x, struct radeon_encoder, base) |
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47 | #define to_radeon_framebuffer(x) container_of(x, struct radeon_framebuffer, base) |
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48 | |||
5078 | serge | 49 | #define RADEON_MAX_HPD_PINS 7 |
50 | #define RADEON_MAX_CRTCS 6 |
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51 | #define RADEON_MAX_AFMT_BLOCKS 7 |
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52 | |||
1117 | serge | 53 | enum radeon_rmx_type { |
54 | RMX_OFF, |
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55 | RMX_FULL, |
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56 | RMX_CENTER, |
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57 | RMX_ASPECT |
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58 | }; |
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59 | |||
60 | enum radeon_tv_std { |
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61 | TV_STD_NTSC, |
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62 | TV_STD_PAL, |
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63 | TV_STD_PAL_M, |
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64 | TV_STD_PAL_60, |
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65 | TV_STD_NTSC_J, |
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66 | TV_STD_SCART_PAL, |
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67 | TV_STD_SECAM, |
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68 | TV_STD_PAL_CN, |
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1404 | serge | 69 | TV_STD_PAL_N, |
1117 | serge | 70 | }; |
71 | |||
1963 | serge | 72 | enum radeon_underscan_type { |
73 | UNDERSCAN_OFF, |
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74 | UNDERSCAN_ON, |
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75 | UNDERSCAN_AUTO, |
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76 | }; |
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77 | |||
78 | enum radeon_hpd_id { |
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79 | RADEON_HPD_1 = 0, |
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80 | RADEON_HPD_2, |
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81 | RADEON_HPD_3, |
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82 | RADEON_HPD_4, |
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83 | RADEON_HPD_5, |
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84 | RADEON_HPD_6, |
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85 | RADEON_HPD_NONE = 0xff, |
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86 | }; |
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87 | |||
88 | #define RADEON_MAX_I2C_BUS 16 |
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89 | |||
1321 | serge | 90 | /* radeon gpio-based i2c |
91 | * 1. "mask" reg and bits |
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92 | * grabs the gpio pins for software use |
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93 | * 0=not held 1=held |
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94 | * 2. "a" reg and bits |
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95 | * output pin value |
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96 | * 0=low 1=high |
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97 | * 3. "en" reg and bits |
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98 | * sets the pin direction |
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99 | * 0=input 1=output |
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100 | * 4. "y" reg and bits |
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101 | * input pin value |
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102 | * 0=low 1=high |
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103 | */ |
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1117 | serge | 104 | struct radeon_i2c_bus_rec { |
105 | bool valid; |
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1321 | serge | 106 | /* id used by atom */ |
107 | uint8_t i2c_id; |
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1430 | serge | 108 | /* id used by atom */ |
1963 | serge | 109 | enum radeon_hpd_id hpd; |
1321 | serge | 110 | /* can be used with hw i2c engine */ |
111 | bool hw_capable; |
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112 | /* uses multi-media i2c engine */ |
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113 | bool mm_i2c; |
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114 | /* regs and bits */ |
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1117 | serge | 115 | uint32_t mask_clk_reg; |
116 | uint32_t mask_data_reg; |
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117 | uint32_t a_clk_reg; |
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118 | uint32_t a_data_reg; |
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1321 | serge | 119 | uint32_t en_clk_reg; |
120 | uint32_t en_data_reg; |
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121 | uint32_t y_clk_reg; |
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122 | uint32_t y_data_reg; |
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1117 | serge | 123 | uint32_t mask_clk_mask; |
124 | uint32_t mask_data_mask; |
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125 | uint32_t a_clk_mask; |
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126 | uint32_t a_data_mask; |
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1321 | serge | 127 | uint32_t en_clk_mask; |
128 | uint32_t en_data_mask; |
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129 | uint32_t y_clk_mask; |
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130 | uint32_t y_data_mask; |
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1117 | serge | 131 | }; |
132 | |||
133 | struct radeon_tmds_pll { |
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134 | uint32_t freq; |
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135 | uint32_t value; |
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136 | }; |
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137 | |||
138 | #define RADEON_MAX_BIOS_CONNECTOR 16 |
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139 | |||
1430 | serge | 140 | /* pll flags */ |
1117 | serge | 141 | #define RADEON_PLL_USE_BIOS_DIVS (1 << 0) |
142 | #define RADEON_PLL_NO_ODD_POST_DIV (1 << 1) |
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143 | #define RADEON_PLL_USE_REF_DIV (1 << 2) |
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144 | #define RADEON_PLL_LEGACY (1 << 3) |
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145 | #define RADEON_PLL_PREFER_LOW_REF_DIV (1 << 4) |
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146 | #define RADEON_PLL_PREFER_HIGH_REF_DIV (1 << 5) |
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147 | #define RADEON_PLL_PREFER_LOW_FB_DIV (1 << 6) |
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148 | #define RADEON_PLL_PREFER_HIGH_FB_DIV (1 << 7) |
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149 | #define RADEON_PLL_PREFER_LOW_POST_DIV (1 << 8) |
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150 | #define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9) |
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151 | #define RADEON_PLL_USE_FRAC_FB_DIV (1 << 10) |
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1179 | serge | 152 | #define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11) |
1404 | serge | 153 | #define RADEON_PLL_USE_POST_DIV (1 << 12) |
1963 | serge | 154 | #define RADEON_PLL_IS_LCD (1 << 13) |
155 | #define RADEON_PLL_PREFER_MINM_OVER_MAXP (1 << 14) |
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1117 | serge | 156 | |
157 | struct radeon_pll { |
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1404 | serge | 158 | /* reference frequency */ |
159 | uint32_t reference_freq; |
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160 | |||
161 | /* fixed dividers */ |
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162 | uint32_t reference_div; |
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163 | uint32_t post_div; |
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164 | |||
165 | /* pll in/out limits */ |
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1117 | serge | 166 | uint32_t pll_in_min; |
167 | uint32_t pll_in_max; |
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168 | uint32_t pll_out_min; |
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169 | uint32_t pll_out_max; |
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1963 | serge | 170 | uint32_t lcd_pll_out_min; |
171 | uint32_t lcd_pll_out_max; |
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1404 | serge | 172 | uint32_t best_vco; |
1117 | serge | 173 | |
1404 | serge | 174 | /* divider limits */ |
1117 | serge | 175 | uint32_t min_ref_div; |
176 | uint32_t max_ref_div; |
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177 | uint32_t min_post_div; |
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178 | uint32_t max_post_div; |
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179 | uint32_t min_feedback_div; |
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180 | uint32_t max_feedback_div; |
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181 | uint32_t min_frac_feedback_div; |
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182 | uint32_t max_frac_feedback_div; |
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1404 | serge | 183 | |
184 | /* flags for the current clock */ |
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185 | uint32_t flags; |
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186 | |||
187 | /* pll id */ |
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188 | uint32_t id; |
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1117 | serge | 189 | }; |
190 | |||
191 | struct radeon_i2c_chan { |
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1321 | serge | 192 | struct i2c_adapter adapter; |
1117 | serge | 193 | struct drm_device *dev; |
1963 | serge | 194 | struct i2c_algo_bit_data bit; |
1117 | serge | 195 | struct radeon_i2c_bus_rec rec; |
5078 | serge | 196 | struct drm_dp_aux aux; |
197 | bool has_aux; |
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198 | struct mutex mutex; |
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1117 | serge | 199 | }; |
200 | |||
201 | /* mostly for macs, but really any system without connector tables */ |
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202 | enum radeon_connector_table { |
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1963 | serge | 203 | CT_NONE = 0, |
1117 | serge | 204 | CT_GENERIC, |
205 | CT_IBOOK, |
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206 | CT_POWERBOOK_EXTERNAL, |
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207 | CT_POWERBOOK_INTERNAL, |
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208 | CT_POWERBOOK_VGA, |
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209 | CT_MINI_EXTERNAL, |
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210 | CT_MINI_INTERNAL, |
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211 | CT_IMAC_G5_ISIGHT, |
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212 | CT_EMAC, |
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1963 | serge | 213 | CT_RN50_POWER, |
214 | CT_MAC_X800, |
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215 | CT_MAC_G5_9600, |
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3192 | Serge | 216 | CT_SAM440EP, |
217 | CT_MAC_G4_SILVER |
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1117 | serge | 218 | }; |
219 | |||
1321 | serge | 220 | enum radeon_dvo_chip { |
221 | DVO_SIL164, |
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222 | DVO_SIL1178, |
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223 | }; |
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224 | |||
1963 | serge | 225 | struct radeon_fbdev; |
226 | |||
2997 | Serge | 227 | struct radeon_afmt { |
228 | bool enabled; |
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229 | int offset; |
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230 | bool last_buffer_filled_status; |
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231 | int id; |
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5078 | serge | 232 | struct r600_audio_pin *pin; |
2997 | Serge | 233 | }; |
234 | |||
1117 | serge | 235 | struct radeon_mode_info { |
236 | struct atom_context *atom_context; |
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1268 | serge | 237 | struct card_info *atom_card_info; |
1117 | serge | 238 | enum radeon_connector_table connector_table; |
239 | bool mode_config_initialized; |
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5078 | serge | 240 | struct radeon_crtc *crtcs[RADEON_MAX_CRTCS]; |
241 | struct radeon_afmt *afmt[RADEON_MAX_AFMT_BLOCKS]; |
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1179 | serge | 242 | /* DVI-I properties */ |
243 | struct drm_property *coherent_mode_property; |
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244 | /* DAC enable load detect */ |
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245 | struct drm_property *load_detect_property; |
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1963 | serge | 246 | /* TV standard */ |
1179 | serge | 247 | struct drm_property *tv_std_property; |
248 | /* legacy TMDS PLL detect */ |
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249 | struct drm_property *tmds_pll_property; |
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1963 | serge | 250 | /* underscan */ |
251 | struct drm_property *underscan_property; |
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252 | struct drm_property *underscan_hborder_property; |
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253 | struct drm_property *underscan_vborder_property; |
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5078 | serge | 254 | /* audio */ |
255 | struct drm_property *audio_property; |
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256 | /* FMT dithering */ |
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257 | struct drm_property *dither_property; |
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1430 | serge | 258 | /* hardcoded DFP edid from BIOS */ |
259 | struct edid *bios_hardcoded_edid; |
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1963 | serge | 260 | int bios_hardcoded_edid_size; |
261 | |||
262 | /* pointer to fbdev info structure */ |
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263 | struct radeon_fbdev *rfbdev; |
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2997 | Serge | 264 | /* firmware flags */ |
265 | u16 firmware_flags; |
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266 | /* pointer to backlight encoder */ |
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267 | struct radeon_encoder *bl_encoder; |
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1117 | serge | 268 | }; |
269 | |||
2997 | Serge | 270 | #define RADEON_MAX_BL_LEVEL 0xFF |
271 | |||
272 | #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) |
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273 | |||
274 | struct radeon_backlight_privdata { |
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275 | struct radeon_encoder *encoder; |
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276 | uint8_t negative; |
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277 | }; |
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278 | |||
279 | #endif |
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280 | |||
1179 | serge | 281 | #define MAX_H_CODE_TIMING_LEN 32 |
282 | #define MAX_V_CODE_TIMING_LEN 32 |
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283 | |||
284 | /* need to store these as reading |
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285 | back code tables is excessive */ |
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286 | struct radeon_tv_regs { |
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287 | uint32_t tv_uv_adr; |
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288 | uint32_t timing_cntl; |
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289 | uint32_t hrestart; |
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290 | uint32_t vrestart; |
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291 | uint32_t frestart; |
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292 | uint16_t h_code_timing[MAX_H_CODE_TIMING_LEN]; |
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293 | uint16_t v_code_timing[MAX_V_CODE_TIMING_LEN]; |
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294 | }; |
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295 | |||
2997 | Serge | 296 | struct radeon_atom_ss { |
297 | uint16_t percentage; |
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5078 | serge | 298 | uint16_t percentage_divider; |
2997 | Serge | 299 | uint8_t type; |
300 | uint16_t step; |
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301 | uint8_t delay; |
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302 | uint8_t range; |
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303 | uint8_t refdiv; |
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304 | /* asic_ss */ |
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305 | uint16_t rate; |
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306 | uint16_t amount; |
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307 | }; |
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308 | |||
5078 | serge | 309 | enum radeon_flip_status { |
310 | RADEON_FLIP_NONE, |
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311 | RADEON_FLIP_PENDING, |
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312 | RADEON_FLIP_SUBMITTED |
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313 | }; |
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314 | |||
1117 | serge | 315 | struct radeon_crtc { |
1123 | serge | 316 | struct drm_crtc base; |
1117 | serge | 317 | int crtc_id; |
1179 | serge | 318 | u16 lut_r[256], lut_g[256], lut_b[256]; |
1117 | serge | 319 | bool enabled; |
320 | bool can_tile; |
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321 | uint32_t crtc_offset; |
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1321 | serge | 322 | struct drm_gem_object *cursor_bo; |
1117 | serge | 323 | uint64_t cursor_addr; |
324 | int cursor_width; |
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325 | int cursor_height; |
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5078 | serge | 326 | int max_cursor_width; |
327 | int max_cursor_height; |
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1179 | serge | 328 | uint32_t legacy_display_base_addr; |
329 | uint32_t legacy_cursor_offset; |
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330 | enum radeon_rmx_type rmx_type; |
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1963 | serge | 331 | u8 h_border; |
332 | u8 v_border; |
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1179 | serge | 333 | fixed20_12 vsc; |
334 | fixed20_12 hsc; |
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1268 | serge | 335 | struct drm_display_mode native_mode; |
1430 | serge | 336 | int pll_id; |
5078 | serge | 337 | /* page flipping */ |
338 | struct workqueue_struct *flip_queue; |
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339 | struct radeon_flip_work *flip_work; |
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340 | enum radeon_flip_status flip_status; |
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2997 | Serge | 341 | /* pll sharing */ |
342 | struct radeon_atom_ss ss; |
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343 | bool ss_enabled; |
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344 | u32 adjusted_clock; |
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345 | int bpc; |
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346 | u32 pll_reference_div; |
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347 | u32 pll_post_div; |
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348 | u32 pll_flags; |
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349 | struct drm_encoder *encoder; |
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350 | struct drm_connector *connector; |
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5078 | serge | 351 | /* for dpm */ |
352 | u32 line_time; |
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353 | u32 wm_low; |
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354 | u32 wm_high; |
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355 | struct drm_display_mode hw_mode; |
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1117 | serge | 356 | }; |
357 | |||
358 | struct radeon_encoder_primary_dac { |
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359 | /* legacy primary dac */ |
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360 | uint32_t ps2_pdac_adj; |
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361 | }; |
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362 | |||
363 | struct radeon_encoder_lvds { |
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364 | /* legacy lvds */ |
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365 | uint16_t panel_vcc_delay; |
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366 | uint8_t panel_pwr_delay; |
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367 | uint8_t panel_digon_delay; |
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368 | uint8_t panel_blon_delay; |
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369 | uint16_t panel_ref_divider; |
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370 | uint8_t panel_post_divider; |
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371 | uint16_t panel_fb_divider; |
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372 | bool use_bios_dividers; |
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373 | uint32_t lvds_gen_cntl; |
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374 | /* panel mode */ |
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1268 | serge | 375 | struct drm_display_mode native_mode; |
1963 | serge | 376 | struct backlight_device *bl_dev; |
377 | int dpms_mode; |
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378 | uint8_t backlight_level; |
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1117 | serge | 379 | }; |
380 | |||
381 | struct radeon_encoder_tv_dac { |
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382 | /* legacy tv dac */ |
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383 | uint32_t ps2_tvdac_adj; |
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384 | uint32_t ntsc_tvdac_adj; |
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385 | uint32_t pal_tvdac_adj; |
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386 | |||
1179 | serge | 387 | int h_pos; |
388 | int v_pos; |
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389 | int h_size; |
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390 | int supported_tv_stds; |
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391 | bool tv_on; |
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1117 | serge | 392 | enum radeon_tv_std tv_std; |
1179 | serge | 393 | struct radeon_tv_regs tv; |
1117 | serge | 394 | }; |
395 | |||
396 | struct radeon_encoder_int_tmds { |
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397 | /* legacy int tmds */ |
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398 | struct radeon_tmds_pll tmds_pll[4]; |
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399 | }; |
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400 | |||
1321 | serge | 401 | struct radeon_encoder_ext_tmds { |
402 | /* tmds over dvo */ |
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403 | struct radeon_i2c_chan *i2c_bus; |
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404 | uint8_t slave_addr; |
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405 | enum radeon_dvo_chip dvo_chip; |
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406 | }; |
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407 | |||
1268 | serge | 408 | /* spread spectrum */ |
1117 | serge | 409 | struct radeon_encoder_atom_dig { |
1963 | serge | 410 | bool linkb; |
1117 | serge | 411 | /* atom dig */ |
412 | bool coherent_mode; |
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1963 | serge | 413 | int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB, etc. */ |
414 | /* atom lvds/edp */ |
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415 | uint32_t lcd_misc; |
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1117 | serge | 416 | uint16_t panel_pwr_delay; |
1963 | serge | 417 | uint32_t lcd_ss_id; |
1117 | serge | 418 | /* panel mode */ |
1268 | serge | 419 | struct drm_display_mode native_mode; |
1963 | serge | 420 | struct backlight_device *bl_dev; |
421 | int dpms_mode; |
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422 | uint8_t backlight_level; |
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2997 | Serge | 423 | int panel_mode; |
424 | struct radeon_afmt *afmt; |
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1117 | serge | 425 | }; |
426 | |||
1179 | serge | 427 | struct radeon_encoder_atom_dac { |
428 | enum radeon_tv_std tv_std; |
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429 | }; |
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430 | |||
1117 | serge | 431 | struct radeon_encoder { |
432 | struct drm_encoder base; |
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1963 | serge | 433 | uint32_t encoder_enum; |
1117 | serge | 434 | uint32_t encoder_id; |
435 | uint32_t devices; |
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1179 | serge | 436 | uint32_t active_device; |
1117 | serge | 437 | uint32_t flags; |
438 | uint32_t pixel_clock; |
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439 | enum radeon_rmx_type rmx_type; |
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1963 | serge | 440 | enum radeon_underscan_type underscan_type; |
441 | uint32_t underscan_hborder; |
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442 | uint32_t underscan_vborder; |
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1268 | serge | 443 | struct drm_display_mode native_mode; |
1117 | serge | 444 | void *enc_priv; |
1963 | serge | 445 | int audio_polling_active; |
446 | bool is_ext_encoder; |
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447 | u16 caps; |
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1117 | serge | 448 | }; |
449 | |||
450 | struct radeon_connector_atom_dig { |
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451 | uint32_t igp_lane_info; |
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1321 | serge | 452 | /* displayport */ |
3192 | Serge | 453 | u8 dpcd[DP_RECEIVER_CAP_SIZE]; |
1321 | serge | 454 | u8 dp_sink_type; |
455 | int dp_clock; |
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456 | int dp_lane_count; |
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1963 | serge | 457 | bool edp_on; |
1117 | serge | 458 | }; |
459 | |||
1321 | serge | 460 | struct radeon_gpio_rec { |
461 | bool valid; |
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462 | u8 id; |
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463 | u32 reg; |
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464 | u32 mask; |
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465 | }; |
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466 | |||
467 | struct radeon_hpd { |
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468 | enum radeon_hpd_id hpd; |
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469 | u8 plugged_state; |
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470 | struct radeon_gpio_rec gpio; |
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471 | }; |
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472 | |||
1963 | serge | 473 | struct radeon_router { |
474 | u32 router_id; |
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475 | struct radeon_i2c_bus_rec i2c_info; |
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476 | u8 i2c_addr; |
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477 | /* i2c mux */ |
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478 | bool ddc_valid; |
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479 | u8 ddc_mux_type; |
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480 | u8 ddc_mux_control_pin; |
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481 | u8 ddc_mux_state; |
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482 | /* clock/data mux */ |
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483 | bool cd_valid; |
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484 | u8 cd_mux_type; |
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485 | u8 cd_mux_control_pin; |
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486 | u8 cd_mux_state; |
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487 | }; |
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488 | |||
5078 | serge | 489 | enum radeon_connector_audio { |
490 | RADEON_AUDIO_DISABLE = 0, |
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491 | RADEON_AUDIO_ENABLE = 1, |
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492 | RADEON_AUDIO_AUTO = 2 |
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493 | }; |
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494 | |||
495 | enum radeon_connector_dither { |
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496 | RADEON_FMT_DITHER_DISABLE = 0, |
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497 | RADEON_FMT_DITHER_ENABLE = 1, |
||
498 | }; |
||
499 | |||
1117 | serge | 500 | struct radeon_connector { |
501 | struct drm_connector base; |
||
502 | uint32_t connector_id; |
||
503 | uint32_t devices; |
||
504 | struct radeon_i2c_chan *ddc_bus; |
||
1963 | serge | 505 | /* some systems have an hdmi and vga port with a shared ddc line */ |
1268 | serge | 506 | bool shared_ddc; |
1179 | serge | 507 | bool use_digital; |
508 | /* we need to mind the EDID between detect |
||
509 | and get modes due to analog/digital/tvencoder */ |
||
510 | struct edid *edid; |
||
1117 | serge | 511 | void *con_priv; |
1179 | serge | 512 | bool dac_load_detect; |
2997 | Serge | 513 | bool detected_by_load; /* if the connection status was determined by load */ |
1268 | serge | 514 | uint16_t connector_object_id; |
1321 | serge | 515 | struct radeon_hpd hpd; |
1963 | serge | 516 | struct radeon_router router; |
517 | struct radeon_i2c_chan *router_bus; |
||
5078 | serge | 518 | enum radeon_connector_audio audio; |
519 | enum radeon_connector_dither dither; |
||
520 | int pixelclock_for_modeset; |
||
1117 | serge | 521 | }; |
522 | |||
523 | struct radeon_framebuffer { |
||
1123 | serge | 524 | struct drm_framebuffer base; |
525 | struct drm_gem_object *obj; |
||
1117 | serge | 526 | }; |
527 | |||
2997 | Serge | 528 | #define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \ |
529 | ((em) == ATOM_ENCODER_MODE_DP_MST)) |
||
1963 | serge | 530 | |
3764 | Serge | 531 | struct atom_clock_dividers { |
532 | u32 post_div; |
||
533 | union { |
||
534 | struct { |
||
535 | #ifdef __BIG_ENDIAN |
||
536 | u32 reserved : 6; |
||
537 | u32 whole_fb_div : 12; |
||
538 | u32 frac_fb_div : 14; |
||
539 | #else |
||
540 | u32 frac_fb_div : 14; |
||
541 | u32 whole_fb_div : 12; |
||
542 | u32 reserved : 6; |
||
543 | #endif |
||
544 | }; |
||
545 | u32 fb_div; |
||
546 | }; |
||
547 | u32 ref_div; |
||
548 | bool enable_post_div; |
||
549 | bool enable_dithen; |
||
550 | u32 vco_mode; |
||
551 | u32 real_clock; |
||
5078 | serge | 552 | /* added for CI */ |
553 | u32 post_divider; |
||
554 | u32 flags; |
||
3764 | Serge | 555 | }; |
556 | |||
5078 | serge | 557 | struct atom_mpll_param { |
558 | union { |
||
559 | struct { |
||
560 | #ifdef __BIG_ENDIAN |
||
561 | u32 reserved : 8; |
||
562 | u32 clkfrac : 12; |
||
563 | u32 clkf : 12; |
||
564 | #else |
||
565 | u32 clkf : 12; |
||
566 | u32 clkfrac : 12; |
||
567 | u32 reserved : 8; |
||
568 | #endif |
||
569 | }; |
||
570 | u32 fb_div; |
||
571 | }; |
||
572 | u32 post_div; |
||
573 | u32 bwcntl; |
||
574 | u32 dll_speed; |
||
575 | u32 vco_mode; |
||
576 | u32 yclk_sel; |
||
577 | u32 qdr; |
||
578 | u32 half_rate; |
||
579 | }; |
||
580 | |||
581 | #define MEM_TYPE_GDDR5 0x50 |
||
582 | #define MEM_TYPE_GDDR4 0x40 |
||
583 | #define MEM_TYPE_GDDR3 0x30 |
||
584 | #define MEM_TYPE_DDR2 0x20 |
||
585 | #define MEM_TYPE_GDDR1 0x10 |
||
586 | #define MEM_TYPE_DDR3 0xb0 |
||
587 | #define MEM_TYPE_MASK 0xf0 |
||
588 | |||
589 | struct atom_memory_info { |
||
590 | u8 mem_vendor; |
||
591 | u8 mem_type; |
||
592 | }; |
||
593 | |||
594 | #define MAX_AC_TIMING_ENTRIES 16 |
||
595 | |||
596 | struct atom_memory_clock_range_table |
||
597 | { |
||
598 | u8 num_entries; |
||
599 | u8 rsv[3]; |
||
600 | u32 mclk[MAX_AC_TIMING_ENTRIES]; |
||
601 | }; |
||
602 | |||
603 | #define VBIOS_MC_REGISTER_ARRAY_SIZE 32 |
||
604 | #define VBIOS_MAX_AC_TIMING_ENTRIES 20 |
||
605 | |||
606 | struct atom_mc_reg_entry { |
||
607 | u32 mclk_max; |
||
608 | u32 mc_data[VBIOS_MC_REGISTER_ARRAY_SIZE]; |
||
609 | }; |
||
610 | |||
611 | struct atom_mc_register_address { |
||
612 | u16 s1; |
||
613 | u8 pre_reg_data; |
||
614 | }; |
||
615 | |||
616 | struct atom_mc_reg_table { |
||
617 | u8 last; |
||
618 | u8 num_entries; |
||
619 | struct atom_mc_reg_entry mc_reg_table_entry[VBIOS_MAX_AC_TIMING_ENTRIES]; |
||
620 | struct atom_mc_register_address mc_reg_address[VBIOS_MC_REGISTER_ARRAY_SIZE]; |
||
621 | }; |
||
622 | |||
623 | #define MAX_VOLTAGE_ENTRIES 32 |
||
624 | |||
625 | struct atom_voltage_table_entry |
||
626 | { |
||
627 | u16 value; |
||
628 | u32 smio_low; |
||
629 | }; |
||
630 | |||
631 | struct atom_voltage_table |
||
632 | { |
||
633 | u32 count; |
||
634 | u32 mask_low; |
||
635 | u32 phase_delay; |
||
636 | struct atom_voltage_table_entry entries[MAX_VOLTAGE_ENTRIES]; |
||
637 | }; |
||
638 | |||
639 | |||
640 | extern void |
||
641 | radeon_add_atom_connector(struct drm_device *dev, |
||
642 | uint32_t connector_id, |
||
643 | uint32_t supported_device, |
||
644 | int connector_type, |
||
645 | struct radeon_i2c_bus_rec *i2c_bus, |
||
646 | uint32_t igp_lane_info, |
||
647 | uint16_t connector_object_id, |
||
648 | struct radeon_hpd *hpd, |
||
649 | struct radeon_router *router); |
||
650 | extern void |
||
651 | radeon_add_legacy_connector(struct drm_device *dev, |
||
652 | uint32_t connector_id, |
||
653 | uint32_t supported_device, |
||
654 | int connector_type, |
||
655 | struct radeon_i2c_bus_rec *i2c_bus, |
||
656 | uint16_t connector_object_id, |
||
657 | struct radeon_hpd *hpd); |
||
658 | extern uint32_t |
||
659 | radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device, |
||
660 | uint8_t dac); |
||
661 | extern void radeon_link_encoder_connector(struct drm_device *dev); |
||
662 | |||
1404 | serge | 663 | extern enum radeon_tv_std |
664 | radeon_combios_get_tv_info(struct radeon_device *rdev); |
||
665 | extern enum radeon_tv_std |
||
666 | radeon_atombios_get_tv_info(struct radeon_device *rdev); |
||
5078 | serge | 667 | extern void radeon_atombios_get_default_voltages(struct radeon_device *rdev, |
668 | u16 *vddc, u16 *vddci, u16 *mvdd); |
||
1404 | serge | 669 | |
5078 | serge | 670 | extern void |
671 | radeon_combios_connected_scratch_regs(struct drm_connector *connector, |
||
672 | struct drm_encoder *encoder, |
||
673 | bool connected); |
||
674 | extern void |
||
675 | radeon_atombios_connected_scratch_regs(struct drm_connector *connector, |
||
676 | struct drm_encoder *encoder, |
||
677 | bool connected); |
||
678 | |||
1963 | serge | 679 | extern struct drm_connector * |
680 | radeon_get_connector_for_encoder(struct drm_encoder *encoder); |
||
2997 | Serge | 681 | extern struct drm_connector * |
682 | radeon_get_connector_for_encoder_init(struct drm_encoder *encoder); |
||
683 | extern bool radeon_dig_monitor_is_duallink(struct drm_encoder *encoder, |
||
684 | u32 pixel_clock); |
||
1963 | serge | 685 | |
2997 | Serge | 686 | extern u16 radeon_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder); |
687 | extern u16 radeon_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector); |
||
1963 | serge | 688 | extern bool radeon_connector_is_dp12_capable(struct drm_connector *connector); |
2997 | Serge | 689 | extern int radeon_get_monitor_bpc(struct drm_connector *connector); |
1963 | serge | 690 | |
5078 | serge | 691 | extern struct edid *radeon_connector_edid(struct drm_connector *connector); |
692 | |||
1321 | serge | 693 | extern void radeon_connector_hotplug(struct drm_connector *connector); |
1963 | serge | 694 | extern int radeon_dp_mode_valid_helper(struct drm_connector *connector, |
1321 | serge | 695 | struct drm_display_mode *mode); |
696 | extern void radeon_dp_set_link_config(struct drm_connector *connector, |
||
2997 | Serge | 697 | const struct drm_display_mode *mode); |
1963 | serge | 698 | extern void radeon_dp_link_train(struct drm_encoder *encoder, |
1321 | serge | 699 | struct drm_connector *connector); |
2997 | Serge | 700 | extern bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector); |
1321 | serge | 701 | extern u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector); |
702 | extern bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector); |
||
2997 | Serge | 703 | extern int radeon_dp_get_panel_mode(struct drm_encoder *encoder, |
704 | struct drm_connector *connector); |
||
5078 | serge | 705 | extern void radeon_dp_set_rx_power_state(struct drm_connector *connector, |
706 | u8 power_state); |
||
707 | extern void radeon_dp_aux_init(struct radeon_connector *radeon_connector); |
||
1963 | serge | 708 | extern void atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode); |
709 | extern void radeon_atom_encoder_init(struct radeon_device *rdev); |
||
2997 | Serge | 710 | extern void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev); |
1321 | serge | 711 | extern void atombios_dig_transmitter_setup(struct drm_encoder *encoder, |
712 | int action, uint8_t lane_num, |
||
713 | uint8_t lane_set); |
||
1986 | serge | 714 | extern void radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder); |
2997 | Serge | 715 | extern struct drm_encoder *radeon_get_external_encoder(struct drm_encoder *encoder); |
5078 | serge | 716 | void radeon_atom_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le); |
1321 | serge | 717 | |
1963 | serge | 718 | extern void radeon_i2c_init(struct radeon_device *rdev); |
719 | extern void radeon_i2c_fini(struct radeon_device *rdev); |
||
720 | extern void radeon_combios_i2c_init(struct radeon_device *rdev); |
||
721 | extern void radeon_atombios_i2c_init(struct radeon_device *rdev); |
||
722 | extern void radeon_i2c_add(struct radeon_device *rdev, |
||
723 | struct radeon_i2c_bus_rec *rec, |
||
724 | const char *name); |
||
725 | extern struct radeon_i2c_chan *radeon_i2c_lookup(struct radeon_device *rdev, |
||
726 | struct radeon_i2c_bus_rec *i2c_bus); |
||
1117 | serge | 727 | extern struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev, |
728 | struct radeon_i2c_bus_rec *rec, |
||
729 | const char *name); |
||
730 | extern void radeon_i2c_destroy(struct radeon_i2c_chan *i2c); |
||
1430 | serge | 731 | extern void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus, |
1321 | serge | 732 | u8 slave_addr, |
733 | u8 addr, |
||
734 | u8 *val); |
||
1430 | serge | 735 | extern void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c, |
1321 | serge | 736 | u8 slave_addr, |
737 | u8 addr, |
||
738 | u8 val); |
||
1963 | serge | 739 | extern void radeon_router_select_ddc_port(struct radeon_connector *radeon_connector); |
740 | extern void radeon_router_select_cd_port(struct radeon_connector *radeon_connector); |
||
3192 | Serge | 741 | extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector, bool use_aux); |
1117 | serge | 742 | |
1123 | serge | 743 | extern struct drm_encoder *radeon_best_encoder(struct drm_connector *connector); |
1117 | serge | 744 | |
1963 | serge | 745 | extern bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev, |
746 | struct radeon_atom_ss *ss, |
||
747 | int id); |
||
748 | extern bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev, |
||
749 | struct radeon_atom_ss *ss, |
||
750 | int id, u32 clock); |
||
751 | |||
752 | extern void radeon_compute_pll_legacy(struct radeon_pll *pll, |
||
1117 | serge | 753 | uint64_t freq, |
754 | uint32_t *dot_clock_p, |
||
755 | uint32_t *fb_div_p, |
||
756 | uint32_t *frac_fb_div_p, |
||
757 | uint32_t *ref_div_p, |
||
1404 | serge | 758 | uint32_t *post_div_p); |
1117 | serge | 759 | |
1963 | serge | 760 | extern void radeon_compute_pll_avivo(struct radeon_pll *pll, |
761 | u32 freq, |
||
762 | u32 *dot_clock_p, |
||
763 | u32 *fb_div_p, |
||
764 | u32 *frac_fb_div_p, |
||
765 | u32 *ref_div_p, |
||
766 | u32 *post_div_p); |
||
767 | |||
1321 | serge | 768 | extern void radeon_setup_encoder_clones(struct drm_device *dev); |
769 | |||
1117 | serge | 770 | struct drm_encoder *radeon_encoder_legacy_lvds_add(struct drm_device *dev, int bios_index); |
771 | struct drm_encoder *radeon_encoder_legacy_primary_dac_add(struct drm_device *dev, int bios_index, int with_tv); |
||
772 | struct drm_encoder *radeon_encoder_legacy_tv_dac_add(struct drm_device *dev, int bios_index, int with_tv); |
||
773 | struct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, int bios_index); |
||
774 | struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, int bios_index); |
||
1963 | serge | 775 | extern void atombios_dvo_setup(struct drm_encoder *encoder, int action); |
1321 | serge | 776 | extern void atombios_digital_setup(struct drm_encoder *encoder, int action); |
1117 | serge | 777 | extern int atombios_get_encoder_mode(struct drm_encoder *encoder); |
1963 | serge | 778 | extern bool atombios_set_edp_panel_power(struct drm_connector *connector, int action); |
1179 | serge | 779 | extern void radeon_encoder_set_active_device(struct drm_encoder *encoder); |
1117 | serge | 780 | |
781 | extern void radeon_crtc_load_lut(struct drm_crtc *crtc); |
||
782 | extern int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y, |
||
783 | struct drm_framebuffer *old_fb); |
||
1963 | serge | 784 | extern int atombios_crtc_set_base_atomic(struct drm_crtc *crtc, |
785 | struct drm_framebuffer *fb, |
||
786 | int x, int y, |
||
787 | enum mode_set_atomic state); |
||
1117 | serge | 788 | extern int atombios_crtc_mode_set(struct drm_crtc *crtc, |
789 | struct drm_display_mode *mode, |
||
790 | struct drm_display_mode *adjusted_mode, |
||
791 | int x, int y, |
||
792 | struct drm_framebuffer *old_fb); |
||
793 | extern void atombios_crtc_dpms(struct drm_crtc *crtc, int mode); |
||
794 | |||
795 | extern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y, |
||
796 | struct drm_framebuffer *old_fb); |
||
1963 | serge | 797 | extern int radeon_crtc_set_base_atomic(struct drm_crtc *crtc, |
798 | struct drm_framebuffer *fb, |
||
799 | int x, int y, |
||
800 | enum mode_set_atomic state); |
||
801 | extern int radeon_crtc_do_set_base(struct drm_crtc *crtc, |
||
802 | struct drm_framebuffer *fb, |
||
803 | int x, int y, int atomic); |
||
1117 | serge | 804 | extern int radeon_crtc_cursor_set(struct drm_crtc *crtc, |
805 | struct drm_file *file_priv, |
||
806 | uint32_t handle, |
||
807 | uint32_t width, |
||
808 | uint32_t height); |
||
809 | extern int radeon_crtc_cursor_move(struct drm_crtc *crtc, |
||
810 | int x, int y); |
||
811 | |||
1963 | serge | 812 | extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc, |
5078 | serge | 813 | unsigned int flags, |
814 | int *vpos, int *hpos, void *stime, |
||
815 | void *etime); |
||
1963 | serge | 816 | |
1430 | serge | 817 | extern bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev); |
818 | extern struct edid * |
||
1963 | serge | 819 | radeon_bios_get_hardcoded_edid(struct radeon_device *rdev); |
1117 | serge | 820 | extern bool radeon_atom_get_clock_info(struct drm_device *dev); |
821 | extern bool radeon_combios_get_clock_info(struct drm_device *dev); |
||
822 | extern struct radeon_encoder_atom_dig * |
||
823 | radeon_atombios_get_lvds_info(struct radeon_encoder *encoder); |
||
1321 | serge | 824 | extern bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder, |
1179 | serge | 825 | struct radeon_encoder_int_tmds *tmds); |
1321 | serge | 826 | extern bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder, |
1179 | serge | 827 | struct radeon_encoder_int_tmds *tmds); |
1321 | serge | 828 | extern bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder, |
1179 | serge | 829 | struct radeon_encoder_int_tmds *tmds); |
1321 | serge | 830 | extern bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder, |
831 | struct radeon_encoder_ext_tmds *tmds); |
||
832 | extern bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder, |
||
833 | struct radeon_encoder_ext_tmds *tmds); |
||
1117 | serge | 834 | extern struct radeon_encoder_primary_dac * |
835 | radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder); |
||
836 | extern struct radeon_encoder_tv_dac * |
||
837 | radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder); |
||
838 | extern struct radeon_encoder_lvds * |
||
839 | radeon_combios_get_lvds_info(struct radeon_encoder *encoder); |
||
840 | extern void radeon_combios_get_ext_tmds_info(struct radeon_encoder *encoder); |
||
841 | extern struct radeon_encoder_tv_dac * |
||
842 | radeon_combios_get_tv_dac_info(struct radeon_encoder *encoder); |
||
843 | extern struct radeon_encoder_primary_dac * |
||
844 | radeon_combios_get_primary_dac_info(struct radeon_encoder *encoder); |
||
1321 | serge | 845 | extern bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder); |
846 | extern void radeon_external_tmds_setup(struct drm_encoder *encoder); |
||
1117 | serge | 847 | extern void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock); |
848 | extern void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev); |
||
849 | extern void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock); |
||
850 | extern void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev); |
||
1179 | serge | 851 | extern void radeon_save_bios_scratch_regs(struct radeon_device *rdev); |
852 | extern void radeon_restore_bios_scratch_regs(struct radeon_device *rdev); |
||
1117 | serge | 853 | extern void |
854 | radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc); |
||
855 | extern void |
||
856 | radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on); |
||
857 | extern void |
||
858 | radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc); |
||
859 | extern void |
||
860 | radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on); |
||
861 | extern void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, |
||
862 | u16 blue, int regno); |
||
1221 | serge | 863 | extern void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, |
864 | u16 *blue, int regno); |
||
2997 | Serge | 865 | int radeon_framebuffer_init(struct drm_device *dev, |
1963 | serge | 866 | struct radeon_framebuffer *rfb, |
2997 | Serge | 867 | struct drm_mode_fb_cmd2 *mode_cmd, |
1117 | serge | 868 | struct drm_gem_object *obj); |
869 | |||
870 | int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb); |
||
871 | bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev); |
||
872 | bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev); |
||
873 | void radeon_atombios_init_crtc(struct drm_device *dev, |
||
874 | struct radeon_crtc *radeon_crtc); |
||
875 | void radeon_legacy_init_crtc(struct drm_device *dev, |
||
876 | struct radeon_crtc *radeon_crtc); |
||
877 | |||
878 | void radeon_get_clock_info(struct drm_device *dev); |
||
879 | |||
880 | extern bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev); |
||
881 | extern bool radeon_get_atom_connector_info_from_supported_devices_table(struct drm_device *dev); |
||
882 | |||
883 | void radeon_enc_destroy(struct drm_encoder *encoder); |
||
884 | void radeon_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj); |
||
885 | void radeon_combios_asic_init(struct drm_device *dev); |
||
1179 | serge | 886 | bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc, |
2997 | Serge | 887 | const struct drm_display_mode *mode, |
1179 | serge | 888 | struct drm_display_mode *adjusted_mode); |
1963 | serge | 889 | void radeon_panel_mode_fixup(struct drm_encoder *encoder, |
890 | struct drm_display_mode *adjusted_mode); |
||
1179 | serge | 891 | void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc); |
1123 | serge | 892 | |
1179 | serge | 893 | /* legacy tv */ |
894 | void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder, |
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895 | uint32_t *h_total_disp, uint32_t *h_sync_strt_wid, |
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896 | uint32_t *v_total_disp, uint32_t *v_sync_strt_wid); |
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897 | void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder, |
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898 | uint32_t *htotal_cntl, uint32_t *ppll_ref_div, |
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899 | uint32_t *ppll_div_3, uint32_t *pixclks_cntl); |
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900 | void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder, |
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901 | uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div, |
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902 | uint32_t *p2pll_div_0, uint32_t *pixclks_cntl); |
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903 | void radeon_legacy_tv_mode_set(struct drm_encoder *encoder, |
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904 | struct drm_display_mode *mode, |
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905 | struct drm_display_mode *adjusted_mode); |
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1963 | serge | 906 | |
5078 | serge | 907 | /* fmt blocks */ |
908 | void avivo_program_fmt(struct drm_encoder *encoder); |
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909 | void dce3_program_fmt(struct drm_encoder *encoder); |
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910 | void dce4_program_fmt(struct drm_encoder *encoder); |
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911 | void dce8_program_fmt(struct drm_encoder *encoder); |
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912 | |||
1963 | serge | 913 | /* fbdev layer */ |
914 | int radeon_fbdev_init(struct radeon_device *rdev); |
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915 | void radeon_fbdev_fini(struct radeon_device *rdev); |
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916 | void radeon_fbdev_set_suspend(struct radeon_device *rdev, int state); |
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917 | int radeon_fbdev_total_size(struct radeon_device *rdev); |
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918 | bool radeon_fbdev_robj_is_fb(struct radeon_device *rdev, struct radeon_bo *robj); |
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919 | |||
920 | void radeon_fb_output_poll_changed(struct radeon_device *rdev); |
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921 | |||
5078 | serge | 922 | void radeon_crtc_handle_vblank(struct radeon_device *rdev, int crtc_id); |
1963 | serge | 923 | void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id); |
924 | |||
925 | int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp, bool tiled); |
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1117 | serge | 926 | #endif><>><>><>><>><>><>><>><>><>><>><>><>><>><>><> |