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1117 | serge | 1 | /* |
2 | * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and |
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3 | * VA Linux Systems Inc., Fremont, California. |
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4 | * Copyright 2008 Red Hat Inc. |
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5 | * |
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6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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7 | * copy of this software and associated documentation files (the "Software"), |
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8 | * to deal in the Software without restriction, including without limitation |
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9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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10 | * and/or sell copies of the Software, and to permit persons to whom the |
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11 | * Software is furnished to do so, subject to the following conditions: |
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12 | * |
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13 | * The above copyright notice and this permission notice shall be included in |
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14 | * all copies or substantial portions of the Software. |
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15 | * |
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16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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22 | * OTHER DEALINGS IN THE SOFTWARE. |
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23 | * |
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24 | * Original Authors: |
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25 | * Kevin E. Martin, Rickard E. Faith, Alan Hourihane |
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26 | * |
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27 | * Kernel port Author: Dave Airlie |
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28 | */ |
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29 | |||
30 | #ifndef RADEON_MODE_H |
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31 | #define RADEON_MODE_H |
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32 | |||
2997 | Serge | 33 | #include |
34 | #include |
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35 | #include |
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36 | #include |
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37 | #include |
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1125 | serge | 38 | #include |
39 | #include |
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1117 | serge | 40 | |
1963 | serge | 41 | struct radeon_bo; |
1179 | serge | 42 | struct radeon_device; |
43 | |||
1117 | serge | 44 | #define to_radeon_crtc(x) container_of(x, struct radeon_crtc, base) |
45 | #define to_radeon_connector(x) container_of(x, struct radeon_connector, base) |
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46 | #define to_radeon_encoder(x) container_of(x, struct radeon_encoder, base) |
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47 | #define to_radeon_framebuffer(x) container_of(x, struct radeon_framebuffer, base) |
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48 | |||
49 | enum radeon_rmx_type { |
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50 | RMX_OFF, |
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51 | RMX_FULL, |
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52 | RMX_CENTER, |
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53 | RMX_ASPECT |
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54 | }; |
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55 | |||
56 | enum radeon_tv_std { |
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57 | TV_STD_NTSC, |
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58 | TV_STD_PAL, |
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59 | TV_STD_PAL_M, |
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60 | TV_STD_PAL_60, |
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61 | TV_STD_NTSC_J, |
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62 | TV_STD_SCART_PAL, |
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63 | TV_STD_SECAM, |
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64 | TV_STD_PAL_CN, |
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1404 | serge | 65 | TV_STD_PAL_N, |
1117 | serge | 66 | }; |
67 | |||
1963 | serge | 68 | enum radeon_underscan_type { |
69 | UNDERSCAN_OFF, |
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70 | UNDERSCAN_ON, |
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71 | UNDERSCAN_AUTO, |
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72 | }; |
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73 | |||
74 | enum radeon_hpd_id { |
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75 | RADEON_HPD_1 = 0, |
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76 | RADEON_HPD_2, |
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77 | RADEON_HPD_3, |
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78 | RADEON_HPD_4, |
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79 | RADEON_HPD_5, |
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80 | RADEON_HPD_6, |
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81 | RADEON_HPD_NONE = 0xff, |
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82 | }; |
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83 | |||
84 | #define RADEON_MAX_I2C_BUS 16 |
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85 | |||
1321 | serge | 86 | /* radeon gpio-based i2c |
87 | * 1. "mask" reg and bits |
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88 | * grabs the gpio pins for software use |
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89 | * 0=not held 1=held |
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90 | * 2. "a" reg and bits |
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91 | * output pin value |
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92 | * 0=low 1=high |
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93 | * 3. "en" reg and bits |
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94 | * sets the pin direction |
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95 | * 0=input 1=output |
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96 | * 4. "y" reg and bits |
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97 | * input pin value |
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98 | * 0=low 1=high |
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99 | */ |
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1117 | serge | 100 | struct radeon_i2c_bus_rec { |
101 | bool valid; |
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1321 | serge | 102 | /* id used by atom */ |
103 | uint8_t i2c_id; |
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1430 | serge | 104 | /* id used by atom */ |
1963 | serge | 105 | enum radeon_hpd_id hpd; |
1321 | serge | 106 | /* can be used with hw i2c engine */ |
107 | bool hw_capable; |
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108 | /* uses multi-media i2c engine */ |
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109 | bool mm_i2c; |
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110 | /* regs and bits */ |
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1117 | serge | 111 | uint32_t mask_clk_reg; |
112 | uint32_t mask_data_reg; |
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113 | uint32_t a_clk_reg; |
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114 | uint32_t a_data_reg; |
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1321 | serge | 115 | uint32_t en_clk_reg; |
116 | uint32_t en_data_reg; |
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117 | uint32_t y_clk_reg; |
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118 | uint32_t y_data_reg; |
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1117 | serge | 119 | uint32_t mask_clk_mask; |
120 | uint32_t mask_data_mask; |
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121 | uint32_t a_clk_mask; |
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122 | uint32_t a_data_mask; |
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1321 | serge | 123 | uint32_t en_clk_mask; |
124 | uint32_t en_data_mask; |
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125 | uint32_t y_clk_mask; |
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126 | uint32_t y_data_mask; |
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1117 | serge | 127 | }; |
128 | |||
129 | struct radeon_tmds_pll { |
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130 | uint32_t freq; |
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131 | uint32_t value; |
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132 | }; |
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133 | |||
134 | #define RADEON_MAX_BIOS_CONNECTOR 16 |
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135 | |||
1430 | serge | 136 | /* pll flags */ |
1117 | serge | 137 | #define RADEON_PLL_USE_BIOS_DIVS (1 << 0) |
138 | #define RADEON_PLL_NO_ODD_POST_DIV (1 << 1) |
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139 | #define RADEON_PLL_USE_REF_DIV (1 << 2) |
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140 | #define RADEON_PLL_LEGACY (1 << 3) |
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141 | #define RADEON_PLL_PREFER_LOW_REF_DIV (1 << 4) |
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142 | #define RADEON_PLL_PREFER_HIGH_REF_DIV (1 << 5) |
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143 | #define RADEON_PLL_PREFER_LOW_FB_DIV (1 << 6) |
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144 | #define RADEON_PLL_PREFER_HIGH_FB_DIV (1 << 7) |
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145 | #define RADEON_PLL_PREFER_LOW_POST_DIV (1 << 8) |
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146 | #define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9) |
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147 | #define RADEON_PLL_USE_FRAC_FB_DIV (1 << 10) |
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1179 | serge | 148 | #define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11) |
1404 | serge | 149 | #define RADEON_PLL_USE_POST_DIV (1 << 12) |
1963 | serge | 150 | #define RADEON_PLL_IS_LCD (1 << 13) |
151 | #define RADEON_PLL_PREFER_MINM_OVER_MAXP (1 << 14) |
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1117 | serge | 152 | |
153 | struct radeon_pll { |
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1404 | serge | 154 | /* reference frequency */ |
155 | uint32_t reference_freq; |
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156 | |||
157 | /* fixed dividers */ |
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158 | uint32_t reference_div; |
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159 | uint32_t post_div; |
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160 | |||
161 | /* pll in/out limits */ |
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1117 | serge | 162 | uint32_t pll_in_min; |
163 | uint32_t pll_in_max; |
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164 | uint32_t pll_out_min; |
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165 | uint32_t pll_out_max; |
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1963 | serge | 166 | uint32_t lcd_pll_out_min; |
167 | uint32_t lcd_pll_out_max; |
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1404 | serge | 168 | uint32_t best_vco; |
1117 | serge | 169 | |
1404 | serge | 170 | /* divider limits */ |
1117 | serge | 171 | uint32_t min_ref_div; |
172 | uint32_t max_ref_div; |
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173 | uint32_t min_post_div; |
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174 | uint32_t max_post_div; |
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175 | uint32_t min_feedback_div; |
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176 | uint32_t max_feedback_div; |
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177 | uint32_t min_frac_feedback_div; |
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178 | uint32_t max_frac_feedback_div; |
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1404 | serge | 179 | |
180 | /* flags for the current clock */ |
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181 | uint32_t flags; |
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182 | |||
183 | /* pll id */ |
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184 | uint32_t id; |
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1117 | serge | 185 | }; |
186 | |||
187 | struct radeon_i2c_chan { |
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1321 | serge | 188 | struct i2c_adapter adapter; |
1117 | serge | 189 | struct drm_device *dev; |
1321 | serge | 190 | union { |
1963 | serge | 191 | struct i2c_algo_bit_data bit; |
1321 | serge | 192 | struct i2c_algo_dp_aux_data dp; |
193 | } algo; |
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1117 | serge | 194 | struct radeon_i2c_bus_rec rec; |
195 | }; |
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196 | |||
197 | /* mostly for macs, but really any system without connector tables */ |
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198 | enum radeon_connector_table { |
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1963 | serge | 199 | CT_NONE = 0, |
1117 | serge | 200 | CT_GENERIC, |
201 | CT_IBOOK, |
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202 | CT_POWERBOOK_EXTERNAL, |
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203 | CT_POWERBOOK_INTERNAL, |
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204 | CT_POWERBOOK_VGA, |
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205 | CT_MINI_EXTERNAL, |
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206 | CT_MINI_INTERNAL, |
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207 | CT_IMAC_G5_ISIGHT, |
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208 | CT_EMAC, |
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1963 | serge | 209 | CT_RN50_POWER, |
210 | CT_MAC_X800, |
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211 | CT_MAC_G5_9600, |
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3192 | Serge | 212 | CT_SAM440EP, |
213 | CT_MAC_G4_SILVER |
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1117 | serge | 214 | }; |
215 | |||
1321 | serge | 216 | enum radeon_dvo_chip { |
217 | DVO_SIL164, |
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218 | DVO_SIL1178, |
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219 | }; |
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220 | |||
1963 | serge | 221 | struct radeon_fbdev; |
222 | |||
2997 | Serge | 223 | struct radeon_afmt { |
224 | bool enabled; |
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225 | int offset; |
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226 | bool last_buffer_filled_status; |
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227 | int id; |
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228 | }; |
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229 | |||
1117 | serge | 230 | struct radeon_mode_info { |
231 | struct atom_context *atom_context; |
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1268 | serge | 232 | struct card_info *atom_card_info; |
1117 | serge | 233 | enum radeon_connector_table connector_table; |
234 | bool mode_config_initialized; |
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1430 | serge | 235 | struct radeon_crtc *crtcs[6]; |
2997 | Serge | 236 | struct radeon_afmt *afmt[6]; |
1179 | serge | 237 | /* DVI-I properties */ |
238 | struct drm_property *coherent_mode_property; |
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239 | /* DAC enable load detect */ |
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240 | struct drm_property *load_detect_property; |
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1963 | serge | 241 | /* TV standard */ |
1179 | serge | 242 | struct drm_property *tv_std_property; |
243 | /* legacy TMDS PLL detect */ |
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244 | struct drm_property *tmds_pll_property; |
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1963 | serge | 245 | /* underscan */ |
246 | struct drm_property *underscan_property; |
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247 | struct drm_property *underscan_hborder_property; |
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248 | struct drm_property *underscan_vborder_property; |
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1430 | serge | 249 | /* hardcoded DFP edid from BIOS */ |
250 | struct edid *bios_hardcoded_edid; |
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1963 | serge | 251 | int bios_hardcoded_edid_size; |
252 | |||
253 | /* pointer to fbdev info structure */ |
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254 | struct radeon_fbdev *rfbdev; |
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2997 | Serge | 255 | /* firmware flags */ |
256 | u16 firmware_flags; |
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257 | /* pointer to backlight encoder */ |
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258 | struct radeon_encoder *bl_encoder; |
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1117 | serge | 259 | }; |
260 | |||
2997 | Serge | 261 | #define RADEON_MAX_BL_LEVEL 0xFF |
262 | |||
263 | #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) |
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264 | |||
265 | struct radeon_backlight_privdata { |
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266 | struct radeon_encoder *encoder; |
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267 | uint8_t negative; |
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268 | }; |
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269 | |||
270 | #endif |
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271 | |||
1179 | serge | 272 | #define MAX_H_CODE_TIMING_LEN 32 |
273 | #define MAX_V_CODE_TIMING_LEN 32 |
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274 | |||
275 | /* need to store these as reading |
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276 | back code tables is excessive */ |
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277 | struct radeon_tv_regs { |
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278 | uint32_t tv_uv_adr; |
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279 | uint32_t timing_cntl; |
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280 | uint32_t hrestart; |
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281 | uint32_t vrestart; |
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282 | uint32_t frestart; |
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283 | uint16_t h_code_timing[MAX_H_CODE_TIMING_LEN]; |
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284 | uint16_t v_code_timing[MAX_V_CODE_TIMING_LEN]; |
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285 | }; |
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286 | |||
2997 | Serge | 287 | struct radeon_atom_ss { |
288 | uint16_t percentage; |
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289 | uint8_t type; |
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290 | uint16_t step; |
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291 | uint8_t delay; |
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292 | uint8_t range; |
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293 | uint8_t refdiv; |
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294 | /* asic_ss */ |
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295 | uint16_t rate; |
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296 | uint16_t amount; |
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297 | }; |
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298 | |||
1117 | serge | 299 | struct radeon_crtc { |
1123 | serge | 300 | struct drm_crtc base; |
1117 | serge | 301 | int crtc_id; |
1179 | serge | 302 | u16 lut_r[256], lut_g[256], lut_b[256]; |
1117 | serge | 303 | bool enabled; |
304 | bool can_tile; |
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305 | uint32_t crtc_offset; |
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1321 | serge | 306 | struct drm_gem_object *cursor_bo; |
1117 | serge | 307 | uint64_t cursor_addr; |
308 | int cursor_width; |
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309 | int cursor_height; |
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1179 | serge | 310 | uint32_t legacy_display_base_addr; |
311 | uint32_t legacy_cursor_offset; |
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312 | enum radeon_rmx_type rmx_type; |
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1963 | serge | 313 | u8 h_border; |
314 | u8 v_border; |
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1179 | serge | 315 | fixed20_12 vsc; |
316 | fixed20_12 hsc; |
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1268 | serge | 317 | struct drm_display_mode native_mode; |
1430 | serge | 318 | int pll_id; |
2160 | serge | 319 | int deferred_flip_completion; |
2997 | Serge | 320 | /* pll sharing */ |
321 | struct radeon_atom_ss ss; |
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322 | bool ss_enabled; |
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323 | u32 adjusted_clock; |
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324 | int bpc; |
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325 | u32 pll_reference_div; |
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326 | u32 pll_post_div; |
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327 | u32 pll_flags; |
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328 | struct drm_encoder *encoder; |
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329 | struct drm_connector *connector; |
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1117 | serge | 330 | }; |
331 | |||
332 | struct radeon_encoder_primary_dac { |
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333 | /* legacy primary dac */ |
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334 | uint32_t ps2_pdac_adj; |
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335 | }; |
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336 | |||
337 | struct radeon_encoder_lvds { |
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338 | /* legacy lvds */ |
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339 | uint16_t panel_vcc_delay; |
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340 | uint8_t panel_pwr_delay; |
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341 | uint8_t panel_digon_delay; |
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342 | uint8_t panel_blon_delay; |
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343 | uint16_t panel_ref_divider; |
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344 | uint8_t panel_post_divider; |
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345 | uint16_t panel_fb_divider; |
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346 | bool use_bios_dividers; |
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347 | uint32_t lvds_gen_cntl; |
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348 | /* panel mode */ |
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1268 | serge | 349 | struct drm_display_mode native_mode; |
1963 | serge | 350 | struct backlight_device *bl_dev; |
351 | int dpms_mode; |
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352 | uint8_t backlight_level; |
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1117 | serge | 353 | }; |
354 | |||
355 | struct radeon_encoder_tv_dac { |
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356 | /* legacy tv dac */ |
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357 | uint32_t ps2_tvdac_adj; |
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358 | uint32_t ntsc_tvdac_adj; |
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359 | uint32_t pal_tvdac_adj; |
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360 | |||
1179 | serge | 361 | int h_pos; |
362 | int v_pos; |
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363 | int h_size; |
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364 | int supported_tv_stds; |
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365 | bool tv_on; |
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1117 | serge | 366 | enum radeon_tv_std tv_std; |
1179 | serge | 367 | struct radeon_tv_regs tv; |
1117 | serge | 368 | }; |
369 | |||
370 | struct radeon_encoder_int_tmds { |
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371 | /* legacy int tmds */ |
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372 | struct radeon_tmds_pll tmds_pll[4]; |
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373 | }; |
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374 | |||
1321 | serge | 375 | struct radeon_encoder_ext_tmds { |
376 | /* tmds over dvo */ |
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377 | struct radeon_i2c_chan *i2c_bus; |
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378 | uint8_t slave_addr; |
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379 | enum radeon_dvo_chip dvo_chip; |
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380 | }; |
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381 | |||
1268 | serge | 382 | /* spread spectrum */ |
1117 | serge | 383 | struct radeon_encoder_atom_dig { |
1963 | serge | 384 | bool linkb; |
1117 | serge | 385 | /* atom dig */ |
386 | bool coherent_mode; |
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1963 | serge | 387 | int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB, etc. */ |
388 | /* atom lvds/edp */ |
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389 | uint32_t lcd_misc; |
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1117 | serge | 390 | uint16_t panel_pwr_delay; |
1963 | serge | 391 | uint32_t lcd_ss_id; |
1117 | serge | 392 | /* panel mode */ |
1268 | serge | 393 | struct drm_display_mode native_mode; |
1963 | serge | 394 | struct backlight_device *bl_dev; |
395 | int dpms_mode; |
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396 | uint8_t backlight_level; |
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2997 | Serge | 397 | int panel_mode; |
398 | struct radeon_afmt *afmt; |
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1117 | serge | 399 | }; |
400 | |||
1179 | serge | 401 | struct radeon_encoder_atom_dac { |
402 | enum radeon_tv_std tv_std; |
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403 | }; |
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404 | |||
1117 | serge | 405 | struct radeon_encoder { |
406 | struct drm_encoder base; |
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1963 | serge | 407 | uint32_t encoder_enum; |
1117 | serge | 408 | uint32_t encoder_id; |
409 | uint32_t devices; |
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1179 | serge | 410 | uint32_t active_device; |
1117 | serge | 411 | uint32_t flags; |
412 | uint32_t pixel_clock; |
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413 | enum radeon_rmx_type rmx_type; |
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1963 | serge | 414 | enum radeon_underscan_type underscan_type; |
415 | uint32_t underscan_hborder; |
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416 | uint32_t underscan_vborder; |
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1268 | serge | 417 | struct drm_display_mode native_mode; |
1117 | serge | 418 | void *enc_priv; |
1963 | serge | 419 | int audio_polling_active; |
420 | bool is_ext_encoder; |
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421 | u16 caps; |
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1117 | serge | 422 | }; |
423 | |||
424 | struct radeon_connector_atom_dig { |
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425 | uint32_t igp_lane_info; |
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1321 | serge | 426 | /* displayport */ |
427 | struct radeon_i2c_chan *dp_i2c_bus; |
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3192 | Serge | 428 | u8 dpcd[DP_RECEIVER_CAP_SIZE]; |
1321 | serge | 429 | u8 dp_sink_type; |
430 | int dp_clock; |
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431 | int dp_lane_count; |
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1963 | serge | 432 | bool edp_on; |
1117 | serge | 433 | }; |
434 | |||
1321 | serge | 435 | struct radeon_gpio_rec { |
436 | bool valid; |
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437 | u8 id; |
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438 | u32 reg; |
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439 | u32 mask; |
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440 | }; |
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441 | |||
442 | struct radeon_hpd { |
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443 | enum radeon_hpd_id hpd; |
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444 | u8 plugged_state; |
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445 | struct radeon_gpio_rec gpio; |
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446 | }; |
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447 | |||
1963 | serge | 448 | struct radeon_router { |
449 | u32 router_id; |
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450 | struct radeon_i2c_bus_rec i2c_info; |
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451 | u8 i2c_addr; |
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452 | /* i2c mux */ |
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453 | bool ddc_valid; |
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454 | u8 ddc_mux_type; |
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455 | u8 ddc_mux_control_pin; |
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456 | u8 ddc_mux_state; |
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457 | /* clock/data mux */ |
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458 | bool cd_valid; |
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459 | u8 cd_mux_type; |
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460 | u8 cd_mux_control_pin; |
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461 | u8 cd_mux_state; |
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462 | }; |
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463 | |||
1117 | serge | 464 | struct radeon_connector { |
465 | struct drm_connector base; |
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466 | uint32_t connector_id; |
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467 | uint32_t devices; |
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468 | struct radeon_i2c_chan *ddc_bus; |
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1963 | serge | 469 | /* some systems have an hdmi and vga port with a shared ddc line */ |
1268 | serge | 470 | bool shared_ddc; |
1179 | serge | 471 | bool use_digital; |
472 | /* we need to mind the EDID between detect |
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473 | and get modes due to analog/digital/tvencoder */ |
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474 | struct edid *edid; |
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1117 | serge | 475 | void *con_priv; |
1179 | serge | 476 | bool dac_load_detect; |
2997 | Serge | 477 | bool detected_by_load; /* if the connection status was determined by load */ |
1268 | serge | 478 | uint16_t connector_object_id; |
1321 | serge | 479 | struct radeon_hpd hpd; |
1963 | serge | 480 | struct radeon_router router; |
481 | struct radeon_i2c_chan *router_bus; |
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1117 | serge | 482 | }; |
483 | |||
484 | struct radeon_framebuffer { |
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1123 | serge | 485 | struct drm_framebuffer base; |
486 | struct drm_gem_object *obj; |
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1117 | serge | 487 | }; |
488 | |||
2997 | Serge | 489 | #define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \ |
490 | ((em) == ATOM_ENCODER_MODE_DP_MST)) |
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1963 | serge | 491 | |
3764 | Serge | 492 | struct atom_clock_dividers { |
493 | u32 post_div; |
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494 | union { |
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495 | struct { |
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496 | #ifdef __BIG_ENDIAN |
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497 | u32 reserved : 6; |
||
498 | u32 whole_fb_div : 12; |
||
499 | u32 frac_fb_div : 14; |
||
500 | #else |
||
501 | u32 frac_fb_div : 14; |
||
502 | u32 whole_fb_div : 12; |
||
503 | u32 reserved : 6; |
||
504 | #endif |
||
505 | }; |
||
506 | u32 fb_div; |
||
507 | }; |
||
508 | u32 ref_div; |
||
509 | bool enable_post_div; |
||
510 | bool enable_dithen; |
||
511 | u32 vco_mode; |
||
512 | u32 real_clock; |
||
513 | }; |
||
514 | |||
1404 | serge | 515 | extern enum radeon_tv_std |
516 | radeon_combios_get_tv_info(struct radeon_device *rdev); |
||
517 | extern enum radeon_tv_std |
||
518 | radeon_atombios_get_tv_info(struct radeon_device *rdev); |
||
519 | |||
1963 | serge | 520 | extern struct drm_connector * |
521 | radeon_get_connector_for_encoder(struct drm_encoder *encoder); |
||
2997 | Serge | 522 | extern struct drm_connector * |
523 | radeon_get_connector_for_encoder_init(struct drm_encoder *encoder); |
||
524 | extern bool radeon_dig_monitor_is_duallink(struct drm_encoder *encoder, |
||
525 | u32 pixel_clock); |
||
1963 | serge | 526 | |
2997 | Serge | 527 | extern u16 radeon_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder); |
528 | extern u16 radeon_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector); |
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1963 | serge | 529 | extern bool radeon_connector_encoder_is_hbr2(struct drm_connector *connector); |
530 | extern bool radeon_connector_is_dp12_capable(struct drm_connector *connector); |
||
2997 | Serge | 531 | extern int radeon_get_monitor_bpc(struct drm_connector *connector); |
1963 | serge | 532 | |
1321 | serge | 533 | extern void radeon_connector_hotplug(struct drm_connector *connector); |
1963 | serge | 534 | extern int radeon_dp_mode_valid_helper(struct drm_connector *connector, |
1321 | serge | 535 | struct drm_display_mode *mode); |
536 | extern void radeon_dp_set_link_config(struct drm_connector *connector, |
||
2997 | Serge | 537 | const struct drm_display_mode *mode); |
1963 | serge | 538 | extern void radeon_dp_link_train(struct drm_encoder *encoder, |
1321 | serge | 539 | struct drm_connector *connector); |
2997 | Serge | 540 | extern bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector); |
1321 | serge | 541 | extern u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector); |
542 | extern bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector); |
||
2997 | Serge | 543 | extern int radeon_dp_get_panel_mode(struct drm_encoder *encoder, |
544 | struct drm_connector *connector); |
||
1963 | serge | 545 | extern void atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode); |
546 | extern void radeon_atom_encoder_init(struct radeon_device *rdev); |
||
2997 | Serge | 547 | extern void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev); |
1321 | serge | 548 | extern void atombios_dig_transmitter_setup(struct drm_encoder *encoder, |
549 | int action, uint8_t lane_num, |
||
550 | uint8_t lane_set); |
||
1986 | serge | 551 | extern void radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder); |
2997 | Serge | 552 | extern struct drm_encoder *radeon_get_external_encoder(struct drm_encoder *encoder); |
1321 | serge | 553 | extern int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode, |
1963 | serge | 554 | u8 write_byte, u8 *read_byte); |
1321 | serge | 555 | |
1963 | serge | 556 | extern void radeon_i2c_init(struct radeon_device *rdev); |
557 | extern void radeon_i2c_fini(struct radeon_device *rdev); |
||
558 | extern void radeon_combios_i2c_init(struct radeon_device *rdev); |
||
559 | extern void radeon_atombios_i2c_init(struct radeon_device *rdev); |
||
560 | extern void radeon_i2c_add(struct radeon_device *rdev, |
||
561 | struct radeon_i2c_bus_rec *rec, |
||
562 | const char *name); |
||
563 | extern struct radeon_i2c_chan *radeon_i2c_lookup(struct radeon_device *rdev, |
||
564 | struct radeon_i2c_bus_rec *i2c_bus); |
||
1321 | serge | 565 | extern struct radeon_i2c_chan *radeon_i2c_create_dp(struct drm_device *dev, |
566 | struct radeon_i2c_bus_rec *rec, |
||
567 | const char *name); |
||
1117 | serge | 568 | extern struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev, |
569 | struct radeon_i2c_bus_rec *rec, |
||
570 | const char *name); |
||
571 | extern void radeon_i2c_destroy(struct radeon_i2c_chan *i2c); |
||
1430 | serge | 572 | extern void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus, |
1321 | serge | 573 | u8 slave_addr, |
574 | u8 addr, |
||
575 | u8 *val); |
||
1430 | serge | 576 | extern void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c, |
1321 | serge | 577 | u8 slave_addr, |
578 | u8 addr, |
||
579 | u8 val); |
||
1963 | serge | 580 | extern void radeon_router_select_ddc_port(struct radeon_connector *radeon_connector); |
581 | extern void radeon_router_select_cd_port(struct radeon_connector *radeon_connector); |
||
3192 | Serge | 582 | extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector, bool use_aux); |
1117 | serge | 583 | extern int radeon_ddc_get_modes(struct radeon_connector *radeon_connector); |
584 | |||
1123 | serge | 585 | extern struct drm_encoder *radeon_best_encoder(struct drm_connector *connector); |
1117 | serge | 586 | |
1963 | serge | 587 | extern bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev, |
588 | struct radeon_atom_ss *ss, |
||
589 | int id); |
||
590 | extern bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev, |
||
591 | struct radeon_atom_ss *ss, |
||
592 | int id, u32 clock); |
||
593 | |||
594 | extern void radeon_compute_pll_legacy(struct radeon_pll *pll, |
||
1117 | serge | 595 | uint64_t freq, |
596 | uint32_t *dot_clock_p, |
||
597 | uint32_t *fb_div_p, |
||
598 | uint32_t *frac_fb_div_p, |
||
599 | uint32_t *ref_div_p, |
||
1404 | serge | 600 | uint32_t *post_div_p); |
1117 | serge | 601 | |
1963 | serge | 602 | extern void radeon_compute_pll_avivo(struct radeon_pll *pll, |
603 | u32 freq, |
||
604 | u32 *dot_clock_p, |
||
605 | u32 *fb_div_p, |
||
606 | u32 *frac_fb_div_p, |
||
607 | u32 *ref_div_p, |
||
608 | u32 *post_div_p); |
||
609 | |||
1321 | serge | 610 | extern void radeon_setup_encoder_clones(struct drm_device *dev); |
611 | |||
1117 | serge | 612 | struct drm_encoder *radeon_encoder_legacy_lvds_add(struct drm_device *dev, int bios_index); |
613 | struct drm_encoder *radeon_encoder_legacy_primary_dac_add(struct drm_device *dev, int bios_index, int with_tv); |
||
614 | struct drm_encoder *radeon_encoder_legacy_tv_dac_add(struct drm_device *dev, int bios_index, int with_tv); |
||
615 | struct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, int bios_index); |
||
616 | struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, int bios_index); |
||
1963 | serge | 617 | extern void atombios_dvo_setup(struct drm_encoder *encoder, int action); |
1321 | serge | 618 | extern void atombios_digital_setup(struct drm_encoder *encoder, int action); |
1117 | serge | 619 | extern int atombios_get_encoder_mode(struct drm_encoder *encoder); |
1963 | serge | 620 | extern bool atombios_set_edp_panel_power(struct drm_connector *connector, int action); |
1179 | serge | 621 | extern void radeon_encoder_set_active_device(struct drm_encoder *encoder); |
1117 | serge | 622 | |
623 | extern void radeon_crtc_load_lut(struct drm_crtc *crtc); |
||
624 | extern int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y, |
||
625 | struct drm_framebuffer *old_fb); |
||
1963 | serge | 626 | extern int atombios_crtc_set_base_atomic(struct drm_crtc *crtc, |
627 | struct drm_framebuffer *fb, |
||
628 | int x, int y, |
||
629 | enum mode_set_atomic state); |
||
1117 | serge | 630 | extern int atombios_crtc_mode_set(struct drm_crtc *crtc, |
631 | struct drm_display_mode *mode, |
||
632 | struct drm_display_mode *adjusted_mode, |
||
633 | int x, int y, |
||
634 | struct drm_framebuffer *old_fb); |
||
635 | extern void atombios_crtc_dpms(struct drm_crtc *crtc, int mode); |
||
636 | |||
637 | extern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y, |
||
638 | struct drm_framebuffer *old_fb); |
||
1963 | serge | 639 | extern int radeon_crtc_set_base_atomic(struct drm_crtc *crtc, |
640 | struct drm_framebuffer *fb, |
||
641 | int x, int y, |
||
642 | enum mode_set_atomic state); |
||
643 | extern int radeon_crtc_do_set_base(struct drm_crtc *crtc, |
||
644 | struct drm_framebuffer *fb, |
||
645 | int x, int y, int atomic); |
||
1117 | serge | 646 | extern int radeon_crtc_cursor_set(struct drm_crtc *crtc, |
647 | struct drm_file *file_priv, |
||
648 | uint32_t handle, |
||
649 | uint32_t width, |
||
650 | uint32_t height); |
||
651 | extern int radeon_crtc_cursor_move(struct drm_crtc *crtc, |
||
652 | int x, int y); |
||
653 | |||
1963 | serge | 654 | extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc, |
655 | int *vpos, int *hpos); |
||
656 | |||
1430 | serge | 657 | extern bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev); |
658 | extern struct edid * |
||
1963 | serge | 659 | radeon_bios_get_hardcoded_edid(struct radeon_device *rdev); |
1117 | serge | 660 | extern bool radeon_atom_get_clock_info(struct drm_device *dev); |
661 | extern bool radeon_combios_get_clock_info(struct drm_device *dev); |
||
662 | extern struct radeon_encoder_atom_dig * |
||
663 | radeon_atombios_get_lvds_info(struct radeon_encoder *encoder); |
||
1321 | serge | 664 | extern bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder, |
1179 | serge | 665 | struct radeon_encoder_int_tmds *tmds); |
1321 | serge | 666 | extern bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder, |
1179 | serge | 667 | struct radeon_encoder_int_tmds *tmds); |
1321 | serge | 668 | extern bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder, |
1179 | serge | 669 | struct radeon_encoder_int_tmds *tmds); |
1321 | serge | 670 | extern bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder, |
671 | struct radeon_encoder_ext_tmds *tmds); |
||
672 | extern bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder, |
||
673 | struct radeon_encoder_ext_tmds *tmds); |
||
1117 | serge | 674 | extern struct radeon_encoder_primary_dac * |
675 | radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder); |
||
676 | extern struct radeon_encoder_tv_dac * |
||
677 | radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder); |
||
678 | extern struct radeon_encoder_lvds * |
||
679 | radeon_combios_get_lvds_info(struct radeon_encoder *encoder); |
||
680 | extern void radeon_combios_get_ext_tmds_info(struct radeon_encoder *encoder); |
||
681 | extern struct radeon_encoder_tv_dac * |
||
682 | radeon_combios_get_tv_dac_info(struct radeon_encoder *encoder); |
||
683 | extern struct radeon_encoder_primary_dac * |
||
684 | radeon_combios_get_primary_dac_info(struct radeon_encoder *encoder); |
||
1321 | serge | 685 | extern bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder); |
686 | extern void radeon_external_tmds_setup(struct drm_encoder *encoder); |
||
1117 | serge | 687 | extern void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock); |
688 | extern void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev); |
||
689 | extern void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock); |
||
690 | extern void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev); |
||
1179 | serge | 691 | extern void radeon_save_bios_scratch_regs(struct radeon_device *rdev); |
692 | extern void radeon_restore_bios_scratch_regs(struct radeon_device *rdev); |
||
1117 | serge | 693 | extern void |
694 | radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc); |
||
695 | extern void |
||
696 | radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on); |
||
697 | extern void |
||
698 | radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc); |
||
699 | extern void |
||
700 | radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on); |
||
701 | extern void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, |
||
702 | u16 blue, int regno); |
||
1221 | serge | 703 | extern void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, |
704 | u16 *blue, int regno); |
||
2997 | Serge | 705 | int radeon_framebuffer_init(struct drm_device *dev, |
1963 | serge | 706 | struct radeon_framebuffer *rfb, |
2997 | Serge | 707 | struct drm_mode_fb_cmd2 *mode_cmd, |
1117 | serge | 708 | struct drm_gem_object *obj); |
709 | |||
710 | int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb); |
||
711 | bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev); |
||
712 | bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev); |
||
713 | void radeon_atombios_init_crtc(struct drm_device *dev, |
||
714 | struct radeon_crtc *radeon_crtc); |
||
715 | void radeon_legacy_init_crtc(struct drm_device *dev, |
||
716 | struct radeon_crtc *radeon_crtc); |
||
717 | |||
718 | void radeon_get_clock_info(struct drm_device *dev); |
||
719 | |||
720 | extern bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev); |
||
721 | extern bool radeon_get_atom_connector_info_from_supported_devices_table(struct drm_device *dev); |
||
722 | |||
723 | void radeon_enc_destroy(struct drm_encoder *encoder); |
||
724 | void radeon_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj); |
||
725 | void radeon_combios_asic_init(struct drm_device *dev); |
||
1179 | serge | 726 | bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc, |
2997 | Serge | 727 | const struct drm_display_mode *mode, |
1179 | serge | 728 | struct drm_display_mode *adjusted_mode); |
1963 | serge | 729 | void radeon_panel_mode_fixup(struct drm_encoder *encoder, |
730 | struct drm_display_mode *adjusted_mode); |
||
1179 | serge | 731 | void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc); |
1123 | serge | 732 | |
1179 | serge | 733 | /* legacy tv */ |
734 | void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder, |
||
735 | uint32_t *h_total_disp, uint32_t *h_sync_strt_wid, |
||
736 | uint32_t *v_total_disp, uint32_t *v_sync_strt_wid); |
||
737 | void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder, |
||
738 | uint32_t *htotal_cntl, uint32_t *ppll_ref_div, |
||
739 | uint32_t *ppll_div_3, uint32_t *pixclks_cntl); |
||
740 | void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder, |
||
741 | uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div, |
||
742 | uint32_t *p2pll_div_0, uint32_t *pixclks_cntl); |
||
743 | void radeon_legacy_tv_mode_set(struct drm_encoder *encoder, |
||
744 | struct drm_display_mode *mode, |
||
745 | struct drm_display_mode *adjusted_mode); |
||
1963 | serge | 746 | |
747 | /* fbdev layer */ |
||
748 | int radeon_fbdev_init(struct radeon_device *rdev); |
||
749 | void radeon_fbdev_fini(struct radeon_device *rdev); |
||
750 | void radeon_fbdev_set_suspend(struct radeon_device *rdev, int state); |
||
751 | int radeon_fbdev_total_size(struct radeon_device *rdev); |
||
752 | bool radeon_fbdev_robj_is_fb(struct radeon_device *rdev, struct radeon_bo *robj); |
||
753 | |||
754 | void radeon_fb_output_poll_changed(struct radeon_device *rdev); |
||
755 | |||
756 | void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id); |
||
757 | |||
758 | int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp, bool tiled); |
||
1117 | serge | 759 | #endif><>><>><>><>><>><>><>><>><>><>><>><>><>><>><> |